[PATCH 0/3] ARM: dts: BCM5301X: Linksys EA9500 device tree changes

[PATCH 0/3] ARM: dts: BCM5301X: Linksys EA9500 device tree changes

[Vivek Unune]

1. Drop mmioreg mdio mux infavor of the pinmux
2. Add port5 and port7 which are connected to gmac0 & 1 respectively
3. Define fixed partitions

Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: "Rafał Miłecki" <zajec5@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vivek Unune <npcomplete13@gmail.com>

Vivek Unune (3):
  ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl
  ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7
  ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions

 .../boot/dts/bcm47094-linksys-panamera.dts    | 216 +++++++++++-------
 arch/arm/boot/dts/bcm5301x.dtsi               |   4 +-
 2 files changed, 137 insertions(+), 83 deletions(-)

-- 
2.25.1

[PATCH 0/3] ARM: dts: BCM5301X: Linksys EA9500 device tree changes

[Vivek Unune]

1. Drop mmioreg mdio mux infavor of the pinmux
2. Add port5 and port7 which are connected to gmac0 & 1 respectively
3. Define fixed partitions

Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: "Rafał Miłecki" <zajec5@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Vivek Unune <npcomplete13@gmail.com>

Vivek Unune (3):
  ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl
  ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7
  ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions

 .../boot/dts/bcm47094-linksys-panamera.dts    | 216 +++++++++++-------
 arch/arm/boot/dts/bcm5301x.dtsi               |   4 +-
 2 files changed, 137 insertions(+), 83 deletions(-)

-- 
2.25.1


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[PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

Forgo the use of mmioreg mdio mux infavor of the pinctrl

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 153 +++++++++---------
 arch/arm/boot/dts/bcm5301x.dtsi               |   4 +-
 2 files changed, 74 insertions(+), 83 deletions(-)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 0faae8950375..f8443d9f86b7 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -122,87 +122,6 @@ bluebar8 {
 			gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
 		};
 	};
-
-	mdio-bus-mux {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* BIT(9) = 1 => external mdio */
-		mdio_ext: mdio@200 {
-			reg = <0x200>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-
-	mdio-mii-mux {
-		compatible = "mdio-mux-mmioreg";
-		mdio-parent-bus = <&mdio_ext>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x1800c1c0 0x4>;
-
-		/* BIT(6) = mdc, BIT(7) = mdio */
-		mux-mask = <0xc0>;
-
-		mdio-mii@0 {
-			/* Enable MII function */
-			reg = <0x0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch@0  {
-				compatible = "brcm,bcm53125";
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
-				reset-names = "robo_reset";
-				reg = <0>;
-				dsa,member = <1 0>;
-
-				ports {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					port@0 {
-						reg = <0>;
-						label = "lan1";
-					};
-
-					port@1 {
-						reg = <1>;
-						label = "lan5";
-					};
-
-					port@2 {
-						reg = <2>;
-						label = "lan2";
-					};
-
-					port@3 {
-						reg = <3>;
-						label = "lan6";
-					};
-
-					port@4 {
-						reg = <4>;
-						label = "lan3";
-					};
-
-					sw1_p8: port@8 {
-						reg = <8>;
-						ethernet = <&sw0_p0>;
-						label = "cpu";
-
-						fixed-link {
-							speed = <1000>;
-							full-duplex;
-						};
-					};
-				};
-			};
-		};
-	};
 };
 
 &usb2 {
@@ -265,6 +184,78 @@ fixed-link {
 	};
 };
 
+&pinctrl {
+	compatible = "brcm,bcm4709-pinmux";
+
+	pinmux_mdio: mdio {
+		groups = "mdio_grp";
+		function = "mdio";
+	};
+};
+
+&mdio_bus_mux {
+
+	/* BIT(9) = 1 => external mdio */
+	mdio@200 {
+		reg = <0x200>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0  {
+			compatible = "brcm,bcm53125";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+			reset-names = "robo_reset";
+			reg = <0>;
+			dsa,member = <1 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinmux_mdio>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					label = "lan1";
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "lan5";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "lan2";
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "lan6";
+				};
+
+				port@4 {
+					reg = <4>;
+					label = "lan3";
+				};
+
+				sw1_p8: port@8 {
+					reg = <8>;
+					ethernet = <&sw0_p0>;
+					label = "cpu";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+};
+
 &usb3_phy {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 9d9e8fe3f6ae..1476375f88bb 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -369,7 +369,7 @@ mdio: mdio@18003000 {
 		#address-cells = <1>;
 	};
 
-	mdio-bus-mux@18003000 {
+	mdio_bus_mux: mdio-bus-mux@18003000 {
 		compatible = "mdio-mux-mmioreg";
 		mdio-parent-bus = <&mdio>;
 		#address-cells = <1>;
@@ -428,7 +428,7 @@ cru@100 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			pin-controller@1c0 {
+			pinctrl: pin-controller@1c0 {
 				compatible = "brcm,bcm4708-pinmux";
 				reg = <0x1c0 0x24>;
 				reg-names = "cru_gpio_control";
-- 
2.25.1

[PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

Forgo the use of mmioreg mdio mux infavor of the pinctrl

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 153 +++++++++---------
 arch/arm/boot/dts/bcm5301x.dtsi               |   4 +-
 2 files changed, 74 insertions(+), 83 deletions(-)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 0faae8950375..f8443d9f86b7 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -122,87 +122,6 @@ bluebar8 {
 			gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
 		};
 	};
-
-	mdio-bus-mux {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		/* BIT(9) = 1 => external mdio */
-		mdio_ext: mdio@200 {
-			reg = <0x200>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-
-	mdio-mii-mux {
-		compatible = "mdio-mux-mmioreg";
-		mdio-parent-bus = <&mdio_ext>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x1800c1c0 0x4>;
-
-		/* BIT(6) = mdc, BIT(7) = mdio */
-		mux-mask = <0xc0>;
-
-		mdio-mii@0 {
-			/* Enable MII function */
-			reg = <0x0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch@0  {
-				compatible = "brcm,bcm53125";
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
-				reset-names = "robo_reset";
-				reg = <0>;
-				dsa,member = <1 0>;
-
-				ports {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					port@0 {
-						reg = <0>;
-						label = "lan1";
-					};
-
-					port@1 {
-						reg = <1>;
-						label = "lan5";
-					};
-
-					port@2 {
-						reg = <2>;
-						label = "lan2";
-					};
-
-					port@3 {
-						reg = <3>;
-						label = "lan6";
-					};
-
-					port@4 {
-						reg = <4>;
-						label = "lan3";
-					};
-
-					sw1_p8: port@8 {
-						reg = <8>;
-						ethernet = <&sw0_p0>;
-						label = "cpu";
-
-						fixed-link {
-							speed = <1000>;
-							full-duplex;
-						};
-					};
-				};
-			};
-		};
-	};
 };
 
 &usb2 {
@@ -265,6 +184,78 @@ fixed-link {
 	};
 };
 
+&pinctrl {
+	compatible = "brcm,bcm4709-pinmux";
+
+	pinmux_mdio: mdio {
+		groups = "mdio_grp";
+		function = "mdio";
+	};
+};
+
+&mdio_bus_mux {
+
+	/* BIT(9) = 1 => external mdio */
+	mdio@200 {
+		reg = <0x200>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0  {
+			compatible = "brcm,bcm53125";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+			reset-names = "robo_reset";
+			reg = <0>;
+			dsa,member = <1 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinmux_mdio>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					label = "lan1";
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "lan5";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "lan2";
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "lan6";
+				};
+
+				port@4 {
+					reg = <4>;
+					label = "lan3";
+				};
+
+				sw1_p8: port@8 {
+					reg = <8>;
+					ethernet = <&sw0_p0>;
+					label = "cpu";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+};
+
 &usb3_phy {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 9d9e8fe3f6ae..1476375f88bb 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -369,7 +369,7 @@ mdio: mdio@18003000 {
 		#address-cells = <1>;
 	};
 
-	mdio-bus-mux@18003000 {
+	mdio_bus_mux: mdio-bus-mux@18003000 {
 		compatible = "mdio-mux-mmioreg";
 		mdio-parent-bus = <&mdio>;
 		#address-cells = <1>;
@@ -428,7 +428,7 @@ cru@100 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			pin-controller@1c0 {
+			pinctrl: pin-controller@1c0 {
 				compatible = "brcm,bcm4708-pinmux";
 				reg = <0x1c0 0x24>;
 				reg-names = "cru_gpio_control";
-- 
2.25.1


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Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Andrew Lunn]

On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> Forgo the use of mmioreg mdio mux infavor of the pinctrl

Hi Vivek

Could you add some more details please. I don't know this
hardware. I'm assuming there are two MDIO busses, external as talked
about in the comments, and an internal one? And for this hardware you
only need one of them? But i don't see what pinmux has to do with
this?

Thanks
	Andrew
 

Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Andrew Lunn]

On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> Forgo the use of mmioreg mdio mux infavor of the pinctrl

Hi Vivek

Could you add some more details please. I don't know this
hardware. I'm assuming there are two MDIO busses, external as talked
about in the comments, and an internal one? And for this hardware you
only need one of them? But i don't see what pinmux has to do with
this?

Thanks
	Andrew
 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote:
> On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> > Forgo the use of mmioreg mdio mux infavor of the pinctrl
> 
> Hi Vivek
> 
> Could you add some more details please. I don't know this
> hardware. I'm assuming there are two MDIO busses, external as talked
> about in the comments, and an internal one? And for this hardware you
> only need one of them? But i don't see what pinmux has to do with
> this?
Hi Andrew,

There are indeed two mdio busses. To access the external bus, 9th bit
of the mdio register has to be set. And to enable mii function,
one has to set the registers 6 & 7 which is part of the pin controller.
Earlier the pin controller was not defined and I resorted to use a
combination of memory mapped io mux to change desired bits.

Now that we have a pin controller - which is resposnsible for other 
functionality such as pwm, i2c, uart2, it makes sense to have a consistent
device tree

Hope this helps,

Vivek


> 
> Thanks
> 	Andrew
>  

Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote:
> On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> > Forgo the use of mmioreg mdio mux infavor of the pinctrl
> 
> Hi Vivek
> 
> Could you add some more details please. I don't know this
> hardware. I'm assuming there are two MDIO busses, external as talked
> about in the comments, and an internal one? And for this hardware you
> only need one of them? But i don't see what pinmux has to do with
> this?
Hi Andrew,

There are indeed two mdio busses. To access the external bus, 9th bit
of the mdio register has to be set. And to enable mii function,
one has to set the registers 6 & 7 which is part of the pin controller.
Earlier the pin controller was not defined and I resorted to use a
combination of memory mapped io mux to change desired bits.

Now that we have a pin controller - which is resposnsible for other 
functionality such as pwm, i2c, uart2, it makes sense to have a consistent
device tree

Hope this helps,

Vivek


> 
> Thanks
> 	Andrew
>  

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linux-arm-kernel mailing list
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Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Andrew Lunn]

On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote:
> On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote:
> > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> > > Forgo the use of mmioreg mdio mux infavor of the pinctrl
> > 
> > Hi Vivek
> > 
> > Could you add some more details please. I don't know this
> > hardware. I'm assuming there are two MDIO busses, external as talked
> > about in the comments, and an internal one? And for this hardware you
> > only need one of them? But i don't see what pinmux has to do with
> > this?
> Hi Andrew,
> 
> There are indeed two mdio busses. To access the external bus, 9th bit
> of the mdio register has to be set. And to enable mii function,
> one has to set the registers 6 & 7 which is part of the pin controller.
> Earlier the pin controller was not defined and I resorted to use a
> combination of memory mapped io mux to change desired bits.
> 
> Now that we have a pin controller - which is resposnsible for other 
> functionality such as pwm, i2c, uart2, it makes sense to have a consistent
> device tree

What makes it confusing is that you make multiple changes at once. It
would be easier to follow if you added the pinmux and removed the
mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a
second patch rearrange the mdio-bus-mux. Small simple steps, with good
commit messages are much easier to follow and say, Yes, this is
correct.

	Andrew

Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Andrew Lunn]

On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote:
> On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote:
> > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> > > Forgo the use of mmioreg mdio mux infavor of the pinctrl
> > 
> > Hi Vivek
> > 
> > Could you add some more details please. I don't know this
> > hardware. I'm assuming there are two MDIO busses, external as talked
> > about in the comments, and an internal one? And for this hardware you
> > only need one of them? But i don't see what pinmux has to do with
> > this?
> Hi Andrew,
> 
> There are indeed two mdio busses. To access the external bus, 9th bit
> of the mdio register has to be set. And to enable mii function,
> one has to set the registers 6 & 7 which is part of the pin controller.
> Earlier the pin controller was not defined and I resorted to use a
> combination of memory mapped io mux to change desired bits.
> 
> Now that we have a pin controller - which is resposnsible for other 
> functionality such as pwm, i2c, uart2, it makes sense to have a consistent
> device tree

What makes it confusing is that you make multiple changes at once. It
would be easier to follow if you added the pinmux and removed the
mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a
second patch rearrange the mdio-bus-mux. Small simple steps, with good
commit messages are much easier to follow and say, Yes, this is
correct.

	Andrew

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Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Thu, Oct 08, 2020 at 02:26:21AM +0200, Andrew Lunn wrote:
> On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote:
> > On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote:
> > > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> > > > Forgo the use of mmioreg mdio mux infavor of the pinctrl
> > > 
> > > Hi Vivek
> > > 
> > > Could you add some more details please. I don't know this
> > > hardware. I'm assuming there are two MDIO busses, external as talked
> > > about in the comments, and an internal one? And for this hardware you
> > > only need one of them? But i don't see what pinmux has to do with
> > > this?
> > Hi Andrew,
> > 
> > There are indeed two mdio busses. To access the external bus, 9th bit
> > of the mdio register has to be set. And to enable mii function,
> > one has to set the registers 6 & 7 which is part of the pin controller.
> > Earlier the pin controller was not defined and I resorted to use a
> > combination of memory mapped io mux to change desired bits.
> > 
> > Now that we have a pin controller - which is resposnsible for other 
> > functionality such as pwm, i2c, uart2, it makes sense to have a consistent
> > device tree
> 
> What makes it confusing is that you make multiple changes at once. It
> would be easier to follow if you added the pinmux and removed the
> mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a
> second patch rearrange the mdio-bus-mux. Small simple steps, with good
> commit messages are much easier to follow and say, Yes, this is
> correct.
> 
Sure, le me declutter this.

Thanks,

Vivek

Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Thu, Oct 08, 2020 at 02:26:21AM +0200, Andrew Lunn wrote:
> On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote:
> > On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote:
> > > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote:
> > > > Forgo the use of mmioreg mdio mux infavor of the pinctrl
> > > 
> > > Hi Vivek
> > > 
> > > Could you add some more details please. I don't know this
> > > hardware. I'm assuming there are two MDIO busses, external as talked
> > > about in the comments, and an internal one? And for this hardware you
> > > only need one of them? But i don't see what pinmux has to do with
> > > this?
> > Hi Andrew,
> > 
> > There are indeed two mdio busses. To access the external bus, 9th bit
> > of the mdio register has to be set. And to enable mii function,
> > one has to set the registers 6 & 7 which is part of the pin controller.
> > Earlier the pin controller was not defined and I resorted to use a
> > combination of memory mapped io mux to change desired bits.
> > 
> > Now that we have a pin controller - which is resposnsible for other 
> > functionality such as pwm, i2c, uart2, it makes sense to have a consistent
> > device tree
> 
> What makes it confusing is that you make multiple changes at once. It
> would be easier to follow if you added the pinmux and removed the
> mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a
> second patch rearrange the mdio-bus-mux. Small simple steps, with good
> commit messages are much easier to follow and say, Yes, this is
> correct.
> 
Sure, le me declutter this.

Thanks,

Vivek

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[PATCH v2 0/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

  1. BCM47094 pinctrl - use correct driver and define mdio pins
  2. Linksys EA9500 make use of pinctrl and drop mdio-mii-mux

Vivek Unune (2):
  ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins
  ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>

 .../boot/dts/bcm47094-linksys-panamera.dts    | 26 +++----------------
 arch/arm/boot/dts/bcm47094.dtsi               |  9 +++++++
 arch/arm/boot/dts/bcm5301x.dtsi               |  2 +-
 3 files changed, 14 insertions(+), 23 deletions(-)

-- 
2.25.1

[PATCH v2 0/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

  1. BCM47094 pinctrl - use correct driver and define mdio pins
  2. Linksys EA9500 make use of pinctrl and drop mdio-mii-mux

Vivek Unune (2):
  ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins
  ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>

 .../boot/dts/bcm47094-linksys-panamera.dts    | 26 +++----------------
 arch/arm/boot/dts/bcm47094.dtsi               |  9 +++++++
 arch/arm/boot/dts/bcm5301x.dtsi               |  2 +-
 3 files changed, 14 insertions(+), 23 deletions(-)

-- 
2.25.1


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[PATCH v2 1/2] ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins

[Vivek Unune]

BCM47094 version of pinmux uses different driver and supports mdio
pinmux pins. Hence, use the correct driver and define the pins.

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
---
 arch/arm/boot/dts/bcm47094.dtsi | 9 +++++++++
 arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi
index cdc5ff593adb..747ca030435f 100644
--- a/arch/arm/boot/dts/bcm47094.dtsi
+++ b/arch/arm/boot/dts/bcm47094.dtsi
@@ -8,6 +8,15 @@
 / {
 };
 
+&pinctrl {
+	compatible = "brcm,bcm4709-pinmux";
+
+	pinmux_mdio: mdio {
+		groups = "mdio_grp";
+		function = "mdio";
+	};
+};
+
 &usb3_phy {
 	compatible = "brcm,ns-bx-usb3-phy";
 };
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 3e55ff4fb550..cfc08cdd590f 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -428,7 +428,7 @@ cru@100 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			pin-controller@1c0 {
+			pinctrl: pin-controller@1c0 {
 				compatible = "brcm,bcm4708-pinmux";
 				reg = <0x1c0 0x24>;
 				reg-names = "cru_gpio_control";
-- 
2.25.1

[PATCH v2 1/2] ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins

[Vivek Unune]

BCM47094 version of pinmux uses different driver and supports mdio
pinmux pins. Hence, use the correct driver and define the pins.

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
---
 arch/arm/boot/dts/bcm47094.dtsi | 9 +++++++++
 arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi
index cdc5ff593adb..747ca030435f 100644
--- a/arch/arm/boot/dts/bcm47094.dtsi
+++ b/arch/arm/boot/dts/bcm47094.dtsi
@@ -8,6 +8,15 @@
 / {
 };
 
+&pinctrl {
+	compatible = "brcm,bcm4709-pinmux";
+
+	pinmux_mdio: mdio {
+		groups = "mdio_grp";
+		function = "mdio";
+	};
+};
+
 &usb3_phy {
 	compatible = "brcm,ns-bx-usb3-phy";
 };
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 3e55ff4fb550..cfc08cdd590f 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -428,7 +428,7 @@ cru@100 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			pin-controller@1c0 {
+			pinctrl: pin-controller@1c0 {
 				compatible = "brcm,bcm4708-pinmux";
 				reg = <0x1c0 0x24>;
 				reg-names = "cru_gpio_control";
-- 
2.25.1


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Re: [PATCH v2 1/2] ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins

[Rafał Miłecki]

On Wed, 4 Nov 2020 at 21:30, Vivek Unune <npcomplete13@gmail.com> wrote:
> BCM47094 version of pinmux uses different driver and supports mdio
> pinmux pins. Hence, use the correct driver and define the pins.
>
> Signed-off-by: Vivek Unune <npcomplete13@gmail.com>

Subject and message are a bit confusing as it's actually a matter of
chipset specific binding and not a driver.

Change looks OK, thanks for handling that!

Acked-by: Rafał Miłecki <rafal@milecki.pl>

Re: [PATCH v2 1/2] ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins

[Rafał Miłecki]

On Wed, 4 Nov 2020 at 21:30, Vivek Unune <npcomplete13@gmail.com> wrote:
> BCM47094 version of pinmux uses different driver and supports mdio
> pinmux pins. Hence, use the correct driver and define the pins.
>
> Signed-off-by: Vivek Unune <npcomplete13@gmail.com>

Subject and message are a bit confusing as it's actually a matter of
chipset specific binding and not a driver.

Change looks OK, thanks for handling that!

Acked-by: Rafał Miłecki <rafal@milecki.pl>

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Re: [PATCH v2 1/2] ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins

[Florian Fainelli]

On 11/9/20 9:21 AM, Rafał Miłecki wrote:
> On Wed, 4 Nov 2020 at 21:30, Vivek Unune <npcomplete13@gmail.com> wrote:
>> BCM47094 version of pinmux uses different driver and supports mdio
>> pinmux pins. Hence, use the correct driver and define the pins.
>>
>> Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
> 
> Subject and message are a bit confusing as it's actually a matter of
> chipset specific binding and not a driver.
> 
> Change looks OK, thanks for handling that!
> 
> Acked-by: Rafał Miłecki <rafal@milecki.pl>
> 

Agreed, applied and fixed up the subject and commit message this way:

    ARM: dts: BCM5301X: Use corretc pinctrl compatible for 4709x

    BCM47094 version of pinmux uses different compatible and supports MDIO
    pinmux pins. Hence, use the correct compatible string and defines the
    MDIO pins group.

Thanks!
-- 
Florian

Re: [PATCH v2 1/2] ARM: dts: BCM5301X: pinctrl - use correct driver and define mdio pins

[Florian Fainelli]

On 11/9/20 9:21 AM, Rafał Miłecki wrote:
> On Wed, 4 Nov 2020 at 21:30, Vivek Unune <npcomplete13@gmail.com> wrote:
>> BCM47094 version of pinmux uses different driver and supports mdio
>> pinmux pins. Hence, use the correct driver and define the pins.
>>
>> Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
> 
> Subject and message are a bit confusing as it's actually a matter of
> chipset specific binding and not a driver.
> 
> Change looks OK, thanks for handling that!
> 
> Acked-by: Rafał Miłecki <rafal@milecki.pl>
> 

Agreed, applied and fixed up the subject and commit message this way:

    ARM: dts: BCM5301X: Use corretc pinctrl compatible for 4709x

    BCM47094 version of pinmux uses different compatible and supports MDIO
    pinmux pins. Hence, use the correct compatible string and defines the
    MDIO pins group.

Thanks!
-- 
Florian

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[PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

Now that we have a pin controller, use that instead of manuplating the
mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 26 +++----------------
 1 file changed, 4 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 507af23e227f..3bb3fe5bfbf8 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -123,33 +123,13 @@ bluebar8 {
 		};
 	};
 
-	mdio-bus-mux {
-		#address-cells = <1>;
-		#size-cells = <0>;
+	mdio-bus-mux@18003000 {
 
 		/* BIT(9) = 1 => external mdio */
-		mdio_ext: mdio@200 {
+		mdio@200 {
 			reg = <0x200>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-		};
-	};
-
-	mdio-mii-mux {
-		compatible = "mdio-mux-mmioreg";
-		mdio-parent-bus = <&mdio_ext>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x1800c1c0 0x4>;
-
-		/* BIT(6) = mdc, BIT(7) = mdio */
-		mux-mask = <0xc0>;
-
-		mdio-mii@0 {
-			/* Enable MII function */
-			reg = <0x0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 
 			switch@0  {
 				compatible = "brcm,bcm53125";
@@ -159,6 +139,8 @@ switch@0  {
 				reset-names = "robo_reset";
 				reg = <0>;
 				dsa,member = <1 0>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinmux_mdio>;
 
 				ports {
 					#address-cells = <1>;
-- 
2.25.1

[PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

Now that we have a pin controller, use that instead of manuplating the
mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 26 +++----------------
 1 file changed, 4 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 507af23e227f..3bb3fe5bfbf8 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -123,33 +123,13 @@ bluebar8 {
 		};
 	};
 
-	mdio-bus-mux {
-		#address-cells = <1>;
-		#size-cells = <0>;
+	mdio-bus-mux@18003000 {
 
 		/* BIT(9) = 1 => external mdio */
-		mdio_ext: mdio@200 {
+		mdio@200 {
 			reg = <0x200>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-		};
-	};
-
-	mdio-mii-mux {
-		compatible = "mdio-mux-mmioreg";
-		mdio-parent-bus = <&mdio_ext>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x1800c1c0 0x4>;
-
-		/* BIT(6) = mdc, BIT(7) = mdio */
-		mux-mask = <0xc0>;
-
-		mdio-mii@0 {
-			/* Enable MII function */
-			reg = <0x0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 
 			switch@0  {
 				compatible = "brcm,bcm53125";
@@ -159,6 +139,8 @@ switch@0  {
 				reset-names = "robo_reset";
 				reg = <0>;
 				dsa,member = <1 0>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinmux_mdio>;
 
 				ports {
 					#address-cells = <1>;
-- 
2.25.1


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Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Florian Fainelli]

On 11/4/2020 12:29 PM, Vivek Unune wrote:
> Now that we have a pin controller, use that instead of manuplating the
> mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux

I am a bit confused here as I thought the mux was intended to
dynamically switch the pins in order to support both internal and
external MDIO devices but given the register ranges that were used,
these were actually the pinmux configuration for the MDC and MDIO pins.

This does not break USB and/or PCIe PHY communication does it?
-- 
Florian

Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Florian Fainelli]

On 11/4/2020 12:29 PM, Vivek Unune wrote:
> Now that we have a pin controller, use that instead of manuplating the
> mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux

I am a bit confused here as I thought the mux was intended to
dynamically switch the pins in order to support both internal and
external MDIO devices but given the register ranges that were used,
these were actually the pinmux configuration for the MDC and MDIO pins.

This does not break USB and/or PCIe PHY communication does it?
-- 
Florian

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Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Wed, Nov 04, 2020 at 12:37:45PM -0800, Florian Fainelli wrote:
> 
> 
> On 11/4/2020 12:29 PM, Vivek Unune wrote:
> > Now that we have a pin controller, use that instead of manuplating the
> > mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> 
> I am a bit confused here as I thought the mux was intended to
> dynamically switch the pins in order to support both internal and
> external MDIO devices but given the register ranges that were used,
> these were actually the pinmux configuration for the MDC and MDIO pins.
> 
> This does not break USB and/or PCIe PHY communication does it?

Hi Florian,

The external and internal MDIO logic is controlled by mdio-bus-mux.
Which controls the BIT(9) of the mdio register. This stays.

The removal of mdio-mii-mux and it's replacement with usage of
pinctrl doesn't affect USB3 or PCIe. See below USB3 detection.

[ 4295.450118] usb 1-1: new high-speed USB device number 2 using ehci-platform
[ 4295.690183] usb 4-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 4295.721888] usb-storage 4-1:1.0: USB Mass Storage device detected
[ 4295.728349] scsi host0: usb-storage 4-1:1.0
[ 4296.811047] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra Fit        1.00 PQ: 0 ANSI: 6
[ 4296.821159] sd 0:0:0:0: [sda] 60063744 512-byte logical blocks: (30.8 GB/28.6 GiB)
[ 4296.829667] sd 0:0:0:0: [sda] Write Protect is off
[ 4296.834502] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
[ 4296.834864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 4296.852604] GPT:Primary header thinks Alt. header is not at the end of the disk.
[ 4296.860079] GPT:1540387 != 60063743
[ 4296.863586] GPT:Alternate GPT header not at the end of the disk.
[ 4296.869600] GPT:1540387 != 60063743
[ 4296.873090] GPT: Use GNU Parted to correct GPT errors.
[ 4296.878266]  sda: sda1 sda2
[ 4296.884416] sd 0:0:0:0: [sda] Attached SCSI removable disk


Thanks,

Vivek

Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Wed, Nov 04, 2020 at 12:37:45PM -0800, Florian Fainelli wrote:
> 
> 
> On 11/4/2020 12:29 PM, Vivek Unune wrote:
> > Now that we have a pin controller, use that instead of manuplating the
> > mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> 
> I am a bit confused here as I thought the mux was intended to
> dynamically switch the pins in order to support both internal and
> external MDIO devices but given the register ranges that were used,
> these were actually the pinmux configuration for the MDC and MDIO pins.
> 
> This does not break USB and/or PCIe PHY communication does it?

Hi Florian,

The external and internal MDIO logic is controlled by mdio-bus-mux.
Which controls the BIT(9) of the mdio register. This stays.

The removal of mdio-mii-mux and it's replacement with usage of
pinctrl doesn't affect USB3 or PCIe. See below USB3 detection.

[ 4295.450118] usb 1-1: new high-speed USB device number 2 using ehci-platform
[ 4295.690183] usb 4-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 4295.721888] usb-storage 4-1:1.0: USB Mass Storage device detected
[ 4295.728349] scsi host0: usb-storage 4-1:1.0
[ 4296.811047] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra Fit        1.00 PQ: 0 ANSI: 6
[ 4296.821159] sd 0:0:0:0: [sda] 60063744 512-byte logical blocks: (30.8 GB/28.6 GiB)
[ 4296.829667] sd 0:0:0:0: [sda] Write Protect is off
[ 4296.834502] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
[ 4296.834864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 4296.852604] GPT:Primary header thinks Alt. header is not at the end of the disk.
[ 4296.860079] GPT:1540387 != 60063743
[ 4296.863586] GPT:Alternate GPT header not at the end of the disk.
[ 4296.869600] GPT:1540387 != 60063743
[ 4296.873090] GPT: Use GNU Parted to correct GPT errors.
[ 4296.878266]  sda: sda1 sda2
[ 4296.884416] sd 0:0:0:0: [sda] Attached SCSI removable disk


Thanks,

Vivek

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Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Wed, Nov 4, 2020 at 3:58 PM Vivek Unune <npcomplete13@gmail.com> wrote:
>
> On Wed, Nov 04, 2020 at 12:37:45PM -0800, Florian Fainelli wrote:
> >
> >
> > On 11/4/2020 12:29 PM, Vivek Unune wrote:
> > > Now that we have a pin controller, use that instead of manuplating the
> > > mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> >
> > I am a bit confused here as I thought the mux was intended to
> > dynamically switch the pins in order to support both internal and
> > external MDIO devices but given the register ranges that were used,
> > these were actually the pinmux configuration for the MDC and MDIO pins.
> >
> > This does not break USB and/or PCIe PHY communication does it?
>
> Hi Florian,
>
> The external and internal MDIO logic is controlled by mdio-bus-mux.
> Which controls the BIT(9) of the mdio register. This stays.
>
> The removal of mdio-mii-mux and it's replacement with usage of
> pinctrl doesn't affect USB3 or PCIe. See below USB3 detection.
>
> [ 4295.450118] usb 1-1: new high-speed USB device number 2 using ehci-platform
> [ 4295.690183] usb 4-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
> [ 4295.721888] usb-storage 4-1:1.0: USB Mass Storage device detected
> [ 4295.728349] scsi host0: usb-storage 4-1:1.0
> [ 4296.811047] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra Fit        1.00 PQ: 0 ANSI: 6
> [ 4296.821159] sd 0:0:0:0: [sda] 60063744 512-byte logical blocks: (30.8 GB/28.6 GiB)
> [ 4296.829667] sd 0:0:0:0: [sda] Write Protect is off
> [ 4296.834502] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
> [ 4296.834864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
> [ 4296.852604] GPT:Primary header thinks Alt. header is not at the end of the disk.
> [ 4296.860079] GPT:1540387 != 60063743
> [ 4296.863586] GPT:Alternate GPT header not at the end of the disk.
> [ 4296.869600] GPT:1540387 != 60063743
> [ 4296.873090] GPT: Use GNU Parted to correct GPT errors.
> [ 4296.878266]  sda: sda1 sda2
> [ 4296.884416] sd 0:0:0:0: [sda] Attached SCSI removable disk
>

Hi Florian,

Does this clarify your confusion?

Thanks,

Vivek

Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Wed, Nov 4, 2020 at 3:58 PM Vivek Unune <npcomplete13@gmail.com> wrote:
>
> On Wed, Nov 04, 2020 at 12:37:45PM -0800, Florian Fainelli wrote:
> >
> >
> > On 11/4/2020 12:29 PM, Vivek Unune wrote:
> > > Now that we have a pin controller, use that instead of manuplating the
> > > mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> >
> > I am a bit confused here as I thought the mux was intended to
> > dynamically switch the pins in order to support both internal and
> > external MDIO devices but given the register ranges that were used,
> > these were actually the pinmux configuration for the MDC and MDIO pins.
> >
> > This does not break USB and/or PCIe PHY communication does it?
>
> Hi Florian,
>
> The external and internal MDIO logic is controlled by mdio-bus-mux.
> Which controls the BIT(9) of the mdio register. This stays.
>
> The removal of mdio-mii-mux and it's replacement with usage of
> pinctrl doesn't affect USB3 or PCIe. See below USB3 detection.
>
> [ 4295.450118] usb 1-1: new high-speed USB device number 2 using ehci-platform
> [ 4295.690183] usb 4-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
> [ 4295.721888] usb-storage 4-1:1.0: USB Mass Storage device detected
> [ 4295.728349] scsi host0: usb-storage 4-1:1.0
> [ 4296.811047] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra Fit        1.00 PQ: 0 ANSI: 6
> [ 4296.821159] sd 0:0:0:0: [sda] 60063744 512-byte logical blocks: (30.8 GB/28.6 GiB)
> [ 4296.829667] sd 0:0:0:0: [sda] Write Protect is off
> [ 4296.834502] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
> [ 4296.834864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
> [ 4296.852604] GPT:Primary header thinks Alt. header is not at the end of the disk.
> [ 4296.860079] GPT:1540387 != 60063743
> [ 4296.863586] GPT:Alternate GPT header not at the end of the disk.
> [ 4296.869600] GPT:1540387 != 60063743
> [ 4296.873090] GPT: Use GNU Parted to correct GPT errors.
> [ 4296.878266]  sda: sda1 sda2
> [ 4296.884416] sd 0:0:0:0: [sda] Attached SCSI removable disk
>

Hi Florian,

Does this clarify your confusion?

Thanks,

Vivek

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Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Florian Fainelli]

On 11/9/2020 5:24 AM, Vivek Unune wrote:
> On Wed, Nov 4, 2020 at 3:58 PM Vivek Unune <npcomplete13@gmail.com> wrote:
>>
>> On Wed, Nov 04, 2020 at 12:37:45PM -0800, Florian Fainelli wrote:
>>>
>>>
>>> On 11/4/2020 12:29 PM, Vivek Unune wrote:
>>>> Now that we have a pin controller, use that instead of manuplating the
>>>> mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
>>>
>>> I am a bit confused here as I thought the mux was intended to
>>> dynamically switch the pins in order to support both internal and
>>> external MDIO devices but given the register ranges that were used,
>>> these were actually the pinmux configuration for the MDC and MDIO pins.
>>>
>>> This does not break USB and/or PCIe PHY communication does it?
>>
>> Hi Florian,
>>
>> The external and internal MDIO logic is controlled by mdio-bus-mux.
>> Which controls the BIT(9) of the mdio register. This stays.
>>
>> The removal of mdio-mii-mux and it's replacement with usage of
>> pinctrl doesn't affect USB3 or PCIe. See below USB3 detection.
>>
>> [ 4295.450118] usb 1-1: new high-speed USB device number 2 using ehci-platform
>> [ 4295.690183] usb 4-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
>> [ 4295.721888] usb-storage 4-1:1.0: USB Mass Storage device detected
>> [ 4295.728349] scsi host0: usb-storage 4-1:1.0
>> [ 4296.811047] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra Fit        1.00 PQ: 0 ANSI: 6
>> [ 4296.821159] sd 0:0:0:0: [sda] 60063744 512-byte logical blocks: (30.8 GB/28.6 GiB)
>> [ 4296.829667] sd 0:0:0:0: [sda] Write Protect is off
>> [ 4296.834502] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
>> [ 4296.834864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
>> [ 4296.852604] GPT:Primary header thinks Alt. header is not at the end of the disk.
>> [ 4296.860079] GPT:1540387 != 60063743
>> [ 4296.863586] GPT:Alternate GPT header not at the end of the disk.
>> [ 4296.869600] GPT:1540387 != 60063743
>> [ 4296.873090] GPT: Use GNU Parted to correct GPT errors.
>> [ 4296.878266]  sda: sda1 sda2
>> [ 4296.884416] sd 0:0:0:0: [sda] Attached SCSI removable disk
>>
> 
> Hi Florian,
> 
> Does this clarify your confusion?

It does, thank you for bearing with me, I will apply this later today.
-- 
Florian

Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Florian Fainelli]

On 11/9/2020 5:24 AM, Vivek Unune wrote:
> On Wed, Nov 4, 2020 at 3:58 PM Vivek Unune <npcomplete13@gmail.com> wrote:
>>
>> On Wed, Nov 04, 2020 at 12:37:45PM -0800, Florian Fainelli wrote:
>>>
>>>
>>> On 11/4/2020 12:29 PM, Vivek Unune wrote:
>>>> Now that we have a pin controller, use that instead of manuplating the
>>>> mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
>>>
>>> I am a bit confused here as I thought the mux was intended to
>>> dynamically switch the pins in order to support both internal and
>>> external MDIO devices but given the register ranges that were used,
>>> these were actually the pinmux configuration for the MDC and MDIO pins.
>>>
>>> This does not break USB and/or PCIe PHY communication does it?
>>
>> Hi Florian,
>>
>> The external and internal MDIO logic is controlled by mdio-bus-mux.
>> Which controls the BIT(9) of the mdio register. This stays.
>>
>> The removal of mdio-mii-mux and it's replacement with usage of
>> pinctrl doesn't affect USB3 or PCIe. See below USB3 detection.
>>
>> [ 4295.450118] usb 1-1: new high-speed USB device number 2 using ehci-platform
>> [ 4295.690183] usb 4-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
>> [ 4295.721888] usb-storage 4-1:1.0: USB Mass Storage device detected
>> [ 4295.728349] scsi host0: usb-storage 4-1:1.0
>> [ 4296.811047] scsi 0:0:0:0: Direct-Access     SanDisk  Ultra Fit        1.00 PQ: 0 ANSI: 6
>> [ 4296.821159] sd 0:0:0:0: [sda] 60063744 512-byte logical blocks: (30.8 GB/28.6 GiB)
>> [ 4296.829667] sd 0:0:0:0: [sda] Write Protect is off
>> [ 4296.834502] sd 0:0:0:0: [sda] Mode Sense: 43 00 00 00
>> [ 4296.834864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
>> [ 4296.852604] GPT:Primary header thinks Alt. header is not at the end of the disk.
>> [ 4296.860079] GPT:1540387 != 60063743
>> [ 4296.863586] GPT:Alternate GPT header not at the end of the disk.
>> [ 4296.869600] GPT:1540387 != 60063743
>> [ 4296.873090] GPT: Use GNU Parted to correct GPT errors.
>> [ 4296.878266]  sda: sda1 sda2
>> [ 4296.884416] sd 0:0:0:0: [sda] Attached SCSI removable disk
>>
> 
> Hi Florian,
> 
> Does this clarify your confusion?

It does, thank you for bearing with me, I will apply this later today.
-- 
Florian

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Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Florian Fainelli]

On Wed,  4 Nov 2020 15:29:52 -0500, Vivek Unune <npcomplete13@gmail.com> wrote:
> Now that we have a pin controller, use that instead of manuplating the
> mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> 
> Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
> ---

Applied to devicetree/next, thanks!
--
Florian

Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Florian Fainelli]

On Wed,  4 Nov 2020 15:29:52 -0500, Vivek Unune <npcomplete13@gmail.com> wrote:
> Now that we have a pin controller, use that instead of manuplating the
> mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> 
> Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
> ---

Applied to devicetree/next, thanks!
--
Florian

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Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Mon, Nov 9, 2020 at 12:24 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> On Wed,  4 Nov 2020 15:29:52 -0500, Vivek Unune <npcomplete13@gmail.com> wrote:
> > Now that we have a pin controller, use that instead of manuplating the
> > mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> >
> > Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
> > ---
>
> Applied to devicetree/next, thanks!
> --
> Florian

Thanks!

Re: [PATCH v2 2/2] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl

[Vivek Unune]

On Mon, Nov 9, 2020 at 12:24 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> On Wed,  4 Nov 2020 15:29:52 -0500, Vivek Unune <npcomplete13@gmail.com> wrote:
> > Now that we have a pin controller, use that instead of manuplating the
> > mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux
> >
> > Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
> > ---
>
> Applied to devicetree/next, thanks!
> --
> Florian

Thanks!

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[PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Vivek Unune]

Add port 5 and port 7 which are connected to gmac0 & 1 respectively
DSA driver will use port 5 as cpu port and this works as well.

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index f8443d9f86b7..b36ed0ead733 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -161,6 +161,28 @@ port@4 {
 			label = "wan";
 		};
 
+		port@5 {
+			reg = <5>;
+			ethernet = <&gmac0>;
+			label = "cpu";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		port@7 {
+			reg = <7>;
+			ethernet = <&gmac1>;
+			label = "cpu";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
 		port@8 {
 			reg = <8>;
 			ethernet = <&gmac2>;
-- 
2.25.1

[PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Vivek Unune]

Add port 5 and port 7 which are connected to gmac0 & 1 respectively
DSA driver will use port 5 as cpu port and this works as well.

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index f8443d9f86b7..b36ed0ead733 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -161,6 +161,28 @@ port@4 {
 			label = "wan";
 		};
 
+		port@5 {
+			reg = <5>;
+			ethernet = <&gmac0>;
+			label = "cpu";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		port@7 {
+			reg = <7>;
+			ethernet = <&gmac1>;
+			label = "cpu";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
 		port@8 {
 			reg = <8>;
 			ethernet = <&gmac2>;
-- 
2.25.1


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Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Andrew Lunn]

On Wed, Oct 07, 2020 at 03:01:51PM -0400, Vivek Unune wrote:
> Add port 5 and port 7 which are connected to gmac0 & 1 respectively
> DSA driver will use port 5 as cpu port and this works as well.

What port was used before this was added? The CPU port cannot be
changed because it can break user space, the code which is configuring
the master interface up.

    Andrew

Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Andrew Lunn]

On Wed, Oct 07, 2020 at 03:01:51PM -0400, Vivek Unune wrote:
> Add port 5 and port 7 which are connected to gmac0 & 1 respectively
> DSA driver will use port 5 as cpu port and this works as well.

What port was used before this was added? The CPU port cannot be
changed because it can break user space, the code which is configuring
the master interface up.

    Andrew

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Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Vivek Unune]

On Wed, Oct 07, 2020 at 11:03:27PM +0200, Andrew Lunn wrote:
> On Wed, Oct 07, 2020 at 03:01:51PM -0400, Vivek Unune wrote:
> > Add port 5 and port 7 which are connected to gmac0 & 1 respectively
> > DSA driver will use port 5 as cpu port and this works as well.
> 
> What port was used before this was added? The CPU port cannot be
> changed because it can break user space, the code which is configuring
> the master interface up.

Hi Andrew,

Port 8 was used before this. Factory firmware uses all three - 5, 7, 8 
I'm aware that current implementation of DSA driver does support
multiple CPU ports and uses the first one that is detected. DSA works
for either of the CPU ports.

In case of the non-DSA switch driver, which is enabled by default in
OpenWrt. Port 8 configuration will not work, since the non-DSA driver
uses first gmac core i.e. eth0. But since gmac0 isn't connected to
port 5, it doesn't work.

This router is currently not enabled in Openwrt and it doesn't
generate a firmware for public consumtion. So I'm sure this won't
affect anyone. Albeit, I've been generating custom firmware [1] for
this so I can get feedback on these changes I'm submitting.

With this patch series, I plan to enable firmware for this router
and free me up myself from building custom images. Moreover, the
router will start getting regular updates.

Thanks,

Vivek

[1] https://forum.openwrt.org/t/build-for-linksys-ea9500/1817

Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Vivek Unune]

On Wed, Oct 07, 2020 at 11:03:27PM +0200, Andrew Lunn wrote:
> On Wed, Oct 07, 2020 at 03:01:51PM -0400, Vivek Unune wrote:
> > Add port 5 and port 7 which are connected to gmac0 & 1 respectively
> > DSA driver will use port 5 as cpu port and this works as well.
> 
> What port was used before this was added? The CPU port cannot be
> changed because it can break user space, the code which is configuring
> the master interface up.

Hi Andrew,

Port 8 was used before this. Factory firmware uses all three - 5, 7, 8 
I'm aware that current implementation of DSA driver does support
multiple CPU ports and uses the first one that is detected. DSA works
for either of the CPU ports.

In case of the non-DSA switch driver, which is enabled by default in
OpenWrt. Port 8 configuration will not work, since the non-DSA driver
uses first gmac core i.e. eth0. But since gmac0 isn't connected to
port 5, it doesn't work.

This router is currently not enabled in Openwrt and it doesn't
generate a firmware for public consumtion. So I'm sure this won't
affect anyone. Albeit, I've been generating custom firmware [1] for
this so I can get feedback on these changes I'm submitting.

With this patch series, I plan to enable firmware for this router
and free me up myself from building custom images. Moreover, the
router will start getting regular updates.

Thanks,

Vivek

[1] https://forum.openwrt.org/t/build-for-linksys-ea9500/1817

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Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Andrew Lunn]

> This router is currently not enabled in Openwrt

You have to be careful here. Not everything runs OpenWRT. You cannot
break backwards compatibility in mainline, simple as that. You need to
ensure that mainline does not see a change in the CPU port.

    Andrew

Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Andrew Lunn]

> This router is currently not enabled in Openwrt

You have to be careful here. Not everything runs OpenWRT. You cannot
break backwards compatibility in mainline, simple as that. You need to
ensure that mainline does not see a change in the CPU port.

    Andrew

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Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Florian Fainelli]

On 10/7/2020 5:32 PM, Andrew Lunn wrote:
>> This router is currently not enabled in Openwrt
> 
> You have to be careful here. Not everything runs OpenWRT. You cannot
> break backwards compatibility in mainline, simple as that. You need to
> ensure that mainline does not see a change in the CPU port.

I don't think this is breaking anything, in premise all 3 CPU interfaces 
are completely interchangeable, with the notable fact that port 8 
happens to have the flow accelerator block available for re-circulation 
of packets if we wanted to support a NATP offload at some point in the 
future.

Vivek, maybe you can add ports 5 and 7 in the Device Tree and mark them 
as disabled for now.
-- 
Florian

Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Florian Fainelli]

On 10/7/2020 5:32 PM, Andrew Lunn wrote:
>> This router is currently not enabled in Openwrt
> 
> You have to be careful here. Not everything runs OpenWRT. You cannot
> break backwards compatibility in mainline, simple as that. You need to
> ensure that mainline does not see a change in the CPU port.

I don't think this is breaking anything, in premise all 3 CPU interfaces 
are completely interchangeable, with the notable fact that port 8 
happens to have the flow accelerator block available for re-circulation 
of packets if we wanted to support a NATP offload at some point in the 
future.

Vivek, maybe you can add ports 5 and 7 in the Device Tree and mark them 
as disabled for now.
-- 
Florian

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Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Vivek Unune]

Thanks Florian, I'll do that!

On Thu, Oct 8, 2020 at 10:58 AM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
>
>
> On 10/7/2020 5:32 PM, Andrew Lunn wrote:
> >> This router is currently not enabled in Openwrt
> >
> > You have to be careful here. Not everything runs OpenWRT. You cannot
> > break backwards compatibility in mainline, simple as that. You need to
> > ensure that mainline does not see a change in the CPU port.
>
> I don't think this is breaking anything, in premise all 3 CPU interfaces
> are completely interchangeable, with the notable fact that port 8
> happens to have the flow accelerator block available for re-circulation
> of packets if we wanted to support a NATP offload at some point in the
> future.
>
> Vivek, maybe you can add ports 5 and 7 in the Device Tree and mark them
> as disabled for now.
> --
> Florian

Re: [PATCH 2/3] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7

[Vivek Unune]

Thanks Florian, I'll do that!

On Thu, Oct 8, 2020 at 10:58 AM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
>
>
> On 10/7/2020 5:32 PM, Andrew Lunn wrote:
> >> This router is currently not enabled in Openwrt
> >
> > You have to be careful here. Not everything runs OpenWRT. You cannot
> > break backwards compatibility in mainline, simple as that. You need to
> > ensure that mainline does not see a change in the CPU port.
>
> I don't think this is breaking anything, in premise all 3 CPU interfaces
> are completely interchangeable, with the notable fact that port 8
> happens to have the flow accelerator block available for re-circulation
> of packets if we wanted to support a NATP offload at some point in the
> future.
>
> Vivek, maybe you can add ports 5 and 7 in the Device Tree and mark them
> as disabled for now.
> --
> Florian

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[PATCH 3/3] ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions

[Vivek Unune]

This router has dual paritions to store trx firmware image and
dual partitions for nvram. The second one for acts as a backup store.

When tested with OpenWrt, the default partition parser causes two issues:

1. It labels both nvram partitions as nvram. In factory, second one is
labeled devinfo.
2. It parses second trx image and tries to create second 'linux' partition
and fails with - cannot create another 'linux' partition

The following patch works around both of these issues.

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index b36ed0ead733..488e83c1780d 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -281,3 +281,44 @@ fixed-link {
 &usb3_phy {
 	status = "okay";
 };
+
+&nandcs {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "boot";
+			reg = <0x0000000 0x0080000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "nvram";
+			reg = <0x080000 0x0100000>;
+		};
+
+		partition@180000{
+			label = "devinfo";
+			reg = <0x0180000 0x080000>;
+		};
+
+		partition@200000 {
+			label = "firmware";
+			reg = <0x0200000 0x01D00000>;
+			compatible = "brcm,trx";
+		};
+
+		partition@1F00000 {
+			label = "failsafe";
+			reg = <0x01F00000 0x01D00000>;
+			read-only;
+		};
+
+		partition@0x5200000 {
+			label = "brcmnand";
+			reg = <0x05200000 0x02E00000>;
+		};
+	};
+};
-- 
2.25.1

[PATCH 3/3] ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions

[Vivek Unune]

This router has dual paritions to store trx firmware image and
dual partitions for nvram. The second one for acts as a backup store.

When tested with OpenWrt, the default partition parser causes two issues:

1. It labels both nvram partitions as nvram. In factory, second one is
labeled devinfo.
2. It parses second trx image and tries to create second 'linux' partition
and fails with - cannot create another 'linux' partition

The following patch works around both of these issues.

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
---
 .../boot/dts/bcm47094-linksys-panamera.dts    | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index b36ed0ead733..488e83c1780d 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -281,3 +281,44 @@ fixed-link {
 &usb3_phy {
 	status = "okay";
 };
+
+&nandcs {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "boot";
+			reg = <0x0000000 0x0080000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "nvram";
+			reg = <0x080000 0x0100000>;
+		};
+
+		partition@180000{
+			label = "devinfo";
+			reg = <0x0180000 0x080000>;
+		};
+
+		partition@200000 {
+			label = "firmware";
+			reg = <0x0200000 0x01D00000>;
+			compatible = "brcm,trx";
+		};
+
+		partition@1F00000 {
+			label = "failsafe";
+			reg = <0x01F00000 0x01D00000>;
+			read-only;
+		};
+
+		partition@0x5200000 {
+			label = "brcmnand";
+			reg = <0x05200000 0x02E00000>;
+		};
+	};
+};
-- 
2.25.1


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