From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: vandita.kulkarni@intel.com, uma.shankar@intel.com,
dri-devel@lists.freedesktop.org, swati2.sharma@intel.com
Subject: [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block
Date: Thu, 15 Oct 2020 16:22:55 +0530 [thread overview]
Message-ID: <20201015105259.27934-10-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20201015105259.27934-1-ankit.k.nautiyal@intel.com>
This patch parses HFVSDB fields for DSC1.2 capabilities of an
HDMI2.1 sink. These fields are required by a source to understand the
DSC capability of the sink, to set appropriate PPS parameters,
before transmitting compressed data stream.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_edid.c | 19 +++++++++++++++++++
include/drm/drm_connector.h | 32 ++++++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 8afb136e73f5..feee19657a7a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4889,10 +4889,29 @@ static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
{
struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
u8 max_frl_rate;
+ u8 dsc_max_frl_rate;
max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
&hdmi->max_frl_rate_per_lane);
+
+ hdmi->dsc_1p2 = db[11] & DRM_EDID_DSC_1P2;
+ hdmi->dsc_native_420 = db[11] & DRM_EDID_DSC_NATIVE_420;
+ hdmi->dsc_all_bpp = db[11] & DRM_EDID_DSC_ALL_BPP;
+
+ if (db[11] & DRM_EDID_DSC_16BPC)
+ hdmi->dsc_bpc_supported = 16;
+ else if (db[11] & DRM_EDID_DSC_12BPC)
+ hdmi->dsc_bpc_supported = 12;
+ else if (db[11] & DRM_EDID_DSC_10BPC)
+ hdmi->dsc_bpc_supported = 10;
+ else
+ hdmi->dsc_bpc_supported = 0;
+
+ dsc_max_frl_rate = db[12] & DRM_EDID_DSC_MAX_FRL_RATE;
+ drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi->dsc_max_lanes,
+ &hdmi->dsc_max_frl_rate_per_lane);
+ hdmi->dsc_total_chunk_kbytes = db[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
}
static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index f351bf10c076..7100012f9c0f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -213,6 +213,38 @@ struct drm_hdmi_info {
/** @max_lanes: supported by sink */
u8 max_lanes;
+
+ /** @dsc_1p2: flag for dsc1.2 support by sink */
+ bool dsc_1p2;
+
+ /** @dsc_native_420: Does sink support DSC with 4:2:0 compression */
+ bool dsc_native_420;
+
+ /**
+ * @dsc_all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2
+ * compressed formats
+ */
+ bool dsc_all_bpp;
+
+ /**
+ * @dsc_bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
+ */
+ u8 dsc_bpc_supported;
+
+ /** @dsc_max_slices: maximum number of Horizontal slices supported by */
+ u8 dsc_max_slices;
+
+ /** @dsc_clk_per_slice : max pixel clock in MHz supported per slice */
+ u8 dsc_clk_per_slice;
+
+ /** @dsc_max_lanes : dsc max lanes supported for Fixed rate Link training */
+ u8 dsc_max_lanes;
+
+ /** @dsc_max_frl_rate_per_lane : maximum frl rate with DSC per lane */
+ u8 dsc_max_frl_rate_per_lane;
+
+ /** @dsc_total_chunk_kbytes: max size of chunks in KBs supported per line*/
+ u8 dsc_total_chunk_kbytes;
};
/**
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block
Date: Thu, 15 Oct 2020 16:22:55 +0530 [thread overview]
Message-ID: <20201015105259.27934-10-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20201015105259.27934-1-ankit.k.nautiyal@intel.com>
This patch parses HFVSDB fields for DSC1.2 capabilities of an
HDMI2.1 sink. These fields are required by a source to understand the
DSC capability of the sink, to set appropriate PPS parameters,
before transmitting compressed data stream.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_edid.c | 19 +++++++++++++++++++
include/drm/drm_connector.h | 32 ++++++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 8afb136e73f5..feee19657a7a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4889,10 +4889,29 @@ static void drm_parse_hdmi_21_additional_fields(struct drm_connector *connector,
{
struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
u8 max_frl_rate;
+ u8 dsc_max_frl_rate;
max_frl_rate = db[7] & DRM_EDID_MAX_FRL_RATE_MASK;
drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
&hdmi->max_frl_rate_per_lane);
+
+ hdmi->dsc_1p2 = db[11] & DRM_EDID_DSC_1P2;
+ hdmi->dsc_native_420 = db[11] & DRM_EDID_DSC_NATIVE_420;
+ hdmi->dsc_all_bpp = db[11] & DRM_EDID_DSC_ALL_BPP;
+
+ if (db[11] & DRM_EDID_DSC_16BPC)
+ hdmi->dsc_bpc_supported = 16;
+ else if (db[11] & DRM_EDID_DSC_12BPC)
+ hdmi->dsc_bpc_supported = 12;
+ else if (db[11] & DRM_EDID_DSC_10BPC)
+ hdmi->dsc_bpc_supported = 10;
+ else
+ hdmi->dsc_bpc_supported = 0;
+
+ dsc_max_frl_rate = db[12] & DRM_EDID_DSC_MAX_FRL_RATE;
+ drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi->dsc_max_lanes,
+ &hdmi->dsc_max_frl_rate_per_lane);
+ hdmi->dsc_total_chunk_kbytes = db[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
}
static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index f351bf10c076..7100012f9c0f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -213,6 +213,38 @@ struct drm_hdmi_info {
/** @max_lanes: supported by sink */
u8 max_lanes;
+
+ /** @dsc_1p2: flag for dsc1.2 support by sink */
+ bool dsc_1p2;
+
+ /** @dsc_native_420: Does sink support DSC with 4:2:0 compression */
+ bool dsc_native_420;
+
+ /**
+ * @dsc_all_bpp: Does sink support all bpp with 4:4:4: or 4:2:2
+ * compressed formats
+ */
+ bool dsc_all_bpp;
+
+ /**
+ * @dsc_bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
+ */
+ u8 dsc_bpc_supported;
+
+ /** @dsc_max_slices: maximum number of Horizontal slices supported by */
+ u8 dsc_max_slices;
+
+ /** @dsc_clk_per_slice : max pixel clock in MHz supported per slice */
+ u8 dsc_clk_per_slice;
+
+ /** @dsc_max_lanes : dsc max lanes supported for Fixed rate Link training */
+ u8 dsc_max_lanes;
+
+ /** @dsc_max_frl_rate_per_lane : maximum frl rate with DSC per lane */
+ u8 dsc_max_frl_rate_per_lane;
+
+ /** @dsc_total_chunk_kbytes: max size of chunks in KBs supported per line*/
+ u8 dsc_total_chunk_kbytes;
};
/**
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-15 11:00 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-15 10:52 [RFC 00/13] Add support for DP-HDMI2.1 PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 10:52 ` [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 20:47 ` Shankar, Uma
2020-10-18 20:47 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:31 ` Nautiyal, Ankit K
2020-11-01 5:31 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 20:47 ` Shankar, Uma
2020-10-18 20:47 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:41 ` Nautiyal, Ankit K
2020-11-01 5:41 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 21:33 ` Shankar, Uma
2020-10-18 21:33 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:53 ` Nautiyal, Ankit K
2020-11-01 5:53 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 21:41 ` Shankar, Uma
2020-10-18 21:41 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:56 ` Nautiyal, Ankit K
2020-11-01 5:56 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:14 ` Shankar, Uma
2020-10-18 22:14 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:01 ` Nautiyal, Ankit K
2020-11-01 6:01 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 06/13] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:21 ` Shankar, Uma
2020-10-18 22:21 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:06 ` Nautiyal, Ankit K
2020-11-01 6:06 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 07/13] drm/dp_helper: Add support for link status and link recovery Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:37 ` Shankar, Uma
2020-10-18 22:37 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:18 ` Nautiyal, Ankit K
2020-11-01 6:18 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 08/13] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:49 ` Shankar, Uma
2020-10-18 22:49 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:26 ` Nautiyal, Ankit K
2020-11-01 6:26 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` Ankit Nautiyal [this message]
2020-10-15 10:52 ` [Intel-gfx] [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block Ankit Nautiyal
2020-10-18 23:01 ` Shankar, Uma
2020-10-18 23:01 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:52 ` Nautiyal, Ankit K
2020-11-01 6:52 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 23:19 ` Shankar, Uma
2020-10-18 23:19 ` [Intel-gfx] " Shankar, Uma
2020-11-01 7:00 ` Nautiyal, Ankit K
2020-11-01 7:00 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 14:19 ` kernel test robot
2020-10-15 14:19 ` [RFC PATCH] drm/i915: intel_dp_get_pcon_dsc_cap() can be static kernel test robot
2020-10-15 14:47 ` [Intel-gfx] [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder kernel test robot
2020-10-15 15:10 ` kernel test robot
2020-10-15 17:07 ` kernel test robot
2020-10-15 17:07 ` [PATCH] drm/i915: fix semicolon.cocci warnings kernel test robot
2020-10-18 23:32 ` [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Shankar, Uma
2020-10-18 23:32 ` [Intel-gfx] " Shankar, Uma
2020-10-18 23:34 ` Shankar, Uma
2020-10-18 23:34 ` [Intel-gfx] " Shankar, Uma
2020-11-01 7:14 ` Nautiyal, Ankit K
2020-11-01 7:14 ` [Intel-gfx] " Nautiyal, Ankit K
2020-11-01 7:13 ` Nautiyal, Ankit K
2020-11-01 7:13 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 10:52 ` [RFC 13/13] drm/i915: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 11:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev3) Patchwork
2020-10-15 11:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-15 12:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-15 13:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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