From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 23/26] coresight: etm4x: Detect system instructions support
Date: Tue, 10 Nov 2020 10:33:03 -0700 [thread overview]
Message-ID: <20201110173303.GB3429138@xps15> (raw)
In-Reply-To: <b4a4bd73-00c5-a921-3f01-7100d2a0edf8@arm.com>
On Tue, Nov 10, 2020 at 09:31:42AM +0000, Suzuki K Poulose wrote:
> On 11/9/20 8:22 PM, Mathieu Poirier wrote:
> > On Wed, Oct 28, 2020 at 10:09:42PM +0000, Suzuki K Poulose wrote:
> > > ETM v4.4 onwards adds support for system instruction access
> > > to the ETM. Detect the support on an ETM and switch to using the
> > > mode when available.
> > >
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > ---
> > > .../coresight/coresight-etm4x-core.c | 39 +++++++++++++++++++
> > > 1 file changed, 39 insertions(+)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > index 4bc2f15b6332..dc537b5612eb 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > @@ -675,6 +675,37 @@ static const struct coresight_ops etm4_cs_ops = {
> > > .source_ops = &etm4_source_ops,
> > > };
> > > +static inline bool cpu_supports_sysreg_trace(void)
> > > +{
> > > + u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> > > +
> > > + return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
> >
> > I would do:
> >
> > return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) == 1;
> >
> > Because any other value than '1' are reserved.
>
> Correct. However, this is something we follow for all ID features
> in the arm64 kernel and is clarified in the Arm ARM (ARM DDI 0487F.a) :
>
> "D13.1.3 Principles of the ID scheme for fields in ID registers"
>
> Which guarantees that a (field > n) implies, everything that field == n
> is implied. (Well there are exceptions listed in the section, but
> TRACEVER is not one of those). So this should cover an old kernel
> running on a future CPU, using the features that it understands.
> (See feature_matches() in arch/arm64/kernel/cpufeature.c, which is
> the fundamental logic to detect a feature).
>
While I haven't found anything conclusive in cpufeature.c, the documentation is
clear on the fact that versions are incremental and build on top of previous
ones. We can proceed with the current implementation.
> Please let me know if you're OK with the justification.
>
> Thanks for the review.
>
> Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v3 23/26] coresight: etm4x: Detect system instructions support
Date: Tue, 10 Nov 2020 10:33:03 -0700 [thread overview]
Message-ID: <20201110173303.GB3429138@xps15> (raw)
In-Reply-To: <b4a4bd73-00c5-a921-3f01-7100d2a0edf8@arm.com>
On Tue, Nov 10, 2020 at 09:31:42AM +0000, Suzuki K Poulose wrote:
> On 11/9/20 8:22 PM, Mathieu Poirier wrote:
> > On Wed, Oct 28, 2020 at 10:09:42PM +0000, Suzuki K Poulose wrote:
> > > ETM v4.4 onwards adds support for system instruction access
> > > to the ETM. Detect the support on an ETM and switch to using the
> > > mode when available.
> > >
> > > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > ---
> > > .../coresight/coresight-etm4x-core.c | 39 +++++++++++++++++++
> > > 1 file changed, 39 insertions(+)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > index 4bc2f15b6332..dc537b5612eb 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > @@ -675,6 +675,37 @@ static const struct coresight_ops etm4_cs_ops = {
> > > .source_ops = &etm4_source_ops,
> > > };
> > > +static inline bool cpu_supports_sysreg_trace(void)
> > > +{
> > > + u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
> > > +
> > > + return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
> >
> > I would do:
> >
> > return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) == 1;
> >
> > Because any other value than '1' are reserved.
>
> Correct. However, this is something we follow for all ID features
> in the arm64 kernel and is clarified in the Arm ARM (ARM DDI 0487F.a) :
>
> "D13.1.3 Principles of the ID scheme for fields in ID registers"
>
> Which guarantees that a (field > n) implies, everything that field == n
> is implied. (Well there are exceptions listed in the section, but
> TRACEVER is not one of those). So this should cover an old kernel
> running on a future CPU, using the features that it understands.
> (See feature_matches() in arch/arm64/kernel/cpufeature.c, which is
> the fundamental logic to detect a feature).
>
While I haven't found anything conclusive in cpufeature.c, the documentation is
clear on the fact that versions are incremental and build on top of previous
ones. We can proceed with the current implementation.
> Please let me know if you're OK with the justification.
>
> Thanks for the review.
>
> Suzuki
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next prev parent reply other threads:[~2020-11-10 17:33 UTC|newest]
Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 22:09 [PATCH v3 00/26] coresight: Support for ETM system instructions Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 01/26] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 02/26] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 03/26] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 04/26] coresight: etm4x: Fix accesses to TRCPROCSELR Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 05/26] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-02 21:46 ` Mathieu Poirier
2020-11-02 21:46 ` Mathieu Poirier
2020-11-02 22:04 ` Suzuki K Poulose
2020-11-02 22:04 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 07/26] coresight: Introduce device access abstraction Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 17:14 ` Mathieu Poirier
2020-11-03 17:14 ` Mathieu Poirier
2020-11-03 17:25 ` Mathieu Poirier
2020-11-03 17:25 ` Mathieu Poirier
2020-11-04 10:07 ` Suzuki K Poulose
2020-11-04 10:07 ` Suzuki K Poulose
2020-11-09 21:00 ` Mathieu Poirier
2020-11-09 21:00 ` Mathieu Poirier
2020-11-10 9:24 ` Suzuki K Poulose
2020-11-10 9:24 ` Suzuki K Poulose
2020-11-10 17:02 ` Mathieu Poirier
2020-11-10 17:02 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 08/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:03 ` Mathieu Poirier
2020-11-03 18:03 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 09/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:03 ` Mathieu Poirier
2020-11-03 18:03 ` Mathieu Poirier
2020-11-04 10:42 ` Suzuki K Poulose
2020-11-04 10:42 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 10/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:36 ` Mathieu Poirier
2020-11-03 18:36 ` Mathieu Poirier
2020-11-04 10:54 ` Suzuki K Poulose
2020-11-04 10:54 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 11/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 12/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 18:53 ` Mathieu Poirier
2020-11-03 18:53 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-03 19:03 ` Mathieu Poirier
2020-11-03 19:03 ` Mathieu Poirier
2020-11-03 19:04 ` Mathieu Poirier
2020-11-03 19:04 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 14/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-29 15:26 ` Suzuki K Poulose
2020-10-29 15:26 ` Suzuki K Poulose
2020-11-05 20:52 ` Mathieu Poirier
2020-11-05 20:52 ` Mathieu Poirier
2020-11-05 22:47 ` Suzuki K Poulose
2020-11-05 22:47 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 15/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-05 21:50 ` Mathieu Poirier
2020-11-05 21:50 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 17/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-05 21:55 ` Mathieu Poirier
2020-11-05 21:55 ` Mathieu Poirier
2020-11-09 9:40 ` Suzuki K Poulose
2020-11-09 9:40 ` Suzuki K Poulose
2020-11-09 17:42 ` Mathieu Poirier
2020-11-09 17:42 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 18/26] coresight: etm4x: Clean up " Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 18:52 ` Mathieu Poirier
2020-11-06 18:52 ` Mathieu Poirier
2020-11-09 9:44 ` Suzuki K Poulose
2020-11-09 9:44 ` Suzuki K Poulose
2020-11-10 23:15 ` Suzuki K Poulose
2020-11-10 23:15 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 19/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 20:34 ` Mathieu Poirier
2020-11-06 20:34 ` Mathieu Poirier
2020-11-09 9:48 ` Suzuki K Poulose
2020-11-09 9:48 ` Suzuki K Poulose
2020-11-09 17:48 ` Mathieu Poirier
2020-11-09 17:48 ` Mathieu Poirier
2020-11-06 20:46 ` Mathieu Poirier
2020-11-06 20:46 ` Mathieu Poirier
2020-11-10 10:47 ` Suzuki K Poulose
2020-11-10 10:47 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 20/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 21:11 ` Mathieu Poirier
2020-11-06 21:11 ` Mathieu Poirier
2020-11-09 9:51 ` Suzuki K Poulose
2020-11-09 9:51 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 21/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-06 21:42 ` Mathieu Poirier
2020-11-06 21:42 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 18:32 ` Mathieu Poirier
2020-11-09 18:32 ` Mathieu Poirier
2020-11-10 10:11 ` Suzuki K Poulose
2020-11-10 10:11 ` Suzuki K Poulose
2020-11-10 11:40 ` John Horley
2020-11-10 11:40 ` John Horley
2020-11-10 17:35 ` Mathieu Poirier
2020-11-10 17:35 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 23/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 20:22 ` Mathieu Poirier
2020-11-09 20:22 ` Mathieu Poirier
2020-11-10 9:31 ` Suzuki K Poulose
2020-11-10 9:31 ` Suzuki K Poulose
2020-11-10 17:33 ` Mathieu Poirier [this message]
2020-11-10 17:33 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 24/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 20:43 ` Mathieu Poirier
2020-11-09 20:43 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 25/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-09 20:46 ` Mathieu Poirier
2020-11-09 20:46 ` Mathieu Poirier
2020-11-10 10:50 ` Suzuki K Poulose
2020-11-10 10:50 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 26/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-11-02 15:31 ` Rob Herring
2020-11-02 15:31 ` Rob Herring
2020-11-09 20:50 ` Mathieu Poirier
2020-11-09 20:50 ` Mathieu Poirier
2020-11-10 10:51 ` Suzuki K Poulose
2020-11-10 10:51 ` Suzuki K Poulose
2020-10-29 7:53 ` [PATCH v3 00/26] coresight: Support for ETM system instructions Mike Leach
2020-10-29 7:53 ` Mike Leach
2020-10-29 15:45 ` Suzuki K Poulose
2020-10-29 15:45 ` Suzuki K Poulose
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