From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: rajanv@xilinx.com, tejasp@xilinx.com, dshah@xilinx.com, rvisaval@xilinx.com, michals@xilinx.com, kernel@pengutronix.de, robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, Michael Tretter <m.tretter@pengutronix.de> Subject: [PATCH 10/12] soc: xilinx: vcu: make the PLL configurable Date: Mon, 16 Nov 2020 08:55:30 +0100 [thread overview] Message-ID: <20201116075532.4019252-11-m.tretter@pengutronix.de> (raw) In-Reply-To: <20201116075532.4019252-1-m.tretter@pengutronix.de> Do not configure the PLL when probing the driver, but register the clock in the clock framework and do the configuration based on the respective callbacks. This is necessary to allow the consumers, i.e., encoder and decoder drivers, of the xlnx_vcu clock provider to set the clock rate and actually enable the clocks without relying on some pre-configuration. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- drivers/soc/xilinx/xlnx_vcu.c | 137 ++++++++++++++++++++++++++-------- 1 file changed, 106 insertions(+), 31 deletions(-) diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index cf8456b4ef78..84d7c46cd42f 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -257,9 +257,18 @@ static void xvcu_write_field_reg(void __iomem *iomem, int offset, xvcu_write(iomem, offset, val); } -static int xvcu_pll_wait_for_lock(struct xvcu_device *xvcu) +#define to_vcu_pll(_hw) container_of(_hw, struct vcu_pll, hw) + +struct vcu_pll { + struct clk_hw hw; + void __iomem *reg_base; + unsigned long fvco_min; + unsigned long fvco_max; +}; + +static int xvcu_pll_wait_for_lock(struct vcu_pll *pll) { - void __iomem *base = xvcu->vcu_slcr_ba; + void __iomem *base = pll->reg_base; unsigned long timeout; u32 lock_status; @@ -307,9 +316,9 @@ static const struct xvcu_pll_cfg *xvcu_find_cfg(int div) return cfg; } -static int xvcu_pll_set_div(struct xvcu_device *xvcu, int div) +static int xvcu_pll_set_div(struct vcu_pll *pll, int div) { - void __iomem *base = xvcu->vcu_slcr_ba; + void __iomem *base = pll->reg_base; const struct xvcu_pll_cfg *cfg = NULL; u32 vcu_pll_ctrl; u32 cfg_val; @@ -334,24 +343,49 @@ static int xvcu_pll_set_div(struct xvcu_device *xvcu, int div) return 0; } -static int xvcu_pll_set_rate(struct xvcu_device *xvcu, +static long xvcu_pll_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct vcu_pll *pll = to_vcu_pll(hw); + unsigned int feedback_div; + + rate = clamp_t(unsigned long, rate, pll->fvco_min, pll->fvco_max); + + feedback_div = DIV_ROUND_CLOSEST_ULL(rate, *parent_rate); + feedback_div = clamp_t(unsigned int, feedback_div, 25, 125); + + return *parent_rate * feedback_div; +} + +static unsigned long xvcu_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; + unsigned int div; + u32 vcu_pll_ctrl; + + vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); + div = (vcu_pll_ctrl >> VCU_PLL_CTRL_FBDIV_SHIFT) & VCU_PLL_CTRL_FBDIV_MASK; + + return div * parent_rate; +} + +static int xvcu_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - return xvcu_pll_set_div(xvcu, rate / parent_rate); + struct vcu_pll *pll = to_vcu_pll(hw); + + return xvcu_pll_set_div(pll, rate / parent_rate); } -static int xvcu_pll_enable(struct xvcu_device *xvcu) +static int xvcu_pll_enable(struct clk_hw *hw) { - void __iomem *base = xvcu->vcu_slcr_ba; + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; u32 vcu_pll_ctrl; int ret; - ret = clk_prepare_enable(xvcu->pll_ref); - if (ret) { - dev_err(xvcu->dev, "failed to enable pll_ref clock source\n"); - return ret; - } - xvcu_write_field_reg(base, VCU_PLL_CTRL, 1, VCU_PLL_CTRL_BYPASS_MASK, VCU_PLL_CTRL_BYPASS_SHIFT); @@ -371,9 +405,9 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu) vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT; xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); - ret = xvcu_pll_wait_for_lock(xvcu); + ret = xvcu_pll_wait_for_lock(pll); if (ret) { - dev_err(xvcu->dev, "PLL is not locked\n"); + pr_err("VCU PLL is not locked\n"); goto err; } @@ -381,15 +415,14 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu) 0, VCU_PLL_CTRL_BYPASS_MASK, VCU_PLL_CTRL_BYPASS_SHIFT); - return ret; err: - clk_disable_unprepare(xvcu->pll_ref); return ret; } -static void xvcu_pll_disable(struct xvcu_device *xvcu) +static void xvcu_pll_disable(struct clk_hw *hw) { - void __iomem *base = xvcu->vcu_slcr_ba; + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; u32 vcu_pll_ctrl; vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); @@ -400,8 +433,49 @@ static void xvcu_pll_disable(struct xvcu_device *xvcu) vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT); vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT; xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); +} + +static const struct clk_ops vcu_pll_ops = { + .enable = xvcu_pll_enable, + .disable = xvcu_pll_disable, + .round_rate = xvcu_pll_round_rate, + .recalc_rate = xvcu_pll_recalc_rate, + .set_rate = xvcu_pll_set_rate, +}; + +static struct clk_hw *xvcu_register_pll(struct device *dev, + void __iomem *reg_base, + const char *name, const char *parent, + unsigned long flags) +{ + struct vcu_pll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + init.name = name; + init.parent_names = &parent; + init.ops = &vcu_pll_ops; + init.num_parents = 1; + init.flags = flags; + + pll = devm_kmalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->hw.init = &init; + pll->reg_base = reg_base; + pll->fvco_min = FVCO_MIN; + pll->fvco_max = FVCO_MAX; + + hw = &pll->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + clk_hw_set_rate_range(hw, pll->fvco_min, pll->fvco_max); - clk_disable_unprepare(xvcu->pll_ref); + return hw; } /** @@ -426,7 +500,6 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) u32 pll_clk; u32 mod; int i; - int ret; const struct xvcu_pll_cfg *found = NULL; struct clk_hw *hw; @@ -486,13 +559,9 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", coreclk); dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk); - ret = xvcu_pll_set_rate(xvcu, fvco, refclk); - if (ret) - return ret; - - hw = clk_hw_register_fixed_rate(xvcu->dev, "vcu_pll", - __clk_get_name(xvcu->pll_ref), - 0, fvco); + hw = xvcu_register_pll(xvcu->dev, xvcu, + "vcu_pll", __clk_get_name(xvcu->pll_ref), + CLK_SET_RATE_NO_REPARENT); if (IS_ERR(hw)) return PTR_ERR(hw); xvcu->pll = hw; @@ -519,7 +588,7 @@ static int xvcu_set_pll(struct xvcu_device *xvcu) return ret; } - return xvcu_pll_enable(xvcu); + return 0; } static struct clk_hw *xvcu_clk_hw_register_leaf(struct device *dev, @@ -630,6 +699,13 @@ static int xvcu_register_clock_provider(struct xvcu_device *xvcu) xvcu->clk_data = data; + hw = xvcu_register_pll(dev, reg_base, + "vcu_pll", __clk_get_name(xvcu->pll_ref), + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE); + if (IS_ERR(hw)) + return PTR_ERR(hw); + xvcu->pll = hw; + hw = xvcu_register_pll_post(dev, "vcu_pll_post", clk_hw_get_name(xvcu->pll), reg_base); if (IS_ERR(hw)) @@ -803,7 +879,6 @@ static int xvcu_remove(struct platform_device *pdev) /* Add the the Gasket isolation and put the VCU in reset. */ regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); - xvcu_pll_disable(xvcu); clk_disable_unprepare(xvcu->aclk); return 0; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de> To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: dshah@xilinx.com, tejasp@xilinx.com, sboyd@kernel.org, mturquette@baylibre.com, Michael Tretter <m.tretter@pengutronix.de>, rajanv@xilinx.com, robh+dt@kernel.org, michals@xilinx.com, kernel@pengutronix.de, rvisaval@xilinx.com Subject: [PATCH 10/12] soc: xilinx: vcu: make the PLL configurable Date: Mon, 16 Nov 2020 08:55:30 +0100 [thread overview] Message-ID: <20201116075532.4019252-11-m.tretter@pengutronix.de> (raw) In-Reply-To: <20201116075532.4019252-1-m.tretter@pengutronix.de> Do not configure the PLL when probing the driver, but register the clock in the clock framework and do the configuration based on the respective callbacks. This is necessary to allow the consumers, i.e., encoder and decoder drivers, of the xlnx_vcu clock provider to set the clock rate and actually enable the clocks without relying on some pre-configuration. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- drivers/soc/xilinx/xlnx_vcu.c | 137 ++++++++++++++++++++++++++-------- 1 file changed, 106 insertions(+), 31 deletions(-) diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index cf8456b4ef78..84d7c46cd42f 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -257,9 +257,18 @@ static void xvcu_write_field_reg(void __iomem *iomem, int offset, xvcu_write(iomem, offset, val); } -static int xvcu_pll_wait_for_lock(struct xvcu_device *xvcu) +#define to_vcu_pll(_hw) container_of(_hw, struct vcu_pll, hw) + +struct vcu_pll { + struct clk_hw hw; + void __iomem *reg_base; + unsigned long fvco_min; + unsigned long fvco_max; +}; + +static int xvcu_pll_wait_for_lock(struct vcu_pll *pll) { - void __iomem *base = xvcu->vcu_slcr_ba; + void __iomem *base = pll->reg_base; unsigned long timeout; u32 lock_status; @@ -307,9 +316,9 @@ static const struct xvcu_pll_cfg *xvcu_find_cfg(int div) return cfg; } -static int xvcu_pll_set_div(struct xvcu_device *xvcu, int div) +static int xvcu_pll_set_div(struct vcu_pll *pll, int div) { - void __iomem *base = xvcu->vcu_slcr_ba; + void __iomem *base = pll->reg_base; const struct xvcu_pll_cfg *cfg = NULL; u32 vcu_pll_ctrl; u32 cfg_val; @@ -334,24 +343,49 @@ static int xvcu_pll_set_div(struct xvcu_device *xvcu, int div) return 0; } -static int xvcu_pll_set_rate(struct xvcu_device *xvcu, +static long xvcu_pll_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct vcu_pll *pll = to_vcu_pll(hw); + unsigned int feedback_div; + + rate = clamp_t(unsigned long, rate, pll->fvco_min, pll->fvco_max); + + feedback_div = DIV_ROUND_CLOSEST_ULL(rate, *parent_rate); + feedback_div = clamp_t(unsigned int, feedback_div, 25, 125); + + return *parent_rate * feedback_div; +} + +static unsigned long xvcu_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; + unsigned int div; + u32 vcu_pll_ctrl; + + vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); + div = (vcu_pll_ctrl >> VCU_PLL_CTRL_FBDIV_SHIFT) & VCU_PLL_CTRL_FBDIV_MASK; + + return div * parent_rate; +} + +static int xvcu_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - return xvcu_pll_set_div(xvcu, rate / parent_rate); + struct vcu_pll *pll = to_vcu_pll(hw); + + return xvcu_pll_set_div(pll, rate / parent_rate); } -static int xvcu_pll_enable(struct xvcu_device *xvcu) +static int xvcu_pll_enable(struct clk_hw *hw) { - void __iomem *base = xvcu->vcu_slcr_ba; + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; u32 vcu_pll_ctrl; int ret; - ret = clk_prepare_enable(xvcu->pll_ref); - if (ret) { - dev_err(xvcu->dev, "failed to enable pll_ref clock source\n"); - return ret; - } - xvcu_write_field_reg(base, VCU_PLL_CTRL, 1, VCU_PLL_CTRL_BYPASS_MASK, VCU_PLL_CTRL_BYPASS_SHIFT); @@ -371,9 +405,9 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu) vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT; xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); - ret = xvcu_pll_wait_for_lock(xvcu); + ret = xvcu_pll_wait_for_lock(pll); if (ret) { - dev_err(xvcu->dev, "PLL is not locked\n"); + pr_err("VCU PLL is not locked\n"); goto err; } @@ -381,15 +415,14 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu) 0, VCU_PLL_CTRL_BYPASS_MASK, VCU_PLL_CTRL_BYPASS_SHIFT); - return ret; err: - clk_disable_unprepare(xvcu->pll_ref); return ret; } -static void xvcu_pll_disable(struct xvcu_device *xvcu) +static void xvcu_pll_disable(struct clk_hw *hw) { - void __iomem *base = xvcu->vcu_slcr_ba; + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; u32 vcu_pll_ctrl; vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); @@ -400,8 +433,49 @@ static void xvcu_pll_disable(struct xvcu_device *xvcu) vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT); vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT; xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); +} + +static const struct clk_ops vcu_pll_ops = { + .enable = xvcu_pll_enable, + .disable = xvcu_pll_disable, + .round_rate = xvcu_pll_round_rate, + .recalc_rate = xvcu_pll_recalc_rate, + .set_rate = xvcu_pll_set_rate, +}; + +static struct clk_hw *xvcu_register_pll(struct device *dev, + void __iomem *reg_base, + const char *name, const char *parent, + unsigned long flags) +{ + struct vcu_pll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + init.name = name; + init.parent_names = &parent; + init.ops = &vcu_pll_ops; + init.num_parents = 1; + init.flags = flags; + + pll = devm_kmalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->hw.init = &init; + pll->reg_base = reg_base; + pll->fvco_min = FVCO_MIN; + pll->fvco_max = FVCO_MAX; + + hw = &pll->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + clk_hw_set_rate_range(hw, pll->fvco_min, pll->fvco_max); - clk_disable_unprepare(xvcu->pll_ref); + return hw; } /** @@ -426,7 +500,6 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) u32 pll_clk; u32 mod; int i; - int ret; const struct xvcu_pll_cfg *found = NULL; struct clk_hw *hw; @@ -486,13 +559,9 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", coreclk); dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk); - ret = xvcu_pll_set_rate(xvcu, fvco, refclk); - if (ret) - return ret; - - hw = clk_hw_register_fixed_rate(xvcu->dev, "vcu_pll", - __clk_get_name(xvcu->pll_ref), - 0, fvco); + hw = xvcu_register_pll(xvcu->dev, xvcu, + "vcu_pll", __clk_get_name(xvcu->pll_ref), + CLK_SET_RATE_NO_REPARENT); if (IS_ERR(hw)) return PTR_ERR(hw); xvcu->pll = hw; @@ -519,7 +588,7 @@ static int xvcu_set_pll(struct xvcu_device *xvcu) return ret; } - return xvcu_pll_enable(xvcu); + return 0; } static struct clk_hw *xvcu_clk_hw_register_leaf(struct device *dev, @@ -630,6 +699,13 @@ static int xvcu_register_clock_provider(struct xvcu_device *xvcu) xvcu->clk_data = data; + hw = xvcu_register_pll(dev, reg_base, + "vcu_pll", __clk_get_name(xvcu->pll_ref), + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE); + if (IS_ERR(hw)) + return PTR_ERR(hw); + xvcu->pll = hw; + hw = xvcu_register_pll_post(dev, "vcu_pll_post", clk_hw_get_name(xvcu->pll), reg_base); if (IS_ERR(hw)) @@ -803,7 +879,6 @@ static int xvcu_remove(struct platform_device *pdev) /* Add the the Gasket isolation and put the VCU in reset. */ regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); - xvcu_pll_disable(xvcu); clk_disable_unprepare(xvcu->aclk); return 0; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-16 8:11 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-16 7:55 [PATCH 00/12] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 01/12] ARM: dts: define indexes for output clocks Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-12-02 14:33 ` Michal Simek 2020-12-02 14:33 ` Michal Simek 2020-12-07 19:21 ` Rob Herring 2020-12-07 19:21 ` Rob Herring 2020-12-13 5:44 ` Stephen Boyd 2020-12-13 5:44 ` Stephen Boyd 2020-11-16 7:55 ` [PATCH 02/12] clk: divider: fix initialization with parent_hw Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-12-02 14:28 ` Michal Simek 2020-12-02 14:28 ` Michal Simek 2020-12-13 5:42 ` Stephen Boyd 2020-12-13 5:42 ` Stephen Boyd 2020-11-16 7:55 ` [PATCH 03/12] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 04/12] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 05/12] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 06/12] soc: xilinx: vcu: implement PLL disable Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 07/12] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-12-02 14:41 ` Michal Simek 2020-12-02 14:41 ` Michal Simek 2020-11-16 7:55 ` [PATCH 08/12] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-12-02 14:49 ` Michal Simek 2020-12-02 14:49 ` Michal Simek 2020-12-13 5:55 ` Stephen Boyd 2020-12-13 5:55 ` Stephen Boyd 2020-12-15 11:38 ` Michael Tretter 2020-12-15 11:38 ` Michael Tretter 2020-12-16 1:09 ` Stephen Boyd 2020-12-16 1:09 ` Stephen Boyd 2020-12-21 9:18 ` Michael Tretter 2020-12-21 9:18 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 09/12] soc: xilinx: vcu: make pll post divider explicit Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-12-02 14:51 ` Michal Simek 2020-12-02 14:51 ` Michal Simek 2020-11-16 7:55 ` Michael Tretter [this message] 2020-11-16 7:55 ` [PATCH 10/12] soc: xilinx: vcu: make the PLL configurable Michael Tretter 2020-12-02 14:54 ` Michal Simek 2020-12-02 14:54 ` Michal Simek 2020-11-16 7:55 ` [PATCH 11/12] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-11-16 7:55 ` [PATCH 12/12] soc: xilinx: vcu: use bitfields for register definition Michael Tretter 2020-11-16 7:55 ` Michael Tretter 2020-12-13 5:47 ` Stephen Boyd 2020-12-13 5:47 ` Stephen Boyd 2020-12-03 7:46 ` [PATCH 00/12] soc: xilinx: vcu: Convert driver to clock provider Michal Simek 2020-12-03 7:46 ` Michal Simek 2020-12-03 9:00 ` Michael Tretter 2020-12-03 9:00 ` Michael Tretter 2020-12-03 9:14 ` Michal Simek 2020-12-03 9:14 ` Michal Simek 2020-12-13 5:50 ` Stephen Boyd 2020-12-13 5:50 ` Stephen Boyd 2020-12-15 11:56 ` Michael Tretter 2020-12-15 11:56 ` Michael Tretter 2020-12-16 2:37 ` Stephen Boyd 2020-12-16 2:37 ` Stephen Boyd 2020-12-21 9:19 ` Michael Tretter 2020-12-21 9:19 ` Michael Tretter
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