[PATCH 00/26] TI J7 SoC HSM Rearch support series

[PATCH 00/26] TI J7 SoC HSM Rearch support series

[Tero Kristo]

Hello,

On TI J7 SoCs the device manager firmware is now split into two
portions instead of the existing one which supported all services via a
single firmware image running on DMSC core. Now, the existing DMSC core
is dedicated for secure services only, and the PM and RM functionality
is moved under a separate firmware image running on MCU R5 core. This
is completely transparent for the firmware users, as the existing
messaging mechanism (TI-SCI) routes everything to proper destination,
except for anything that runs on MCU R5, and in our case it happens
to be R5 SPL bootloader.

To support the firmware split, R5 SPL implementation must be changed in
a way that it implements its own PM features, as these are needed during
boot time. This series thus implements a couple of new drivers, PLL
clock driver for the SoCs, and also a generic clock provider driver which
is used to attach device drivers to proper clock entries. Also
implemented is a power domain driver to power up/down IP blocks. R5
SPL bootloader also now needs to load and start the new DM firmware image
and this is handled in the series.

There are also a number of fixes attached to the series for fixing
issues noticed while implementing the new drivers, mostly on the generic
clock drivers side. I decided to keep the series as a single chunk for
now, as it probably makes it easier to see why certain things are done.
Let me know if you want me to split this series somehow.

-Tero


--
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[PATCH 01/26] lib: rational: copy the rational fraction lib routines from Linux

[Tero Kristo]

Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 include/linux/rational.h | 20 ++++++++
 lib/Kconfig              |  7 +++
 lib/Makefile             |  2 +
 lib/rational.c           | 99 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 128 insertions(+)
 create mode 100644 include/linux/rational.h
 create mode 100644 lib/rational.c

diff --git a/include/linux/rational.h b/include/linux/rational.h
new file mode 100644
index 0000000000..33f5f5fc3e
--- /dev/null
+++ b/include/linux/rational.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com>
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+	unsigned long given_numerator, unsigned long given_denominator,
+	unsigned long max_numerator, unsigned long max_denominator,
+	unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 37aae73a26..2c6021c486 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -660,6 +660,13 @@ config SMBIOS_PRODUCT_NAME
 	  The product name to store in SMBIOS structures.
 	  Change this to override the default one (CONFIG_SYS_BOARD).
 
+config LIB_RATIONAL
+	bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+	bool "enable continued fraction calculation routines for SPL"
+	depends on SPL
+
 endmenu
 
 config ASN1_COMPILER
diff --git a/lib/Makefile b/lib/Makefile
index 0cd7bea282..b921691169 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -70,6 +70,8 @@ obj-$(CONFIG_$(SPL_)LZO) += lzo/
 obj-$(CONFIG_$(SPL_)LZMA) += lzma/
 obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 
+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
 obj-$(CONFIG_LIBAVB) += libavb/
 
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
diff --git a/lib/rational.c b/lib/rational.c
new file mode 100644
index 0000000000..316db3b590
--- /dev/null
+++ b/lib/rational.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com>
+ * Copyright (C) 2019 Trent Piepho <tpiepho@gmail.com>
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include <linux/rational.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 10000,
+ *		(1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look@given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+	unsigned long given_numerator, unsigned long given_denominator,
+	unsigned long max_numerator, unsigned long max_denominator,
+	unsigned long *best_numerator, unsigned long *best_denominator)
+{
+	/* n/d is the starting rational, which is continually
+	 * decreased each iteration using the Euclidean algorithm.
+	 *
+	 * dp is the value of d from the prior iteration.
+	 *
+	 * n2/d2, n1/d1, and n0/d0 are our successively more accurate
+	 * approximations of the rational.  They are, respectively,
+	 * the current, previous, and two prior iterations of it.
+	 *
+	 * a is current term of the continued fraction.
+	 */
+	unsigned long n, d, n0, d0, n1, d1, n2, d2;
+	n = given_numerator;
+	d = given_denominator;
+	n0 = d1 = 0;
+	n1 = d0 = 1;
+
+	for (;;) {
+		unsigned long dp, a;
+
+		if (d == 0)
+			break;
+		/* Find next term in continued fraction, 'a', via
+		 * Euclidean algorithm.
+		 */
+		dp = d;
+		a = n / d;
+		d = n % d;
+		n = dp;
+
+		/* Calculate the current rational approximation (aka
+		 * convergent), n2/d2, using the term just found and
+		 * the two prior approximations.
+		 */
+		n2 = n0 + a * n1;
+		d2 = d0 + a * d1;
+
+		/* If the current convergent exceeds the maxes, then
+		 * return either the previous convergent or the
+		 * largest semi-convergent, the final term of which is
+		 * found below as 't'.
+		 */
+		if ((n2 > max_numerator) || (d2 > max_denominator)) {
+			unsigned long t = min((max_numerator - n0) / n1,
+					      (max_denominator - d0) / d1);
+
+			/* This tests if the semi-convergent is closer
+			 * than the previous convergent.
+			 */
+			if (2u * t > a || (2u * t == a && d0 * dp > d1 * d)) {
+				n1 = n0 + t * n1;
+				d1 = d0 + t * d1;
+			}
+			break;
+		}
+		n0 = n1;
+		n1 = n2;
+		d0 = d1;
+		d1 = d2;
+	}
+	*best_numerator = n1;
+	*best_denominator = d1;
+}
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 02/26] ram: k3-j721e: fix clk_set_rate API usage

[Tero Kristo]

clk_set_rate returns the new clock rate for the clock, not 0 in success.
Fix the error checks to reflect proper API usage.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/ram/k3-j721e/k3-j721e-ddrss.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
index d647a8a209..247b9d5f16 100644
--- a/drivers/ram/k3-j721e/k3-j721e-ddrss.c
+++ b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
@@ -195,8 +195,10 @@ static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
 
 	/* Put DDR pll in bypass mode */
 	ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
-	if (ret)
-		dev_err(dev, "ddr clk bypass failed\n");
+	if (ret < 0)
+		dev_err(dev, "ddr clk bypass failed: %d\n", ret);
+	else
+		ret = 0;
 
 	return ret;
 }
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported

[Tero Kristo]

With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/remoteproc/ti_k3_r5f_rproc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 9332a63d21..b2902e7fd3 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev)
 {
 	struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
 	struct k3_r5f_core *core = dev_get_priv(dev);
+#ifdef CONFIG_CLK_TI_SCI
 	bool r_state;
+#endif
 	int ret;
 
 	dev_dbg(dev, "%s\n", __func__);
@@ -804,6 +806,7 @@ static int k3_r5f_probe(struct udevice *dev)
 		return ret;
 	}
 
+#ifdef CONFIG_CLK_TI_SCI
 	ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
 					       &r_state, &core->in_use);
 	if (ret)
@@ -817,6 +820,7 @@ static int k3_r5f_probe(struct udevice *dev)
 
 	/* Make sure Local reset is asserted. Redundant? */
 	reset_assert(&core->reset);
+#endif
 
 	ret = k3_r5f_rproc_configure(core);
 	if (ret) {
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 04/26] common: fit: Update board_fit_image_post_process() to pass fit and node_offset

[Tero Kristo]

From: Lokesh Vutla <lokeshvutla@ti.com>

board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-k3/security.c  | 3 ++-
 arch/arm/mach-keystone/mon.c | 3 ++-
 board/ti/am335x/board.c      | 3 ++-
 board/ti/am43xx/board.c      | 3 ++-
 board/ti/am57xx/board.c      | 3 ++-
 board/ti/dra7xx/evm.c        | 3 ++-
 common/image-fit.c           | 2 +-
 common/spl/spl_fit.c         | 2 +-
 include/image.h              | 7 +++++--
 9 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5a34..5b5ff9ba7b 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,8 @@
 #include <spl.h>
 #include <asm/arch/sys_proto.h>
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d73ac..b863bab196 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
 	return  result;
 }
 
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	int result = 0;
 	void *image = *p_image;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 984cc5e3ba..9a8cc6649c 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -956,7 +956,8 @@ int board_fit_config_name_match(const char *name)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index de49590031..d14355aacd 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -895,7 +895,8 @@ int embedded_dtb_select(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 7809875510..4fd452b050 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1197,7 +1197,8 @@ static int board_bootmode_has_emmc(void)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index ca1976e16a..6364d06ea5 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1064,7 +1064,8 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
 #endif
 
 #ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
diff --git a/common/image-fit.c b/common/image-fit.c
index d54eff9033..093fe8164a 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2042,7 +2042,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 
 #if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
 	/* perform any post-processing on the image data */
-	board_fit_image_post_process(&buf, &size);
+	board_fit_image_post_process(fit, noffset, &buf, &size);
 #endif
 
 	len = (ulong)size;
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index a90d821c82..90a0863057 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -316,7 +316,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 #endif
 
 #ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
-	board_fit_image_post_process(&src, &length);
+	board_fit_image_post_process(fit, node, &src, &length);
 #endif
 
 	if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
diff --git a/include/image.h b/include/image.h
index 10995b8e24..5d03511f38 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1537,12 +1537,15 @@ int board_fit_config_name_match(const char *name);
  * into the FIT creation (i.e. the binary blobs would have been pre-processed
  * before being added to the FIT image).
  *
+ * @fit: pointer to fit image
+ * @node: offset of image node
  * @image: pointer to the image start pointer
  * @size: pointer to the image size
  * @return no return value (failure should be handled internally)
  */
-void board_fit_image_post_process(void **p_image, size_t *p_size);
-#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size);
+#endif
 
 #define FDT_ERROR	((ulong)(-1))
 
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks

[Tero Kristo]

Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk_fixed_rate.c | 45 +++++++++++++++++++++++++++++++++++-
 include/linux/clk-provider.h |  3 +++
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 55e1f8caa5..5556acaf86 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -8,6 +8,9 @@
 #include <dm.h>
 #include <linux/clk-provider.h>
 
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
 	return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -24,6 +27,15 @@ const struct clk_ops clk_fixed_rate_ops = {
 	.enable = dummy_enable,
 };
 
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+	return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+	.get_rate = clk_fixed_rate_raw_get_rate,
+};
+
 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
 {
 	struct clk *clk = &to_clk_fixed_rate(dev)->clk;
@@ -39,6 +51,30 @@ static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+				    ulong rate)
+{
+	struct clk *clk;
+	struct clk_fixed_rate *fixed;
+	int ret;
+
+	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+	if (!fixed)
+		return ERR_PTR(-ENOMEM);
+
+	fixed->fixed_rate = rate;
+
+	clk = &fixed->clk;
+
+	ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+	if (ret) {
+		kfree(fixed);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+
 static const struct udevice_id clk_fixed_rate_match[] = {
 	{
 		.compatible = "fixed-clock",
@@ -47,7 +83,7 @@ static const struct udevice_id clk_fixed_rate_match[] = {
 };
 
 U_BOOT_DRIVER(clk_fixed_rate) = {
-	.name = "fixed_rate_clock",
+	.name = UBOOT_DM_CLK_FIXED_RATE,
 	.id = UCLASS_CLK,
 	.of_match = clk_fixed_rate_match,
 	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
@@ -55,3 +91,10 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
 	.ops = &clk_fixed_rate_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+	.name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+	.id = UCLASS_CLK,
+	.ops = &clk_fixed_rate_raw_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 79dce8f0ad..6b50c42214 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -186,6 +186,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags);
 
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+				    ulong rate);
+
 const char *clk_hw_get_name(const struct clk *hw);
 ulong clk_generic_get_rate(struct clk *clk);
 
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 06/26] clk: fix clock tree dump to properly dump out every registered clock

[Tero Kristo]

Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 cmd/clk.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index e3c3d2f9bb..0245b97136 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
 {
 	int i, is_last;
 	struct udevice *child;
-	struct clk *clkp;
+	struct clk *clkp, *parent;
 	u32 rate;
 
 	clkp = dev_get_clk_ptr(dev);
 	if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+		parent = clk_get_parent(clkp);
+		if (!IS_ERR(parent) && depth == -1)
+			return;
 		depth++;
 		rate = clk_get_rate(clkp);
 
@@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
 	}
 
 	list_for_each_entry(child, &dev->child_head, sibling_node) {
+		if (child == dev)
+			continue;
+
 		is_last = list_is_last(&child->sibling_node, &dev->child_head);
 		show_clks(child, depth, (last_flag << 1) | is_last);
 	}
@@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
 
 int __weak soc_clk_dump(void)
 {
-	struct udevice *root;
+	struct udevice *dev;
+	struct uclass *uc;
+	int ret;
 
-	root = dm_root();
-	if (root) {
-		printf(" Rate               Usecnt      Name\n");
-		printf("------------------------------------------\n");
-		show_clks(root, -1, 0);
-	}
+	ret = uclass_get(UCLASS_CLK, &uc);
+	if (ret)
+		return ret;
+
+	printf(" Rate               Usecnt      Name\n");
+	printf("------------------------------------------\n");
+
+	uclass_foreach_dev(dev, uc)
+		show_clks(dev, -1, 0);
 
 	return 0;
 }
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 07/26] clk: do not attempt to fetch clock pointer with null device

[Tero Kristo]

Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:

  dev_get_uclass_priv: null device

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 31c5997aea..a4b24b98e6 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -493,6 +493,8 @@ struct clk *clk_get_parent(struct clk *clk)
 		return NULL;
 
 	pdev = dev_get_parent(clk->dev);
+	if (!pdev)
+		return ERR_PTR(-ENODEV);
 	pclk = dev_get_clk_ptr(pdev);
 	if (!pclk)
 		return ERR_PTR(-ENODEV);
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 08/26] clk: add support for setting clk rate from cmdline

[Tero Kristo]

Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 cmd/clk.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/cmd/clk.c b/cmd/clk.c
index 0245b97136..fd7944c02e 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 	return ret;
 }
 
+struct udevice *clk_lookup(const char *name)
+{
+	int i = 0;
+	struct udevice *dev;
+
+	do {
+		uclass_get_device(UCLASS_CLK, i++, &dev);
+		if (!strcmp(name, dev->name))
+			return dev;
+	} while (dev);
+
+	return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	struct clk *clk = NULL;
+	s32 freq;
+	struct udevice *dev;
+
+	freq = simple_strtoul(argv[2], NULL, 10);
+
+	dev = clk_lookup(argv[1]);
+
+	if (dev)
+		clk = dev_get_clk_ptr(dev);
+
+	if (!clk) {
+		printf("clock '%s' not found.\n", argv[1]);
+		return -EINVAL;
+	}
+
+	freq = clk_set_rate(clk, freq);
+	if (freq < 0) {
+		printf("set_rate failed: %d\n", freq);
+		return CMD_RET_FAILURE;
+	}
+
+	printf("set_rate returns %u\n", freq);
+	return 0;
+}
+
 static struct cmd_tbl cmd_clk_sub[] = {
 	U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+	U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
 };
 
 static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
 
 #ifdef CONFIG_SYS_LONGHELP
 static char clk_help_text[] =
-	"dump - Print clock frequencies";
+	"dump - Print clock frequencies\n"
+	"setfreq [clk] [freq] - Set clock frequency";
 #endif
 
-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 09/26] clk: sci-clk: fix return value of set_rate

[Tero Kristo]

Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-ti-sci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/clk-ti-sci.c
index 7a9a645137..e2ad18e96b 100644
--- a/drivers/clk/clk-ti-sci.c
+++ b/drivers/clk/clk-ti-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate)
 #endif
 
 	ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
-	if (ret)
+	if (ret) {
 		dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+		return ret;
+	}
 
-	return ret;
+	return rate;
 }
 
 static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 10/26] clk: fix assigned-clocks to pass with deferring provider

[Tero Kristo]

If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-uclass.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index a4b24b98e6..79d5af3d1f 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -239,6 +239,15 @@ static int clk_set_default_parents(struct udevice *dev, int stage)
 
 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
+		/*
+		 * If the clock provider is not ready yet, let it handle
+		 * the re-programming later.
+		 */
+		if (ret == -EPROBE_DEFER) {
+			ret = 0;
+			continue;
+		}
+
 		if (ret) {
 			debug("%s: could not get assigned clock %d for %s\n",
 			      __func__, index, dev_read_name(dev));
@@ -307,6 +316,15 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
 
 		ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
 					      index, &clk);
+		/*
+		 * If the clock provider is not ready yet, let it handle
+		 * the re-programming later.
+		 */
+		if (ret == -EPROBE_DEFER) {
+			ret = 0;
+			continue;
+		}
+
 		if (ret) {
 			debug("%s: could not get assigned clock %d for %s\n",
 			      __func__, index, dev_read_name(dev));
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 11/26] clk: fix set_rate to clean up cached rates for the hierarchy

[Tero Kristo]

Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/clk-uclass.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 79d5af3d1f..9a5c061304 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -544,6 +544,22 @@ long long clk_get_parent_rate(struct clk *clk)
 	return pclk->rate;
 }
 
+static void clk_clean_rate_cache(struct clk *clk)
+{
+	struct udevice *child_dev;
+	struct clk *clkp;
+
+	if (!clk)
+		return;
+
+	clk->rate = 0;
+
+	list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+		clkp = dev_get_clk_ptr(child_dev);
+		clk_clean_rate_cache(clkp);
+	}
+}
+
 ulong clk_set_rate(struct clk *clk, ulong rate)
 {
 	const struct clk_ops *ops;
@@ -556,6 +572,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
 	if (!ops->set_rate)
 		return -ENOSYS;
 
+	/* Clean up cached rates for us and all child clocks */
+	clk_clean_rate_cache(clk);
+
 	return ops->set_rate(clk, rate);
 }
 
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 12/26] clk: add support for TI K3 SoC PLL

[Tero Kristo]

Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/Kconfig      |  12 ++
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-k3-pll.c | 273 +++++++++++++++++++++++++++++++++++++++
 include/k3-clk.h         |  15 +++
 4 files changed, 301 insertions(+)
 create mode 100644 drivers/clk/clk-k3-pll.c
 create mode 100644 include/k3-clk.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..b2e9458f85 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -106,6 +106,18 @@ config CLK_TI_SCI
 	  available on some new TI's SoCs. If you wish to use clock resources
 	  managed by the TI System Controller, say Y here. Otherwise, say N.
 
+config CLK_K3_PLL
+	bool "PLL clock support for K3 SoC family of devices"
+	depends on CLK && LIB_RATIONAL
+	help
+	  Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+	bool "PLL clock support for K3 SoC family of devices"
+	depends on CLK && LIB_RATIONAL && SPL
+	help
+	  Enables PLL clock support for K3 SoC family of devices.
+
 config CLK_HSDK
 	bool "Enable cgu clock driver for HSDK boards"
 	depends on CLK && TARGET_HSDK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..6009eab800 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
 obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
 obj-$(CONFIG_STM32H7) += clk_stm32h7.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
 obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
 obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
diff --git a/drivers/clk/clk-k3-pll.c b/drivers/clk/clk-k3-pll.c
new file mode 100644
index 0000000000..2240f13c7a
--- /dev/null
+++ b/drivers/clk/clk-k3-pll.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+#include <linux/rational.h>
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG			0x08
+#define PLL_KICK0			0x10
+#define PLL_KICK1			0x14
+#define PLL_16FFT_CTRL			0x20
+#define PLL_16FFT_STAT			0x24
+#define PLL_16FFT_FREQ_CTRL0		0x30
+#define PLL_16FFT_FREQ_CTRL1		0x34
+#define PLL_16FFT_DIV_CTRL		0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN	BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN		BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN		BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCK		BIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK	0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK		0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS	24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN          BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE				0x68ef3490
+#define PLL_KICK1_VALUE				0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+	struct clk	clk;
+	void __iomem	*reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 stat;
+	int i;
+
+	for (i = 0; i < 100000; i++) {
+		stat = readl(pll->reg + PLL_16FFT_STAT);
+		if (stat & PLL_16FFT_STAT_LOCK)
+			return 0;
+	}
+
+	printf("%s: pll (%s) failed to lock\n", __func__,
+	       clk->dev->name);
+
+	return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u64 current_freq;
+	u64 parent_freq = clk_get_parent_rate(clk);
+	u32 pllm;
+	u32 plld;
+	u32 pllfm;
+	u32 ctrl;
+
+	/* Check if we are in bypass */
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+		return parent_freq;
+
+	pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+	pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+	plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+		PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+	current_freq = parent_freq * pllm / plld;
+
+	if (pllfm) {
+		u64 tmp;
+
+		tmp = parent_freq * pllfm;
+		do_div(tmp, plld);
+		tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		current_freq += tmp;
+	}
+
+	return current_freq;
+}
+
+static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u64 parent_freq = clk_get_parent_rate(clk);
+	int ret;
+	u32 ctrl;
+	unsigned long pllm;
+	u32 pllfm = 0;
+	unsigned long plld;
+	u32 rem;
+	int shift;
+
+	debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate);
+
+	if (ti_pll_clk_get_rate(clk) == rate)
+		return rate;
+
+	if (rate != parent_freq)
+		/*
+		 * Attempt with higher max multiplier value first to give
+		 * some space for fractional divider to kick in.
+		 */
+		for (shift = 8; shift >= 0; shift -= 8) {
+			rational_best_approximation(rate, parent_freq,
+				((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
+				PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
+			if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
+				break;
+		}
+
+	/* Put PLL to bypass mode */
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	if (rate == parent_freq) {
+		debug("%s: put %s to bypass\n", __func__, clk->dev->name);
+		return rate;
+	}
+
+	debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
+	      __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
+
+	/* Check if we need fractional config */
+	if (plld > 1) {
+		pllfm = pllm % plld;
+		pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+		rem = pllfm % plld;
+		pllfm /= plld;
+		if (rem)
+			pllfm++;
+		pllm /= plld;
+		plld = 1;
+	}
+
+	if (pllfm)
+		ctrl |= PLL_16FFT_CTRL_DSM_EN;
+	else
+		ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+
+	writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
+	writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+	writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
+
+	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+	ctrl |= PLL_16FFT_CTRL_PLL_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	ret = ti_pll_wait_for_lock(clk);
+	if (ret)
+		return ret;
+
+	debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
+	      __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
+
+	return parent_freq * pllm / plld +
+		((parent_freq * pllfm / plld) >>
+		 PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS);
+}
+
+static int ti_pll_clk_enable(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 ctrl;
+
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+	ctrl |= PLL_16FFT_CTRL_PLL_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	return ti_pll_wait_for_lock(clk);
+}
+
+static int ti_pll_clk_disable(struct clk *clk)
+{
+	struct ti_pll_clk *pll = to_clk_pll(clk);
+	u32 ctrl;
+
+	ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+	ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+	writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+	return 0;
+}
+
+static const struct clk_ops ti_pll_clk_ops = {
+	.get_rate = ti_pll_clk_get_rate,
+	.set_rate = ti_pll_clk_set_rate,
+	.enable = ti_pll_clk_enable,
+	.disable = ti_pll_clk_disable,
+};
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+				void __iomem *reg)
+{
+	struct ti_pll_clk *pll;
+	int ret;
+	int i;
+	u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->reg = reg;
+
+	ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
+	if (ret) {
+		printf("%s: failed to register: %d\n", __func__, ret);
+		kfree(pll);
+		return ERR_PTR(ret);
+	}
+
+	/* Unlock the PLL registers */
+	writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
+	writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
+
+	/* Enable all HSDIV outputs */
+	cfg = readl(pll->reg + PLL_16FFT_CFG);
+	for (i = 0; i < 16; i++) {
+		hsdiv_presence_bit = BIT(16 + i);
+		hsdiv_ctrl_offs = 0x80 + (i * 4);
+		/* Enable HSDIV output if present */
+		if ((hsdiv_presence_bit & cfg) != 0UL) {
+			ctrl = readl(pll->reg + hsdiv_ctrl_offs);
+			ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
+			writel(ctrl, pll->reg + hsdiv_ctrl_offs);
+		}
+	}
+
+	return &pll->clk;
+}
+
+U_BOOT_DRIVER(ti_pll_clk) = {
+	.name = "ti-pll-clk",
+	.id = UCLASS_CLK,
+	.ops = &ti_pll_clk_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/k3-clk.h b/include/k3-clk.h
new file mode 100644
index 0000000000..fc84378d03
--- /dev/null
+++ b/include/k3-clk.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com
+ *      Tero Kristo <t-kristo@ti.com>
+ */
+
+#ifndef __K3_CLK_H__
+#define __K3_CLK_H__
+
+#include <linux/clk-provider.h>
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+				void __iomem *reg);
+
+#endif /* __K3_CLK_H__ */
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 13/26] clk: add support for TI K3 SoC clocks

[Tero Kristo]

Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/clk/Kconfig  |  10 ++
 drivers/clk/Makefile |   1 +
 drivers/clk/clk-k3.c | 340 +++++++++++++++++++++++++++++++++++++++++++
 include/k3-clk.h     | 162 +++++++++++++++++++++
 4 files changed, 513 insertions(+)
 create mode 100644 drivers/clk/clk-k3.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index b2e9458f85..003a28f7ac 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -106,6 +106,16 @@ config CLK_TI_SCI
 	  available on some new TI's SoCs. If you wish to use clock resources
 	  managed by the TI System Controller, say Y here. Otherwise, say N.
 
+config CLK_K3
+	bool "Clock support for K3 SoC family of devices"
+	depends on CLK
+	help
+	  Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+	bool "Clock support for K3 SoC family of devices"
+	depends on CLK && SPL
+
 config CLK_K3_PLL
 	bool "PLL clock support for K3 SoC family of devices"
 	depends on CLK && LIB_RATIONAL
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 6009eab800..2f0cb80cb9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -49,5 +49,6 @@ obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
 obj-$(CONFIG_STM32H7) += clk_stm32h7.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
 obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
 obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
diff --git a/drivers/clk/clk-k3.c b/drivers/clk/clk-k3.c
new file mode 100644
index 0000000000..f0392aad5d
--- /dev/null
+++ b/drivers/clk/clk-k3.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <soc.h>
+#include <clk-uclass.h>
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ	800000000
+#define PLL_MAX_FREQ	3200000000UL
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+	u16 dev_id;
+	u32 clk_id;
+	struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+	struct clk_map *map;
+	int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+			u32 dev_id, u32 clk_id)
+{
+	struct clk_map *map;
+
+	debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+	      clk, data, dev_id, clk_id);
+	if (!clk)
+		return;
+
+	map = data->map + data->size++;
+
+	map->dev_id = dev_id;
+	map->clk_id = clk_id;
+	map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+	{
+		.family = "J721E",
+		.data = &j721e_clk_platdata,
+	},
+	{
+		.family = "J7200",
+		.data = &j7200_clk_platdata,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+	struct ti_clk_data *data = dev_get_priv(dev);
+	struct clk *clk;
+	const char *name;
+	const struct clk_data *ti_clk_data;
+	int i, j;
+	const struct soc_attr *soc_match_data;
+	const struct ti_k3_clk_platdata *pdata;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+	if (!soc_match_data)
+		return -ENODEV;
+
+	pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+	data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+			    GFP_KERNEL);
+	data->size = 0;
+
+	for (i = 0; i < pdata->clk_list_cnt; i++) {
+		ti_clk_data = &pdata->clk_list[i];
+
+		switch (ti_clk_data->type) {
+		case CLK_TYPE_FIXED_RATE:
+			name = ti_clk_data->clk.fixed_rate.name;
+			clk = clk_register_fixed_rate(NULL,
+						      name,
+						      ti_clk_data->clk.fixed_rate.rate);
+			break;
+		case CLK_TYPE_DIV:
+			name = ti_clk_data->clk.div.name;
+			clk = clk_register_divider(NULL, name,
+						   ti_clk_data->clk.div.parent,
+						   ti_clk_data->clk.div.flags,
+						   map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE),
+						   ti_clk_data->clk.div.shift,
+						   ti_clk_data->clk.div.width,
+						   0);
+			break;
+		case CLK_TYPE_MUX:
+			name = ti_clk_data->clk.mux.name;
+			clk = clk_register_mux(NULL, name,
+					       ti_clk_data->clk.mux.parents,
+					       ti_clk_data->clk.mux.num_parents,
+					       ti_clk_data->clk.mux.flags,
+					       map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE),
+					       ti_clk_data->clk.mux.shift,
+					       ti_clk_data->clk.mux.width,
+					       0);
+			break;
+		case CLK_TYPE_PLL:
+			name = ti_clk_data->clk.pll.name;
+			clk = clk_register_ti_pll(name,
+						  ti_clk_data->clk.pll.parent,
+						  map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE));
+
+			if (!osc_freq)
+				osc_freq = clk_get_rate(clk_get_parent(clk));
+			break;
+		default:
+			name = NULL;
+			clk = NULL;
+			printf("WARNING: %s has encountered unknown clk type %d\n",
+			       __func__, ti_clk_data->type);
+		}
+
+		if (clk && ti_clk_data->default_freq)
+			clk_set_rate(clk, ti_clk_data->default_freq);
+
+		if (clk && name) {
+			for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) {
+				if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) {
+					clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id,
+						    pdata->soc_dev_clk_data[j].clk_id);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map)
+{
+	if (map->dev_id == dev_id && map->clk_id == clk_id)
+		return 0;
+	if (map->dev_id > dev_id ||
+	    (map->dev_id == dev_id && map->clk_id > clk_id))
+		return -1;
+	return 1;
+}
+
+static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num)
+{
+	int result;
+	int idx;
+
+	for (idx = 0; idx < num; idx++) {
+		result = _clk_cmp(dev_id, clk_id, &map[idx]);
+
+		if (result == 0)
+			return idx;
+	}
+
+	return -ENOENT;
+}
+
+static int ti_clk_of_xlate(struct clk *clk,
+			   struct ofnode_phandle_args *args)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	int idx;
+
+	debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk, args->args_count, args->args[0], args->args[1]);
+
+	if (args->args_count != 2) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (!data->size)
+		return -EPROBE_DEFER;
+
+	idx = bsearch(args->args[0], args->args[1], data->map, data->size);
+	if (idx < 0)
+		return idx;
+
+	clk->id = idx;
+
+	return 0;
+}
+
+static ulong ti_clk_get_rate(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_get_rate(clkp);
+}
+
+static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+	int div = 1;
+	ulong child_rate;
+	const struct clk_ops *ops;
+	ulong new_rate;
+	ulong diff;
+
+	/*
+	 * We must propagate rate change to parent if current clock type
+	 * does not allow setting it.
+	 */
+	while (clkp) {
+		ops = clkp->dev->driver->ops;
+		if (ops->set_rate)
+			break;
+
+		/*
+		 * Store child rate so we can calculate the clock rate
+		 * that must be passed to parent
+		 */
+		child_rate = clk_get_rate(clkp);
+		clkp = clk_get_parent(clkp);
+		if (clkp)
+			div *= clk_get_rate(clkp) / child_rate;
+	}
+
+	if (!clkp)
+		return -ENOSYS;
+
+	child_rate = clk_get_rate(clkp);
+
+	new_rate = clk_set_rate(clkp, rate / div);
+
+	/*
+	 * If the new rate differs by at least 10% of the target,
+	 * modify parent. This handles typical cases where we have a hsdiv
+	 * following directly a PLL
+	 */
+
+	diff = abs(new_rate - rate / div);
+
+	debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__,
+	      clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff);
+
+	if (diff > rate / div / 10) {
+		ulong pll_tgt;
+		int pll_div;
+
+		clk = clkp;
+
+		debug("%s: propagating rate change to parent, rate=%u.\n",
+		      __func__, (u32)rate / div);
+
+		clkp = clk_get_parent(clkp);
+
+		if (rate > osc_freq) {
+			pll_div = PLL_MAX_FREQ / rate / div;
+			pll_tgt = rate / div * pll_div;
+		} else {
+			pll_tgt = osc_freq;
+			pll_div = rate / div / osc_freq;
+		}
+
+		debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__,
+		      (u32)pll_tgt, (u32)rate, pll_div);
+
+		clk_set_rate(clkp, pll_tgt);
+
+		return clk_set_rate(clk, rate / div) * div;
+	}
+
+	return new_rate;
+}
+
+static int ti_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+	struct clk *parentp = data->map[parent->id].clk;
+
+	return clk_set_parent(clkp, parentp);
+}
+
+static int ti_clk_enable(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_enable(clkp);
+}
+
+static int ti_clk_disable(struct clk *clk)
+{
+	struct ti_clk_data *data = dev_get_priv(clk->dev);
+	struct clk *clkp = data->map[clk->id].clk;
+
+	return clk_disable(clkp);
+}
+
+static const struct udevice_id ti_clk_of_match[] = {
+	{ .compatible = "ti,k2g-sci-clk" },
+	{ /* sentinel */ },
+};
+
+static const struct clk_ops ti_clk_ops = {
+	.of_xlate = ti_clk_of_xlate,
+	.set_rate = ti_clk_set_rate,
+	.get_rate = ti_clk_get_rate,
+	.enable = ti_clk_enable,
+	.disable = ti_clk_disable,
+	.set_parent = ti_clk_set_parent,
+};
+
+U_BOOT_DRIVER(ti_clk) = {
+	.name = "ti-clk",
+	.id = UCLASS_CLK,
+	.of_match = ti_clk_of_match,
+	.probe = ti_clk_probe,
+	.priv_auto_alloc_size = sizeof(struct ti_clk_data),
+	.ops = &ti_clk_ops,
+};
diff --git a/include/k3-clk.h b/include/k3-clk.h
index fc84378d03..36f0ddf7cc 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -7,7 +7,169 @@
 #ifndef __K3_CLK_H__
 #define __K3_CLK_H__
 
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
 #include <linux/clk-provider.h>
+#include <linux/types.h>
+#include <stdint.h>
+
+struct dev_clk {
+	int dev_id;
+	int clk_id;
+	const char *clk_name;
+};
+
+#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id,		\
+					.clk_id = _clk_id, .clk_name = _clk_name, }
+
+#define CLK_TYPE_MUX		0x01
+#define CLK_TYPE_DIV		0x02
+#define CLK_TYPE_PLL		0x03
+#define CLK_TYPE_HFOSC		0x04
+#define CLK_TYPE_POSTDIV	0x05
+#define CLK_TYPE_MUX_PLLCTRL	0x06
+#define CLK_TYPE_FIXED_RATE	0x07
+
+struct pll_data {
+	u32 reg;
+	const char *name;
+	const char *parent;
+	u32 flags;
+};
+
+struct mux_data {
+	u32 reg;
+	const char *name;
+	const char * const *parents;
+	int num_parents;
+	u32 flags;
+	int shift;
+	int width;
+};
+
+struct div_data {
+	u32 reg;
+	const char *name;
+	const char *parent;
+	u32 flags;
+	int shift;
+	int width;
+};
+
+struct hfosc_data {
+	const char *name;
+	u32 flags;
+};
+
+struct fixed_rate_data {
+	const char *name;
+	u64 rate;
+	u32 flags;
+};
+
+struct postdiv_data {
+	const char *name;
+	const char *parent;
+	int width;
+	u32 flags;
+};
+
+struct mux_pllctrl_data {
+	u32 reg;
+	const char *name;
+	const char * const *parents;
+	int num_parents;
+	u32 flags;
+};
+
+struct clk_data {
+	int type;
+	u32 default_freq;
+	union {
+		struct pll_data pll;
+		struct mux_data mux;
+		struct div_data div;
+		struct hfosc_data hfosc;
+		struct postdiv_data postdiv;
+		struct mux_pllctrl_data mux_pllctrl;
+		struct fixed_rate_data fixed_rate;
+	} clk;
+};
+
+#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \
+	{								\
+		.type = CLK_TYPE_MUX,					\
+		.clk.mux = { .name = _name, .parents = _parents,	\
+		.reg = _reg,						\
+		.num_parents = _num_parents, .shift = _shift,		\
+		.width = _width, .flags = _flags }			\
+	}
+
+#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags)	\
+	{							\
+		.type = CLK_TYPE_DIV,				\
+		.clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \
+	}
+
+#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \
+	{							\
+		.type = CLK_TYPE_DIV,				\
+		.default_freq = _freq,				\
+		.clk.div = {					\
+			.name = _name, .parent = _parent,	\
+			.reg = _reg, .shift = _shift,		\
+			.width = _width, .flags = _flags }	\
+	}
+
+#define CLK_PLL(_name, _parent, _reg,  _flags)	\
+	{					\
+		.type = CLK_TYPE_PLL,		\
+		.clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
+	}
+
+#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq)	\
+	{							\
+		.type = CLK_TYPE_PLL,				\
+		.default_freq = _freq,				\
+		.clk.pll = { .name = _name, .parent = _parent,	\
+				.reg = _reg, .flags = _flags }	\
+	}
+
+#define CLK_HFOSC(_name, _flags)		\
+	{					\
+		.type = CLK_TYPE_HFOSC,		\
+		.clk.hfosc = { .name = _name, .flags = _flags } \
+	}
+
+#define CLK_FIXED_RATE(_name, _rate, _flags)		\
+	{						\
+		.type = CLK_TYPE_FIXED_RATE,		\
+		.clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \
+	}
+
+#define CLK_POSTDIV(_name, _parent, _width, _flags)	\
+	{						\
+		.type = CLK_TYPE_POSTDIV,		\
+		.clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
+	}
+
+#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags)	\
+	{								\
+		.type = CLK_TYPE_MUX,					\
+		.clk.mux_pllctrl = { .name = _name, .parents = _parents,\
+		.num_parents = _num_parents, .flags = _flags }		\
+	}
+
+struct ti_k3_clk_platdata {
+	const struct clk_data *clk_list;
+	int clk_list_cnt;
+	const struct dev_clk *soc_dev_clk_data;
+	int soc_dev_clk_data_cnt;
+};
+
+extern const struct ti_k3_clk_platdata j721e_clk_platdata;
+extern const struct ti_k3_clk_platdata j7200_clk_platdata;
 
 struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
 				void __iomem *reg);
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 14/26] power: domain: Introduce driver for raw TI K3 PDs

[Tero Kristo]

Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 drivers/power/domain/Kconfig           |   7 +
 drivers/power/domain/Makefile          |   1 +
 drivers/power/domain/ti-power-domain.c | 377 +++++++++++++++++++++++++
 include/k3-dev.h                       |  76 +++++
 4 files changed, 461 insertions(+)
 create mode 100644 drivers/power/domain/ti-power-domain.c
 create mode 100644 include/k3-dev.h

diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980752..b03a82d82c 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@ config TI_SCI_POWER_DOMAIN
 	help
 	  Generic power domain implementation for TI devices implementing the
 	  TI SCI protocol.
+
+config TI_POWER_DOMAIN
+	bool "Enable the TI K3 Power domain driver"
+	depends on POWER_DOMAIN
+	help
+	  Generic power domain implementation for TI K3 devices.
+
 endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6383..3d1e5f073c 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 0000000000..a2d8983540
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <power-domain-uclass.h>
+#include <soc.h>
+#include <k3-dev.h>
+
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_PDSTAT		0x200
+#define PSC_PDCTL		0x300
+#define PSC_MDSTAT		0x800
+#define PSC_MDCTL		0xa00
+
+#define PDCTL_STATE_MASK		0x1
+#define PDCTL_STATE_OFF			0x0
+#define PDCTL_STATE_ON			0x1
+
+#define MDSTAT_STATE_MASK		0x3f
+#define MDSTAT_BUSY_MASK		0x30
+#define MDSTAT_STATE_SWRSTDISABLE	0x0
+#define MDSTAT_STATE_ENABLE		0x3
+
+#define LPSC_TIMEOUT		100000
+#define PD_TIMEOUT		100000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+	u32 val;
+
+	val = readl(psc->base + reg);
+	debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+	return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+	debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+	writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+	return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+	psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+	return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+	psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#ifdef CONFIG_SOC_K3_J721E
+	{
+		.family = "J721E",
+		.data = &j721e_pd_platdata,
+	},
+	{
+		.family = "J7200",
+		.data = &j7200_pd_platdata,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+	struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+	const struct soc_attr *soc_match_data;
+	const struct ti_k3_pd_platdata *pdata;
+
+	printf("%s(dev=%p)\n", __func__, dev);
+
+	if (!data)
+		return -ENOMEM;
+
+	soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+	if (!soc_match_data)
+		return -ENODEV;
+
+	pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+	data->psc = pdata->psc;
+	data->pd = pdata->pd;
+	data->lpsc = pdata->lpsc;
+	data->devs = pdata->devs;
+	data->num_psc = pdata->num_psc;
+	data->num_pd = pdata->num_pd;
+	data->num_lpsc = pdata->num_lpsc;
+	data->num_devs = pdata->num_devs;
+
+	return 0;
+}
+
+static int ti_pd_wait(struct ti_pd *pd)
+{
+	u32 ptstat;
+	int i = PD_TIMEOUT;
+
+	while (i) {
+		ptstat = psc_read(pd->psc, PSC_PTSTAT);
+		if (!(ptstat & BIT(pd->id)))
+			return 0;
+		i--;
+	}
+
+	debug("%s: psc%d, pd%d failed to transition.\n", __func__,
+	      pd->psc->id, pd->id);
+
+	return -ETIMEDOUT;
+}
+
+static void ti_pd_transition(struct ti_pd *pd)
+{
+	psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+}
+
+static u8 ti_pd_state(struct ti_pd *pd)
+{
+	u32 pdctl;
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+	return pdctl & PDCTL_STATE_MASK;
+}
+
+static int ti_pd_get(struct ti_pd *pd)
+{
+	u32 pdctl;
+	int ret;
+
+	pd->usecount++;
+
+	if (pd->usecount > 1)
+		return 0;
+
+	if (pd->depend) {
+		ret = ti_pd_get(pd->depend);
+		if (ret)
+			return ret;
+		ti_pd_transition(pd->depend);
+		ret = ti_pd_wait(pd->depend);
+		if (ret)
+			return ret;
+	}
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+
+	if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON)
+		return 0;
+
+	debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+	pdctl &= ~PDCTL_STATE_MASK;
+	pdctl |= PDCTL_STATE_ON;
+
+	pd_write(pdctl, pd, PSC_PDCTL);
+
+	return 0;
+}
+
+static int ti_pd_put(struct ti_pd *pd)
+{
+	u32 pdctl;
+	int ret;
+
+	pd->usecount--;
+
+	if (pd->usecount > 0)
+		return 0;
+
+	pdctl = pd_read(pd, PSC_PDCTL);
+	if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF)
+		return 0;
+
+	pdctl &= ~PDCTL_STATE_MASK;
+	pdctl |= PDCTL_STATE_OFF;
+
+	debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+	pd_write(pdctl, pd, PSC_PDCTL);
+
+	if (pd->depend) {
+		ti_pd_transition(pd);
+		ret = ti_pd_wait(pd);
+		if (ret)
+			return ret;
+
+		ret = ti_pd_put(pd->depend);
+		if (ret)
+			return ret;
+		ti_pd_transition(pd->depend);
+		ret = ti_pd_wait(pd->depend);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ti_lpsc_wait(struct ti_lpsc *lpsc)
+{
+	u32 mdstat;
+	int i = LPSC_TIMEOUT;
+
+	while (i) {
+		mdstat = lpsc_read(lpsc, PSC_MDSTAT);
+		if (!(mdstat & MDSTAT_BUSY_MASK))
+			return 0;
+		i--;
+	}
+
+	printf("%s: module %d failed to transition.\n", __func__, lpsc->id);
+
+	return -ETIMEDOUT;
+}
+
+static u8 lpsc_get_state(struct ti_lpsc *lpsc)
+{
+	u32 mdctl;
+
+	mdctl = lpsc_read(lpsc, PSC_MDCTL);
+	return mdctl & MDSTAT_STATE_MASK;
+}
+
+static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
+{
+	struct ti_pd *psc_pd;
+	int ret;
+	u32 mdctl;
+
+	psc_pd = lpsc->pd;
+
+	if (state == MDSTAT_STATE_ENABLE) {
+		lpsc->usecount++;
+		if (lpsc->usecount > 1)
+			return 0;
+	} else {
+		lpsc->usecount--;
+		if (lpsc->usecount >= 1)
+			return 0;
+	}
+
+	debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__,
+	      lpsc->psc->id, lpsc->id, state);
+
+	if (lpsc->depend)
+		ti_lpsc_transition(lpsc->depend, state);
+
+	mdctl = lpsc_read(lpsc, PSC_MDCTL);
+	if ((mdctl & MDSTAT_STATE_MASK) == state)
+		return 0;
+
+	if (state == MDSTAT_STATE_ENABLE)
+		ti_pd_get(psc_pd);
+	else
+		ti_pd_put(psc_pd);
+
+	mdctl &= ~MDSTAT_STATE_MASK;
+	mdctl |= state;
+
+	lpsc_write(mdctl, lpsc, PSC_MDCTL);
+
+	ti_pd_transition(psc_pd);
+	ret = ti_pd_wait(psc_pd);
+	if (ret)
+		return ret;
+
+	return ti_lpsc_wait(lpsc);
+}
+
+static int ti_power_domain_transition(struct power_domain *pd, u8 state)
+{
+	struct ti_lpsc *lpsc = pd->priv;
+
+	return ti_lpsc_transition(lpsc, state);
+}
+
+static int ti_power_domain_on(struct power_domain *pd)
+{
+	debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+	return ti_power_domain_transition(pd, MDSTAT_STATE_ENABLE);
+}
+
+static int ti_power_domain_off(struct power_domain *pd)
+{
+	debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+	return ti_power_domain_transition(pd, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct ti_lpsc *lpsc_lookup(struct ti_k3_pd_platdata *data, int id)
+{
+	int idx;
+
+	for (idx = 0; idx < data->num_devs; idx++)
+		if (data->devs[idx].id == id)
+			return data->devs[idx].lpsc;
+
+	return NULL;
+}
+
+static int ti_power_domain_of_xlate(struct power_domain *pd,
+				    struct ofnode_phandle_args *args)
+{
+	struct ti_k3_pd_platdata *data = dev_get_priv(pd->dev);
+	struct ti_lpsc *lpsc;
+
+	debug("%s(power_domain=%p, id=%d)\n", __func__, pd, args->args[0]);
+
+	if (args->args_count < 1) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	lpsc = lpsc_lookup(data, args->args[0]);
+	if (!lpsc) {
+		printf("%s: invalid dev-id: %d\n", __func__, args->args[0]);
+		return -ENOENT;
+	}
+
+	pd->id = lpsc->id;
+	pd->priv = lpsc;
+
+	return 0;
+}
+
+static int ti_power_domain_request(struct power_domain *pd)
+{
+	return 0;
+}
+
+static int ti_power_domain_free(struct power_domain *pd)
+{
+	return 0;
+}
+
+static const struct udevice_id ti_power_domain_of_match[] = {
+	{ .compatible = "ti,sci-pm-domain" },
+	{ /* sentinel */ }
+};
+
+static struct power_domain_ops ti_power_domain_ops = {
+	.on = ti_power_domain_on,
+	.off = ti_power_domain_off,
+	.of_xlate = ti_power_domain_of_xlate,
+	.request = ti_power_domain_request,
+	.rfree = ti_power_domain_free,
+};
+
+U_BOOT_DRIVER(ti_pm_domains) = {
+	.name = "ti-pm-domains",
+	.id = UCLASS_POWER_DOMAIN,
+	.of_match = ti_power_domain_of_match,
+	.probe = ti_power_domain_probe,
+	.priv_auto_alloc_size = sizeof(struct ti_k3_pd_platdata),
+	.ops = &ti_power_domain_ops,
+};
diff --git a/include/k3-dev.h b/include/k3-dev.h
new file mode 100644
index 0000000000..de3a8bdf9e
--- /dev/null
+++ b/include/k3-dev.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments K3 Device Platform Data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __K3_DEV_H__
+#define __K3_DEV_H__
+
+#include <asm/io.h>
+#include <linux/types.h>
+#include <stdint.h>
+
+#define LPSC_MODULE_EXISTS      BIT(0)
+#define LPSC_NO_CLOCK_GATING    BIT(1)
+#define LPSC_DEPENDS            BIT(2)
+#define LPSC_HAS_RESET_ISO      BIT(3)
+#define LPSC_HAS_LOCAL_RESET    BIT(4)
+#define LPSC_NO_MODULE_RESET    BIT(5)
+
+#define PSC_PD_EXISTS           BIT(0)
+#define PSC_PD_ALWAYSON         BIT(1)
+#define PSC_PD_DEPENDS          BIT(2)
+
+struct ti_psc {
+	int id;
+	void __iomem *base;
+};
+
+struct ti_pd;
+
+struct ti_pd {
+	int id;
+	int usecount;
+	struct ti_psc *psc;
+	struct ti_pd *depend;
+};
+
+struct ti_lpsc;
+
+struct ti_lpsc {
+	int id;
+	int usecount;
+	struct ti_psc *psc;
+	struct ti_pd *pd;
+	struct ti_lpsc *depend;
+};
+
+struct ti_dev {
+	struct ti_lpsc *lpsc;
+	int id;
+};
+
+/**
+ * struct ti_k3_pd_platdata - pm domain controller information structure
+ */
+struct ti_k3_pd_platdata {
+	struct ti_psc *psc;
+	struct ti_pd *pd;
+	struct ti_lpsc *lpsc;
+	struct ti_dev *devs;
+	int num_psc;
+	int num_pd;
+	int num_lpsc;
+	int num_devs;
+};
+
+#define PSC(_id, _base) { .id = _id, .base = (void *)_base, }
+#define PSC_PD(_id, _psc, _depend) { .id = _id, .psc = _psc, .depend = _depend }
+#define PSC_LPSC(_id, _psc, _pd, _depend) { .id = _id, .psc = _psc, .pd = _pd, .depend = _depend }
+#define PSC_DEV(_id, _lpsc) { .id = _id, .lpsc = _lpsc }
+
+extern const struct ti_k3_pd_platdata j721e_pd_platdata;
+extern const struct ti_k3_pd_platdata j7200_pd_platdata;
+
+#endif
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 15/26] cmd: ti: pd: Add debug command for K3 power domains

[Tero Kristo]

Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain layer must be enabled on u-boot side for this to work. By
default, u-boot side uses the TI SCI layer, and R5 SPL only uses the
direct access methods.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 cmd/ti/Kconfig                         |   8 ++
 cmd/ti/Makefile                        |   1 +
 cmd/ti/pd.c                            | 185 +++++++++++++++++++++++++
 drivers/power/domain/ti-power-domain.c |   6 +-
 include/k3-dev.h                       |   9 ++
 5 files changed, 206 insertions(+), 3 deletions(-)
 create mode 100644 cmd/ti/pd.c

diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index efeff0d482..db557445a8 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -7,4 +7,12 @@ config CMD_DDR3
 	   supports memory verification, memory comapre and ecc
 	   verification if supported.
 
+config CMD_PD
+	bool "command for verifying power domains"
+	depends on TI_POWER_DOMAIN
+	help
+	   Debug command for K3 power domains. For this to work, the
+	   K3 power domain driver must be enabled for the u-boot; by
+	   default it is only enabled for SPL.
+
 endmenu
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 16fbade9ed..045593396b 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -5,4 +5,5 @@ obj- += dummy.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
 endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
new file mode 100644
index 0000000000..a53ccdcc40
--- /dev/null
+++ b/cmd/ti/pd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <k3-dev.h>
+
+static const struct udevice_id ti_pd_of_match[] = {
+	{ .compatible = "ti,sci-pm-domain" },
+	{ /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+	struct udevice *dev;
+	int i = 0;
+
+	while (1) {
+		uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev);
+		if (!dev)
+			return NULL;
+
+		if (device_is_compatible(dev,
+					 ti_pd_of_match[0].compatible))
+			return  dev_get_priv(dev);
+	}
+
+	return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+	int i;
+	struct ti_lpsc *lpsc;
+	u8 state;
+	static const char * const lpsc_states[] = {
+		"swrstdis", "syncrst", "disable", "enable", "autosleep",
+		"autowake", "unknown",
+	};
+
+	for (i = 0; i < data->num_lpsc; i++) {
+		lpsc = &data->lpsc[i];
+		if (lpsc->pd != pd)
+			continue;
+		state = lpsc_get_state(lpsc);
+		if (state > ARRAY_SIZE(lpsc_states))
+			state = ARRAY_SIZE(lpsc_states) - 1;
+		printf("    LPSC%d: state=%s, usecount=%d\n",
+		       lpsc->id, lpsc_states[state], lpsc->usecount);
+	}
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+	int i;
+	struct ti_pd *pd;
+	u8 state;
+	static const char * const pd_states[] = {
+		"off", "on", "unknown"
+	};
+
+	for (i = 0; i < data->num_pd; i++) {
+		pd = &data->pd[i];
+		if (pd->psc != psc)
+			continue;
+		state = ti_pd_state(pd);
+		if (state > ARRAY_SIZE(pd_states))
+			state = ARRAY_SIZE(pd_states) - 1;
+		printf("  PD%d: state=%s, usecount=%d:\n",
+		       pd->id, pd_states[state], pd->usecount);
+		dump_lpsc(data, pd);
+	}
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+	int i;
+	struct ti_psc *psc;
+
+	for (i = 0; i < data->num_psc; i++) {
+		psc = &data->psc[i];
+		printf("PSC%d [%p]:\n", psc->id, psc->base);
+		dump_pd(data, psc);
+	}
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	struct ti_k3_pd_platdata *data;
+
+	data = ti_pd_find_data();
+	if (!data)
+		return CMD_RET_FAILURE;
+
+	dump_psc(data);
+
+	return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+{
+	u32 psc_id;
+	u32 lpsc_id;
+	int i;
+	struct ti_k3_pd_platdata *data;
+	struct ti_lpsc *lpsc;
+	int ret;
+
+	if (argc < 3)
+		return CMD_RET_FAILURE;
+
+	data = ti_pd_find_data();
+	if (!data)
+		return CMD_RET_FAILURE;
+
+	psc_id = simple_strtoul(argv[1], NULL, 10);
+	lpsc_id = simple_strtoul(argv[2], NULL, 10);
+
+	for (i = 0; i < data->num_lpsc; i++) {
+		lpsc = &data->lpsc[i];
+		if (lpsc->pd->psc->id != psc_id)
+			continue;
+		if (lpsc->id != lpsc_id)
+			continue;
+		printf("%s pd [PSC:%d,LPSC:%d]...\n",
+		       state == MDSTAT_STATE_ENABLE ? "Enabling" : "Disabling",
+		       psc_id, lpsc_id);
+		ret = ti_lpsc_transition(lpsc, state);
+		if (ret)
+			return CMD_RET_FAILURE;
+		else
+			return 0;
+	}
+
+	printf("No matching psc/lpsc found.\n");
+
+	return CMD_RET_FAILURE;
+}
+
+static int do_pd_enable(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	return do_pd_endis(argc, argv, MDSTAT_STATE_ENABLE);
+}
+
+static int do_pd_disable(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	return do_pd_endis(argc, argv, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct cmd_tbl cmd_pd[] = {
+	U_BOOT_CMD_MKENT(dump, 1, 0, do_pd_dump, "", ""),
+	U_BOOT_CMD_MKENT(enable, 3, 0, do_pd_enable, "", ""),
+	U_BOOT_CMD_MKENT(disable, 3, 0, do_pd_disable, "", ""),
+};
+
+static int ti_do_pd(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct cmd_tbl *c;
+
+	argc--;
+	argv++;
+
+	c = find_cmd_tbl(argv[0], cmd_pd, ARRAY_SIZE(cmd_pd));
+	if (c)
+		return c->cmd(cmdtp, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(pd, 4, 1, ti_do_pd,
+	   "TI power domain control",
+#ifdef CONFIG_SYS_LONGHELP
+	   "dump                 - show power domain status\n"
+	   "enable [psc] [lpsc]  - enable power domain\n"
+	   "disable [psc] [lpsc] - disable power domain\n"
+#endif
+);
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index a2d8983540..dfbd75878d 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -134,7 +134,7 @@ static void ti_pd_transition(struct ti_pd *pd)
 	psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
 }
 
-static u8 ti_pd_state(struct ti_pd *pd)
+u8 ti_pd_state(struct ti_pd *pd)
 {
 	u32 pdctl;
 
@@ -233,7 +233,7 @@ static int ti_lpsc_wait(struct ti_lpsc *lpsc)
 	return -ETIMEDOUT;
 }
 
-static u8 lpsc_get_state(struct ti_lpsc *lpsc)
+u8 lpsc_get_state(struct ti_lpsc *lpsc)
 {
 	u32 mdctl;
 
@@ -241,7 +241,7 @@ static u8 lpsc_get_state(struct ti_lpsc *lpsc)
 	return mdctl & MDSTAT_STATE_MASK;
 }
 
-static int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
 {
 	struct ti_pd *psc_pd;
 	int ret;
diff --git a/include/k3-dev.h b/include/k3-dev.h
index de3a8bdf9e..55c5057db3 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -22,6 +22,11 @@
 #define PSC_PD_ALWAYSON         BIT(1)
 #define PSC_PD_DEPENDS          BIT(2)
 
+#define MDSTAT_STATE_MASK		0x3f
+#define MDSTAT_BUSY_MASK		0x30
+#define MDSTAT_STATE_SWRSTDISABLE	0x0
+#define MDSTAT_STATE_ENABLE		0x3
+
 struct ti_psc {
 	int id;
 	void __iomem *base;
@@ -73,4 +78,8 @@ struct ti_k3_pd_platdata {
 extern const struct ti_k3_pd_platdata j721e_pd_platdata;
 extern const struct ti_k3_pd_platdata j7200_pd_platdata;
 
+u8 ti_pd_state(struct ti_pd *pd);
+u8 lpsc_get_state(struct ti_lpsc *lpsc);
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state);
+
 #endif
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 16/26] tools: k3_fit_atf: add DM binary to the FIT image

[Tero Kristo]

Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-k3/config.mk |  4 ++++
 tools/k3_fit_atf.sh        | 19 ++++++++++++++++++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 41fee2b5a1..503ece4520 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -49,6 +49,10 @@ endif
 
 ifdef CONFIG_ARM64
 
+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
 ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
 SPL_ITS := u-boot-spl-k3_HS.its
 $(SPL_ITS): export IS_HS=1
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 4e9f69c087..c0940a2fcc 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -21,6 +21,13 @@ if [ ! -f $TEE ]; then
 	TEE=/dev/null
 fi
 
+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+	echo "WARNING DM file $DM NOT found, resulting might be non-functional" >&2
+	DM=/dev/null
+fi
+
 if [ ! -z "$IS_HS" ]; then
 	HS_APPEND=_HS
 fi
@@ -53,6 +60,16 @@ cat << __HEADER_EOF
 			load = <0x9e800000>;
 			entry = <0x9e800000>;
 		};
+		dm {
+			description = "DM binary";
+			data = /incbin/("$DM");
+			type = "firmware";
+			arch = "arm32";
+			compression = "none";
+			os = "DM";
+			load = <0xa0000000>;
+			entry = <0xa0000000>;
+		};
 		spl {
 			description = "SPL (64-bit)";
 			data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@@ -91,7 +108,7 @@ do
 		$(basename $dtname) {
 			description = "$(basename $dtname .dtb)";
 			firmware = "atf";
-			loadables = "tee", "spl";
+			loadables = "tee", "dm", "spl";
 			fdt = "$(basename $dtname)";
 		};
 __CONF_SECTION_EOF
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 17/26] arm: mach-k3: Add platform data for j721e and j7200

[Tero Kristo]

From: Dave Gerlach <d-gerlach@ti.com>

Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 arch/arm/mach-k3/Makefile         |   2 +-
 arch/arm/mach-k3/j7200/Makefile   |   5 +
 arch/arm/mach-k3/j7200/clk-data.c | 232 ++++++++++++++++++++++++++
 arch/arm/mach-k3/j7200/dev-data.c |  71 ++++++++
 arch/arm/mach-k3/j721e/Makefile   |   5 +
 arch/arm/mach-k3/j721e/clk-data.c | 259 ++++++++++++++++++++++++++++++
 arch/arm/mach-k3/j721e/dev-data.c |  67 ++++++++
 7 files changed, 640 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/j7200/Makefile
 create mode 100644 arch/arm/mach-k3/j7200/clk-data.c
 create mode 100644 arch/arm/mach-k3/j7200/dev-data.c
 create mode 100644 arch/arm/mach-k3/j721e/Makefile
 create mode 100644 arch/arm/mach-k3/j721e/clk-data.c
 create mode 100644 arch/arm/mach-k3/j721e/dev-data.c

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 7572f56925..534ddfcd49 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,7 @@
 #	Lokesh Vutla <lokeshvutla@ti.com>
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 0000000000..ff9abd78ea
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c
new file mode 100644
index 0000000000..f5bdbdd55e
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+	"osc_19_2_mhz",
+	"osc_20_mhz",
+	"osc_24_mhz",
+	"osc_25_mhz",
+	"osc_26_mhz",
+	"osc_27_mhz",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+	"fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+	"wkup_fref_clksel_out0",
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+	"main_pll_hfosc_sel_out0",
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv2_16fft_main_0_hsdivout6_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const struct clk_data clk_list[] = {
+	CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+	CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+	CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+	CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 1, 0x43008084, 0, 1, 0),
+	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+	CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+	CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 1, 0x40f08030, 4, 1, 0),
+	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
+	CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0),
+	CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
+	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+	CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+	CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 1, 0x43008080, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 1, 0x430080b0, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 1, 0x4300808c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 1, 0x4300809c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 1, 0x430080a0, 0, 1, 0),
+	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
+	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+	CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
+	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
+	CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+	CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+	CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 4, 0x108030, 0, 4, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+	DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+	DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+	DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+	DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+	DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"),
+	DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+	DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"),
+	DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"),
+	DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
+	DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"),
+	DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(149, 2, "mcuusart_clk_sel_out0"),
+	DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+	DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"),
+	DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"),
+	DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+};
+
+const struct ti_k3_clk_platdata j7200_clk_platdata = {
+	.clk_list = clk_list,
+	.clk_list_cnt = 63,
+	.soc_dev_clk_data = soc_dev_clk_data,
+	.soc_dev_clk_data_cnt = 61,
+};
diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c
new file mode 100644
index 0000000000..6c0ee688e0
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific device platform data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+	[0] = PSC(0, 0x00400000),
+	[1] = PSC(1, 0x42000000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+	[0] = PSC_PD(0, &soc_psc_list[0], NULL),
+	[1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]),
+	[2] = PSC_PD(14, &soc_psc_list[0], NULL),
+	[3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]),
+	[4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]),
+	[5] = PSC_PD(0, &soc_psc_list[1], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[13]),
+	[2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
+	[3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[5] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[6] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL),
+	[7] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL),
+	[8] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[7]),
+	[9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+	[10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[7]),
+	[11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL),
+	[14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(30, &soc_lpsc_list[0]),
+	PSC_DEV(61, &soc_lpsc_list[1]),
+	PSC_DEV(90, &soc_lpsc_list[2]),
+	PSC_DEV(8, &soc_lpsc_list[3]),
+	PSC_DEV(92, &soc_lpsc_list[4]),
+	PSC_DEV(91, &soc_lpsc_list[5]),
+	PSC_DEV(146, &soc_lpsc_list[6]),
+	PSC_DEV(4, &soc_lpsc_list[7]),
+	PSC_DEV(4, &soc_lpsc_list[8]),
+	PSC_DEV(202, &soc_lpsc_list[9]),
+	PSC_DEV(203, &soc_lpsc_list[10]),
+	PSC_DEV(103, &soc_lpsc_list[11]),
+	PSC_DEV(104, &soc_lpsc_list[11]),
+	PSC_DEV(154, &soc_lpsc_list[11]),
+	PSC_DEV(149, &soc_lpsc_list[11]),
+	PSC_DEV(197, &soc_lpsc_list[12]),
+	PSC_DEV(103, &soc_lpsc_list[13]),
+	PSC_DEV(104, &soc_lpsc_list[14]),
+};
+
+const struct ti_k3_pd_platdata j7200_pd_platdata = {
+	.psc = soc_psc_list,
+	.pd = soc_pd_list,
+	.lpsc = soc_lpsc_list,
+	.devs = soc_dev_list,
+	.num_psc = 2,
+	.num_pd = 6,
+	.num_lpsc = 15,
+	.num_devs = 18,
+};
diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile
new file mode 100644
index 0000000000..ff9abd78ea
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c
new file mode 100644
index 0000000000..455cb81a56
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E specific clock platform data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+	"osc_19_2_mhz",
+	"osc_20_mhz",
+	"osc_24_mhz",
+	"osc_25_mhz",
+	"osc_26_mhz",
+	"osc_27_mhz",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+	"fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
+	"fss_mcu_0_ospi_1_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+	"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+	"wkup_fref_clksel_out0",
+	"hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout4_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+	"gluelogic_hfosc0_clkout",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+	"main_pll_hfosc_sel_out0",
+	"hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_2_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout2_clk",
+	"hsdiv4_16fft_main_1_hsdivout2_clk",
+	"hsdiv4_16fft_main_2_hsdivout2_clk",
+	"hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv3_16fft_main_0_hsdivout6_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const struct clk_data clk_list[] = {
+	CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+	CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+	CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+	CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 1, 0x43008084, 0, 1, 0),
+	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+	CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
+	CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+	CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 1, 0x40f08030, 4, 1, 0),
+	CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 1, 0x40f08034, 4, 1, 0),
+	CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
+	CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0),
+	CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
+	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+	CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+	CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+	CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 1, 0x43008080, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 1, 0x430080b0, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 1, 0x43008088, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 1, 0x4300808c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 1, 0x4300809c, 0, 1, 0),
+	CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 1, 0x430080a0, 0, 1, 0),
+	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
+	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
+	CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+	CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+	CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
+	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
+	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
+	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
+	CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
+	CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
+	CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+	CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+	CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 4, 0x108030, 0, 4, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
+	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+	DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+	DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+	DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+	DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+	DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+	DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"),
+	DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+	DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+	DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"),
+	DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+	DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+	DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+	DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+	DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"),
+	DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
+	DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"),
+	DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+	DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"),
+	DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+	DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+	DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
+	DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(149, 0, "mcuusart_clk_sel_out0"),
+	DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+	DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
+	DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+	DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"),
+	DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+	DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"),
+	DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+	DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+};
+
+const struct ti_k3_clk_platdata j721e_clk_platdata = {
+	.clk_list = clk_list,
+	.clk_list_cnt = 69,
+	.soc_dev_clk_data = soc_dev_clk_data,
+	.soc_dev_clk_data_cnt = 69,
+};
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
new file mode 100644
index 0000000000..e140454c1e
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E specific device platform data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+	[0] = PSC(0, 0x00400000),
+	[1] = PSC(1, 0x42000000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+	[0] = PSC_PD(0, &soc_psc_list[0], NULL),
+	[1] = PSC_PD(14, &soc_psc_list[0], NULL),
+	[2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]),
+	[3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]),
+	[4] = PSC_PD(0, &soc_psc_list[1], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
+	[3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[5] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
+	[6] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL),
+	[7] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[6]),
+	[8] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
+	[9] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[10] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[11] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL),
+	[12] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(30, &soc_lpsc_list[0]),
+	PSC_DEV(61, &soc_lpsc_list[0]),
+	PSC_DEV(146, &soc_lpsc_list[1]),
+	PSC_DEV(90, &soc_lpsc_list[2]),
+	PSC_DEV(47, &soc_lpsc_list[3]),
+	PSC_DEV(92, &soc_lpsc_list[4]),
+	PSC_DEV(91, &soc_lpsc_list[5]),
+	PSC_DEV(4, &soc_lpsc_list[6]),
+	PSC_DEV(202, &soc_lpsc_list[7]),
+	PSC_DEV(203, &soc_lpsc_list[8]),
+	PSC_DEV(103, &soc_lpsc_list[9]),
+	PSC_DEV(104, &soc_lpsc_list[9]),
+	PSC_DEV(154, &soc_lpsc_list[9]),
+	PSC_DEV(149, &soc_lpsc_list[9]),
+	PSC_DEV(197, &soc_lpsc_list[10]),
+	PSC_DEV(103, &soc_lpsc_list[11]),
+	PSC_DEV(104, &soc_lpsc_list[12]),
+};
+
+const struct ti_k3_pd_platdata j721e_pd_platdata = {
+	.psc = soc_psc_list,
+	.pd = soc_pd_list,
+	.lpsc = soc_lpsc_list,
+	.devs = soc_dev_list,
+	.num_psc = 2,
+	.num_pd = 5,
+	.num_lpsc = 13,
+	.num_devs = 17,
+};
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 18/26] arm: mach-k3: add support for detecting firmware images from FIT

[Tero Kristo]

Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-k3/common.c   | 80 +++++++++++++++++++++++++++++++++----
 arch/arm/mach-k3/common.h   |  1 +
 arch/arm/mach-k3/security.c |  3 +-
 3 files changed, 75 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 8c903f14ff..418d053610 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -27,6 +27,27 @@
 #include <elf.h>
 #include <soc.h>
 
+#ifdef CONFIG_SYS_K3_SPL_ATF
+enum {
+	IMAGE_ID_ATF,
+	IMAGE_ID_OPTEE,
+	IMAGE_ID_SPL,
+	IMAGE_ID_DM_FW,
+	IMAGE_AMT,
+};
+
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+static const char *image_os_match[IMAGE_AMT] = {
+	"arm-trusted-firmware",
+	"tee",
+	"U-Boot",
+	"DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
 	struct udevice *dev;
@@ -180,7 +201,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	typedef void __noreturn (*image_entry_noargs_t)(void);
 	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 	u32 loadaddr = 0;
-	int ret, size;
+	int ret, size = 0;
 
 	/* Release all the exclusive devices held by SPL before starting ATF */
 	ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -191,15 +212,20 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 
 	init_env();
 	start_non_linux_remote_cores();
-	size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
-			     &loadaddr);
+	if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
+		size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+				     &loadaddr);
 
 
 	/*
 	 * It is assumed that remoteproc device 1 is the corresponding
 	 * Cortex-A core which runs ATF. Make sure DT reflects the same.
 	 */
-	ret = rproc_load(1, spl_image->entry_point, 0x200);
+	if (!fit_image_info[IMAGE_ID_ATF].image_start)
+		fit_image_info[IMAGE_ID_ATF].image_start =
+			spl_image->entry_point;
+
+	ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
 	if (ret)
 		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
@@ -209,7 +235,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	ret = rproc_start(1);
 	if (ret)
 		panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
-	if (!(size > 0 && valid_elf_image(loadaddr))) {
+	if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+	    !(size > 0 && valid_elf_image(loadaddr))) {
 		debug("Shutting down...\n");
 		release_resources_for_core_shutdown();
 
@@ -217,13 +244,52 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 			asm volatile("wfe");
 	}
 
-	image_entry_noargs_t image_entry =
-		(image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+	if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+		loadaddr = load_elf_image_phdr(loadaddr);
+	} else {
+		loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+		if (valid_elf_image(loadaddr))
+			loadaddr = load_elf_image_phdr(loadaddr);
+	}
+
+	debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+	image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
 
 	image_entry();
 }
 #endif
 
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+				  size_t *p_size)
+{
+	int len;
+	int i;
+	const char *os;
+	u32 addr;
+
+	os = fdt_getprop(fit, node, "os", &len);
+	addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+	debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+	      addr, *p_size, os);
+
+	for (i = 0; i < IMAGE_AMT; i++) {
+		if (!strcmp(os, image_os_match[i])) {
+			fit_image_info[i].image_start = addr;
+			fit_image_info[i].image_len = *p_size;
+			debug("%s: matched image for ID %d\n", __func__, i);
+			break;
+		}
+	}
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+	ti_secure_image_post_process(p_image, p_size);
+#endif
+}
+#endif
+
 #if defined(CONFIG_OF_LIBFDT)
 int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
 {
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index a6dbc7808b..f421ed1bb1 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -28,3 +28,4 @@ void k3_sysfw_print_ver(void);
 void spl_enable_dcache(void);
 void mmr_unlock(phys_addr_t base, u32 partition);
 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
+void ti_secure_image_post_process(void **p_image, size_t *p_size);
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 5b5ff9ba7b..8de9739a40 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,8 +18,7 @@
 #include <spl.h>
 #include <asm/arch/sys_proto.h>
 
-void board_fit_image_post_process(const void *fit, int node, void **p_image,
-				  size_t *p_size)
+void ti_secure_image_post_process(void **p_image, size_t *p_size)
 {
 	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
 	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 19/26] arm: mach-k3: j721e: force enable A72 core 0 during spl shutdown

[Tero Kristo]

With the new raw register mode access PM drivers, A72 core is not
enabled via ti-sci services, leading into bad usecounts for the core.
This effectively shuts down the A72 core when SPL goes down. Prevent the
problem by force enabling the A72 core once, which increases the use
count.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-k3/j721e_init.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index a36e4ed603..d00a9477a2 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -306,6 +306,7 @@ u32 spl_boot_device(void)
 
 #ifdef CONFIG_SYS_K3_SPL_ATF
 
+#define J721E_DEV_A72SS0_CORE0			202
 #define J721E_DEV_MCU_RTI0			262
 #define J721E_DEV_MCU_RTI1			263
 #define J721E_DEV_MCU_ARMSS0_CPU0		250
@@ -324,10 +325,23 @@ void release_resources_for_core_shutdown(void)
 		J721E_DEV_MCU_RTI1,
 	};
 
+	const u32 get_device_ids[] = {
+		J721E_DEV_A72SS0_CORE0
+	};
+
 	ti_sci = get_ti_sci_handle();
 	dev_ops = &ti_sci->ops.dev_ops;
 	proc_ops = &ti_sci->ops.proc_ops;
 
+	/* Iterate through list of devices to get (enable) */
+	for (i = 0; i < ARRAY_SIZE(get_device_ids); i++) {
+		u32 id = get_device_ids[i];
+
+		ret = dev_ops->get_device(ti_sci, id);
+		if (ret)
+			panic("Failed to get device %u (%d)\n", id, ret);
+	}
+
 	/* Iterate through list of devices to put (shutdown) */
 	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
 		u32 id = put_device_ids[i];
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 20/26] arm: mach-k3: do board config for PM and RM only if supported

[Tero Kristo]

If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-k3/sysfw-loader.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 78c158c63f..154d2df049 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -158,11 +158,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
 		      ret);
 
 	/* Apply power/clock (PM) specific configuration to SYSFW */
+#ifdef CONFIG_CLK_TI_SCI
 	ret = board_ops->board_config_pm(ti_sci,
 					 (u64)(u32)cfg_fragment_addr,
 					 (u32)cfg_fragment_size);
 	if (ret)
 		panic("Failed to set board PM configuration (%d)\n", ret);
+#endif
 
 	/* Extract resource management (RM) specific configuration from FIT */
 	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@@ -171,12 +173,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
 		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
 		      ret);
 
+#ifdef CONFIG_CLK_TI_SCI
 	/* Apply resource management (RM) configuration to SYSFW */
 	ret = board_ops->board_config_rm(ti_sci,
 					 (u64)(u32)cfg_fragment_addr,
 					 (u32)cfg_fragment_size);
 	if (ret)
 		panic("Failed to set board RM configuration (%d)\n", ret);
+#endif
 
 	/* Extract security specific configuration from FIT */
 	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
-- 
2.17.1

--
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[PATCH 21/26] arm: mach-k3: common: Drop main r5 start

[Tero Kristo]

From: Dave Gerlach <d-gerlach@ti.com>

Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 arch/arm/mach-k3/common.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 418d053610..5582ea6d7e 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -211,7 +211,9 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 		panic("rproc failed to be initialized (%d)\n", ret);
 
 	init_env();
+#ifdef CONFIG_CLK_TI_SCI
 	start_non_linux_remote_cores();
+#endif
 	if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
 		size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
 				     &loadaddr);
-- 
2.17.1

--
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[PATCH 22/26] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver

[Tero Kristo]

Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 arch/arm/mach-k3/sysfw-loader.c | 98 +++++++++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 154d2df049..c20b601848 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -39,6 +39,43 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define K3_SYSTEM_CONTROLLER_RPROC_ID	0
 
+#define BOARDCFG_ADDRESS		0x41c80000
+
+#define COMP_TYPE_SBL_DATA		0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX	0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX	0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE	0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE	0x000e
+
+struct extboot_comp {
+	u32 comp_type;
+	u32 boot_core;
+	u32 comp_opts;
+	u64 dest_addr;
+	u32 comp_size;
+} __packed;
+
+struct extboot_header {
+	u8 magic[8];
+	u32 num_comps;
+	struct extboot_comp comps[5];
+} __packed;
+
+struct bcfg_desc {
+	u16 type;
+	u16 offset;
+	u16 size;
+	u8 devgrp;
+	u8 reserved;
+} __packed;
+
+struct bcfg_header {
+	u8 num_elems;
+	u8 sw_rev;
+	struct bcfg_desc descs[4];
+} __packed;
+
 static bool sysfw_loaded;
 static void *sysfw_load_address;
 
@@ -130,6 +167,15 @@ static void k3_sysfw_configure_using_fit(void *fit,
 	const void *cfg_fragment_addr;
 	size_t cfg_fragment_size;
 	int ret;
+#ifndef CONFIG_CLK_TI_SCI
+	u8 *buf;
+	struct extboot_header *common_header;
+	struct bcfg_header *bcfg_header;
+	struct extboot_comp *comp;
+	struct bcfg_desc *desc;
+	u32 addr;
+	bool copy_bcfg = false;
+#endif
 
 	/* Find the node holding the images information */
 	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@@ -164,6 +210,46 @@ static void k3_sysfw_configure_using_fit(void *fit,
 					 (u32)cfg_fragment_size);
 	if (ret)
 		panic("Failed to set board PM configuration (%d)\n", ret);
+#else
+	/* Initialize shared memory boardconfig buffer */
+	buf = (u8 *)BOARDCFG_ADDRESS;
+	common_header = (struct extboot_header *)buf;
+
+	/* Check if we have a struct populated by ROM in memory already */
+	if (strcmp((char *)common_header->magic, "EXTBOOT"))
+		copy_bcfg = true;
+
+	if (copy_bcfg) {
+		strcpy((char *)common_header->magic, "EXTBOOT");
+		common_header->num_comps = 1;
+
+		comp = &common_header->comps[0];
+
+		comp->comp_type = COMP_TYPE_SBL_DATA;
+		comp->boot_core = 0x10;
+		comp->comp_opts = 0;
+		addr = (u32)buf + sizeof(*common_header);
+		comp->dest_addr = addr;
+		comp->comp_size = sizeof(*bcfg_header);
+
+		bcfg_header = (struct bcfg_header *)addr;
+
+		bcfg_header->num_elems = 2;
+		bcfg_header->sw_rev = 0;
+
+		desc = &bcfg_header->descs[0];
+
+		desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+		desc->offset = sizeof(*bcfg_header);
+		desc->size = cfg_fragment_size;
+		comp->comp_size += desc->size;
+		desc->devgrp = 0;
+		desc->reserved = 0;
+		memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+		       cfg_fragment_size);
+
+		bcfg_header->descs[1].offset = desc->offset + desc->size;
+	}
 #endif
 
 	/* Extract resource management (RM) specific configuration from FIT */
@@ -180,6 +266,18 @@ static void k3_sysfw_configure_using_fit(void *fit,
 					 (u32)cfg_fragment_size);
 	if (ret)
 		panic("Failed to set board RM configuration (%d)\n", ret);
+#else
+	if (copy_bcfg) {
+		desc = &bcfg_header->descs[1];
+
+		desc->type = BOARD_CONFIG_RM_DESC_TYPE;
+		desc->size = cfg_fragment_size;
+		comp->comp_size += desc->size;
+		desc->devgrp = 0;
+		desc->reserved = 0;
+		memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+		       cfg_fragment_size);
+	}
 #endif
 
 	/* Extract security specific configuration from FIT */
-- 
2.17.1

--
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[PATCH 23/26] configs: j721e_evm_r5: Enable raw access power management features

[Tero Kristo]

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 configs/j721e_evm_r5_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 4128548100..514867635c 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -140,3 +140,9 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 24/26] configs: j721e_evm_r5: disable SCI PM drivers

[Tero Kristo]

With the sysfw rearch, PM services are no longer available for R5 SPL to
use. Instead, we will be using the raw PM register level access drivers
for any PM. Thus, disable the SCI PM drivers to reflect this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 configs/j721e_evm_r5_defconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 514867635c..62586b2f3b 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -72,7 +72,7 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -102,7 +102,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65941=y
 CONFIG_DM_REGULATOR=y
-- 
2.17.1

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 25/26] configs: j721e_evm_r5: enable FIT image post processing

[Tero Kristo]

This is used to parse the images from FIT, and to determine image types.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
 configs/j721e_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 62586b2f3b..f2c047f8e8 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -146,3 +146,4 @@ CONFIG_LIB_RATIONAL=y
 CONFIG_SPL_LIB_RATIONAL=y
 CONFIG_SPL_CLK_K3_PLL=y
 CONFIG_SPL_CLK_K3=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

--
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[PATCH 26/26] configs: j7200_evm_r5: Enable raw access power management features

[Tero Kristo]

From: Dave Gerlach <d-gerlach@ti.com>

Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 configs/j7200_evm_r5_defconfig | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 3820fc508b..19ba12e89f 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -75,7 +75,7 @@ CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -110,7 +110,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_DM_RESET=y
@@ -142,3 +142,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-- 
2.17.1

--
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[PATCH 01/26] lib: rational: copy the rational fraction lib routines from Linux

[Tom Rini]

On Tue, Nov 10, 2020 at 11:05:37AM +0200, Tero Kristo wrote:

> Copy the best rational approximation calculation routines from Linux.
> Typical usecase for these routines is to calculate the M/N divider
> values for PLLs to reach a specific clock rate.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Please say what version of the Linux kernel this is from, for easier
later re-syncing.  Thanks.

-- 
Tom
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[PATCH 01/26] lib: rational: copy the rational fraction lib routines from Linux

[Tero Kristo]

On 10/11/2020 14:55, Tom Rini wrote:
> On Tue, Nov 10, 2020 at 11:05:37AM +0200, Tero Kristo wrote:
> 
>> Copy the best rational approximation calculation routines from Linux.
>> Typical usecase for these routines is to calculate the M/N divider
>> values for PLLs to reach a specific clock rate.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> 
> Please say what version of the Linux kernel this is from, for easier
> later re-syncing.  Thanks.
> 

This is based on kernel commit:

commit 323dd2c3ed0641f49e89b4e420f9eef5d3d5a881
Author: Trent Piepho <tpiepho@gmail.com>
Date:   Wed Dec 4 16:51:57 2019 -0800

     lib/math/rational.c: fix possible incorrect result from rational 
fractions helper

-Tero
--
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[PATCH 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks

[Lokesh Vutla]

+ Simon, Peng, Lukasz

On 10/11/20 2:35 pm, Tero Kristo wrote:
> Current driver only supports registering fixed rate clocks from DT. Add
> new API which makes it possible to register fixed rate clocks directly
> from e.g. platform specific clock drivers.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>


> ---
>  drivers/clk/clk_fixed_rate.c | 45 +++++++++++++++++++++++++++++++++++-
>  include/linux/clk-provider.h |  3 +++
>  2 files changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
> index 55e1f8caa5..5556acaf86 100644
> --- a/drivers/clk/clk_fixed_rate.c
> +++ b/drivers/clk/clk_fixed_rate.c
> @@ -8,6 +8,9 @@
>  #include <dm.h>
>  #include <linux/clk-provider.h>
>  
> +#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
> +#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
> +
>  static ulong clk_fixed_rate_get_rate(struct clk *clk)
>  {
>  	return to_clk_fixed_rate(clk->dev)->fixed_rate;
> @@ -24,6 +27,15 @@ const struct clk_ops clk_fixed_rate_ops = {
>  	.enable = dummy_enable,
>  };
>  
> +static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
> +{
> +	return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
> +}
> +
> +const struct clk_ops clk_fixed_rate_raw_ops = {
> +	.get_rate = clk_fixed_rate_raw_get_rate,
> +};
> +
>  static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
>  {
>  	struct clk *clk = &to_clk_fixed_rate(dev)->clk;
> @@ -39,6 +51,30 @@ static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
>  	return 0;
>  }
>  
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> +				    ulong rate)
> +{
> +	struct clk *clk;
> +	struct clk_fixed_rate *fixed;
> +	int ret;
> +
> +	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
> +	if (!fixed)
> +		return ERR_PTR(-ENOMEM);
> +
> +	fixed->fixed_rate = rate;
> +
> +	clk = &fixed->clk;
> +
> +	ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
> +	if (ret) {
> +		kfree(fixed);
> +		return ERR_PTR(ret);
> +	}
> +
> +	return clk;
> +}
> +
>  static const struct udevice_id clk_fixed_rate_match[] = {
>  	{
>  		.compatible = "fixed-clock",
> @@ -47,7 +83,7 @@ static const struct udevice_id clk_fixed_rate_match[] = {
>  };
>  
>  U_BOOT_DRIVER(clk_fixed_rate) = {
> -	.name = "fixed_rate_clock",
> +	.name = UBOOT_DM_CLK_FIXED_RATE,
>  	.id = UCLASS_CLK,
>  	.of_match = clk_fixed_rate_match,
>  	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> @@ -55,3 +91,10 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
>  	.ops = &clk_fixed_rate_ops,
>  	.flags = DM_FLAG_PRE_RELOC,
>  };
> +
> +U_BOOT_DRIVER(clk_fixed_rate_raw) = {
> +	.name = UBOOT_DM_CLK_FIXED_RATE_RAW,
> +	.id = UCLASS_CLK,
> +	.ops = &clk_fixed_rate_raw_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 79dce8f0ad..6b50c42214 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -186,6 +186,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
>  		void __iomem *reg, u8 shift, u8 width,
>  		u8 clk_mux_flags);
>  
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> +				    ulong rate);
> +
>  const char *clk_hw_get_name(const struct clk *hw);
>  ulong clk_generic_get_rate(struct clk *clk);
>  
> 

[PATCH 06/26] clk: fix clock tree dump to properly dump out every registered clock

[Lokesh Vutla]

+Lucasz

On 10/11/20 2:35 pm, Tero Kristo wrote:
> Some clocks are not associated to a DM node, so just parsing the DM is not
> enough. This is especially true for root clocks, which typically don't have
> any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
> these out.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  cmd/clk.c | 27 +++++++++++++++++++--------
>  1 file changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/cmd/clk.c b/cmd/clk.c
> index e3c3d2f9bb..0245b97136 100644
> --- a/cmd/clk.c
> +++ b/cmd/clk.c
> @@ -18,11 +18,14 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
>  {
>  	int i, is_last;
>  	struct udevice *child;
> -	struct clk *clkp;
> +	struct clk *clkp, *parent;
>  	u32 rate;
>  
>  	clkp = dev_get_clk_ptr(dev);
>  	if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
> +		parent = clk_get_parent(clkp);
> +		if (!IS_ERR(parent) && depth == -1)
> +			return;
>  		depth++;
>  		rate = clk_get_rate(clkp);
>  
> @@ -47,6 +50,9 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
>  	}
>  
>  	list_for_each_entry(child, &dev->child_head, sibling_node) {
> +		if (child == dev)
> +			continue;
> +
>  		is_last = list_is_last(&child->sibling_node, &dev->child_head);
>  		show_clks(child, depth, (last_flag << 1) | is_last);
>  	}
> @@ -54,14 +60,19 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)
>  
>  int __weak soc_clk_dump(void)
>  {
> -	struct udevice *root;
> +	struct udevice *dev;
> +	struct uclass *uc;
> +	int ret;
>  
> -	root = dm_root();
> -	if (root) {
> -		printf(" Rate               Usecnt      Name\n");
> -		printf("------------------------------------------\n");
> -		show_clks(root, -1, 0);
> -	}
> +	ret = uclass_get(UCLASS_CLK, &uc);
> +	if (ret)
> +		return ret;
> +
> +	printf(" Rate               Usecnt      Name\n");
> +	printf("------------------------------------------\n");
> +
> +	uclass_foreach_dev(dev, uc)
> +		show_clks(dev, -1, 0);
>  
>  	return 0;
>  }
> 

[PATCH 08/26] clk: add support for setting clk rate from cmdline

[Lokesh Vutla]

+Lucasz

On 10/11/20 2:35 pm, Tero Kristo wrote:
> Add new clk subcommand "clk setfreq", for setting up a clock rate
> directly from u-boot cmdline. This is handy for any debugging purposes
> towards clocks.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  cmd/clk.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 47 insertions(+), 2 deletions(-)
> 
> diff --git a/cmd/clk.c b/cmd/clk.c
> index 0245b97136..fd7944c02e 100644
> --- a/cmd/clk.c
> +++ b/cmd/clk.c
> @@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc,
>  	return ret;
>  }
>  
> +struct udevice *clk_lookup(const char *name)
> +{
> +	int i = 0;
> +	struct udevice *dev;
> +
> +	do {
> +		uclass_get_device(UCLASS_CLK, i++, &dev);
> +		if (!strcmp(name, dev->name))
> +			return dev;
> +	} while (dev);
> +
> +	return NULL;
> +}
> +
> +static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
> +			  char *const argv[])
> +{
> +	struct clk *clk = NULL;
> +	s32 freq;
> +	struct udevice *dev;
> +
> +	freq = simple_strtoul(argv[2], NULL, 10);
> +
> +	dev = clk_lookup(argv[1]);
> +
> +	if (dev)
> +		clk = dev_get_clk_ptr(dev);
> +
> +	if (!clk) {
> +		printf("clock '%s' not found.\n", argv[1]);
> +		return -EINVAL;
> +	}
> +
> +	freq = clk_set_rate(clk, freq);
> +	if (freq < 0) {
> +		printf("set_rate failed: %d\n", freq);
> +		return CMD_RET_FAILURE;
> +	}
> +
> +	printf("set_rate returns %u\n", freq);
> +	return 0;
> +}
> +
>  static struct cmd_tbl cmd_clk_sub[] = {
>  	U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
> +	U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
>  };
>  
>  static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
> @@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
>  
>  #ifdef CONFIG_SYS_LONGHELP
>  static char clk_help_text[] =
> -	"dump - Print clock frequencies";
> +	"dump - Print clock frequencies\n"
> +	"setfreq [clk] [freq] - Set clock frequency";
>  #endif
>  
> -U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
> +U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
> 

[PATCH 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported

[Lokesh Vutla]

On 10/11/20 2:35 pm, Tero Kristo wrote:
> With the sysfw rearch, sysfw PM calls are no longer available from SPL
> level. To properly support this, remove the is_on checks and the reset
> assertion from the R5 remoteproc driver as these are not supported.
> Attempting to access unavailable services will cause the device to hang.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  drivers/remoteproc/ti_k3_r5f_rproc.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
> index 9332a63d21..b2902e7fd3 100644
> --- a/drivers/remoteproc/ti_k3_r5f_rproc.c
> +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
> @@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev)
>  {
>  	struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
>  	struct k3_r5f_core *core = dev_get_priv(dev);
> +#ifdef CONFIG_CLK_TI_SCI

Since we are checking for device state, can you make this guard under power
domain instead of clock?

>  	bool r_state;
> +#endif
>  	int ret;
>  
>  	dev_dbg(dev, "%s\n", __func__);
> @@ -804,6 +806,7 @@ static int k3_r5f_probe(struct udevice *dev)
>  		return ret;
>  	}
>  
> +#ifdef CONFIG_CLK_TI_SCI

Can you also add a comment here on why we are doing this?

Thanks and regards,
Lokesh

>  	ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
>  					       &r_state, &core->in_use);
>  	if (ret)
> @@ -817,6 +820,7 @@ static int k3_r5f_probe(struct udevice *dev)
>  
>  	/* Make sure Local reset is asserted. Redundant? */
>  	reset_assert(&core->reset);
> +#endif
>  
>  	ret = k3_r5f_rproc_configure(core);
>  	if (ret) {
> 

[PATCH 05/26] clk: fixed_rate: add API for directly registering fixed rate clocks

[Peng Fan]

> Subject: [PATCH 05/26] clk: fixed_rate: add API for directly registering fixed
> rate clocks
> 
> Current driver only supports registering fixed rate clocks from DT. Add new API
> which makes it possible to register fixed rate clocks directly from e.g. platform
> specific clock drivers.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> ---
>  drivers/clk/clk_fixed_rate.c | 45
> +++++++++++++++++++++++++++++++++++-
>  include/linux/clk-provider.h |  3 +++
>  2 files changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index
> 55e1f8caa5..5556acaf86 100644
> --- a/drivers/clk/clk_fixed_rate.c
> +++ b/drivers/clk/clk_fixed_rate.c
> @@ -8,6 +8,9 @@
>  #include <dm.h>
>  #include <linux/clk-provider.h>
> 
> +#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
> +#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
> +
>  static ulong clk_fixed_rate_get_rate(struct clk *clk)  {
>  	return to_clk_fixed_rate(clk->dev)->fixed_rate;
> @@ -24,6 +27,15 @@ const struct clk_ops clk_fixed_rate_ops = {
>  	.enable = dummy_enable,
>  };
> 
> +static ulong clk_fixed_rate_raw_get_rate(struct clk *clk) {
> +	return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate; }
> +
> +const struct clk_ops clk_fixed_rate_raw_ops = {
> +	.get_rate = clk_fixed_rate_raw_get_rate, };
> +
>  static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)  {
>  	struct clk *clk = &to_clk_fixed_rate(dev)->clk; @@ -39,6 +51,30 @@
> static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
>  	return 0;
>  }
> 
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> +				    ulong rate)
> +{
> +	struct clk *clk;
> +	struct clk_fixed_rate *fixed;
> +	int ret;
> +
> +	fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
> +	if (!fixed)
> +		return ERR_PTR(-ENOMEM);
> +
> +	fixed->fixed_rate = rate;
> +
> +	clk = &fixed->clk;
> +
> +	ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name,
> NULL);
> +	if (ret) {
> +		kfree(fixed);
> +		return ERR_PTR(ret);
> +	}
> +
> +	return clk;
> +}
> +
>  static const struct udevice_id clk_fixed_rate_match[] = {
>  	{
>  		.compatible = "fixed-clock",
> @@ -47,7 +83,7 @@ static const struct udevice_id clk_fixed_rate_match[] =
> {  };
> 
>  U_BOOT_DRIVER(clk_fixed_rate) = {
> -	.name = "fixed_rate_clock",
> +	.name = UBOOT_DM_CLK_FIXED_RATE,
>  	.id = UCLASS_CLK,
>  	.of_match = clk_fixed_rate_match,
>  	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> @@ -55,3 +91,10 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
>  	.ops = &clk_fixed_rate_ops,
>  	.flags = DM_FLAG_PRE_RELOC,
>  };
> +
> +U_BOOT_DRIVER(clk_fixed_rate_raw) = {
> +	.name = UBOOT_DM_CLK_FIXED_RATE_RAW,
> +	.id = UCLASS_CLK,
> +	.ops = &clk_fixed_rate_raw_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index
> 79dce8f0ad..6b50c42214 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -186,6 +186,9 @@ struct clk *clk_register_mux(struct device *dev, const
> char *name,
>  		void __iomem *reg, u8 shift, u8 width,
>  		u8 clk_mux_flags);
> 
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> +				    ulong rate);
> +
>  const char *clk_hw_get_name(const struct clk *hw);  ulong
> clk_generic_get_rate(struct clk *clk);
> 
> --
> 2.17.1
> 
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 00/26] TI J7 SoC HSM Rearch support series

[Lokesh Vutla]

On 10/11/20 2:35 pm, Tero Kristo wrote:
> Hello,
> 
> On TI J7 SoCs the device manager firmware is now split into two
> portions instead of the existing one which supported all services via a
> single firmware image running on DMSC core. Now, the existing DMSC core
> is dedicated for secure services only, and the PM and RM functionality
> is moved under a separate firmware image running on MCU R5 core. This
> is completely transparent for the firmware users, as the existing
> messaging mechanism (TI-SCI) routes everything to proper destination,
> except for anything that runs on MCU R5, and in our case it happens
> to be R5 SPL bootloader.

Can you update board/ti/j721e/README with the detail of the boot flow and build
steps?

Thanks and regards,
Lokesh

[PATCH 19/26] arm: mach-k3: j721e: force enable A72 core 0 during spl shutdown

[Lokesh Vutla]

On 10/11/20 2:35 pm, Tero Kristo wrote:
> With the new raw register mode access PM drivers, A72 core is not
> enabled via ti-sci services, leading into bad usecounts for the core.
> This effectively shuts down the A72 core when SPL goes down. Prevent the

When you meant SPL that is R5 going down correct?. But in this case R5 can never
go down no? I am still trying to understand what happens if this patch is not
applied.

Is it that R5 gets reset before jumping to DM firmware? Also at this point DM
services are not available no? who services this get_device request?

Thanks and regards,
Lokesh

> problem by force enabling the A72 core once, which increases the use
> count.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/mach-k3/j721e_init.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
> index a36e4ed603..d00a9477a2 100644
> --- a/arch/arm/mach-k3/j721e_init.c
> +++ b/arch/arm/mach-k3/j721e_init.c
> @@ -306,6 +306,7 @@ u32 spl_boot_device(void)
>  
>  #ifdef CONFIG_SYS_K3_SPL_ATF
>  
> +#define J721E_DEV_A72SS0_CORE0			202
>  #define J721E_DEV_MCU_RTI0			262
>  #define J721E_DEV_MCU_RTI1			263
>  #define J721E_DEV_MCU_ARMSS0_CPU0		250
> @@ -324,10 +325,23 @@ void release_resources_for_core_shutdown(void)
>  		J721E_DEV_MCU_RTI1,
>  	};
>  
> +	const u32 get_device_ids[] = {
> +		J721E_DEV_A72SS0_CORE0
> +	};
> +
>  	ti_sci = get_ti_sci_handle();
>  	dev_ops = &ti_sci->ops.dev_ops;
>  	proc_ops = &ti_sci->ops.proc_ops;
>  
> +	/* Iterate through list of devices to get (enable) */
> +	for (i = 0; i < ARRAY_SIZE(get_device_ids); i++) {
> +		u32 id = get_device_ids[i];
> +
> +		ret = dev_ops->get_device(ti_sci, id);
> +		if (ret)
> +			panic("Failed to get device %u (%d)\n", id, ret);
> +	}
> +
>  	/* Iterate through list of devices to put (shutdown) */
>  	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
>  		u32 id = put_device_ids[i];
> 

[PATCH 20/26] arm: mach-k3: do board config for PM and RM only if supported

[Lokesh Vutla]

On 10/11/20 2:35 pm, Tero Kristo wrote:
> If the raw PM support is built in, we are operating in the split
> firmware approach mode where RM and PM support is not available. In this
> case, skip the board config for these two.
> 
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
>  arch/arm/mach-k3/sysfw-loader.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
> index 78c158c63f..154d2df049 100644
> --- a/arch/arm/mach-k3/sysfw-loader.c
> +++ b/arch/arm/mach-k3/sysfw-loader.c
> @@ -158,11 +158,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
>  		      ret);
>  
>  	/* Apply power/clock (PM) specific configuration to SYSFW */
> +#ifdef CONFIG_CLK_TI_SCI

IMHO, using CONFIG_CLK_TI_SCI is hack here. Can we showhow derive this
information based on the images loaded in FIT?

Thanks and regards,
Lokesh

>  	ret = board_ops->board_config_pm(ti_sci,
>  					 (u64)(u32)cfg_fragment_addr,
>  					 (u32)cfg_fragment_size);
>  	if (ret)
>  		panic("Failed to set board PM configuration (%d)\n", ret);
> +#endif
>  
>  	/* Extract resource management (RM) specific configuration from FIT */
>  	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
> @@ -171,12 +173,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
>  		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
>  		      ret);
>  
> +#ifdef CONFIG_CLK_TI_SCI
>  	/* Apply resource management (RM) configuration to SYSFW */
>  	ret = board_ops->board_config_rm(ti_sci,
>  					 (u64)(u32)cfg_fragment_addr,
>  					 (u32)cfg_fragment_size);
>  	if (ret)
>  		panic("Failed to set board RM configuration (%d)\n", ret);
> +#endif
>  
>  	/* Extract security specific configuration from FIT */
>  	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
> 

[PATCH 21/26] arm: mach-k3: common: Drop main r5 start

[Lokesh Vutla]

On 10/11/20 2:35 pm, Tero Kristo wrote:
> From: Dave Gerlach <d-gerlach@ti.com>
> 
> Only start-up the non-linux remote cores if we are running in legacy
> boot mode. HSM rearch is not yet supporting this.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
>  arch/arm/mach-k3/common.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
> index 418d053610..5582ea6d7e 100644
> --- a/arch/arm/mach-k3/common.c
> +++ b/arch/arm/mach-k3/common.c
> @@ -211,7 +211,9 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
>  		panic("rproc failed to be initialized (%d)\n", ret);
>  
>  	init_env();
> +#ifdef CONFIG_CLK_TI_SCI

Again. This config ussage is a hack. Can we get a better way to do these things?

Thanks and regards,
Lokesh

>  	start_non_linux_remote_cores();
> +#endif
>  	if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
>  		size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
>  				     &loadaddr);
> 

[PATCH 08/26] clk: add support for setting clk rate from cmdline

[Tero Kristo]

On 15/11/2020 12:29, Lokesh Vutla wrote:
> +Lucasz

This is just a nice to have patch. Found it quite useful while debugging 
the new drivers so decided to share.

-Tero

> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> Add new clk subcommand "clk setfreq", for setting up a clock rate
>> directly from u-boot cmdline. This is handy for any debugging purposes
>> towards clocks.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   cmd/clk.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
>>   1 file changed, 47 insertions(+), 2 deletions(-)
>>
>> diff --git a/cmd/clk.c b/cmd/clk.c
>> index 0245b97136..fd7944c02e 100644
>> --- a/cmd/clk.c
>> +++ b/cmd/clk.c
>> @@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc,
>>   	return ret;
>>   }
>>   
>> +struct udevice *clk_lookup(const char *name)
>> +{
>> +	int i = 0;
>> +	struct udevice *dev;
>> +
>> +	do {
>> +		uclass_get_device(UCLASS_CLK, i++, &dev);
>> +		if (!strcmp(name, dev->name))
>> +			return dev;
>> +	} while (dev);
>> +
>> +	return NULL;
>> +}
>> +
>> +static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
>> +			  char *const argv[])
>> +{
>> +	struct clk *clk = NULL;
>> +	s32 freq;
>> +	struct udevice *dev;
>> +
>> +	freq = simple_strtoul(argv[2], NULL, 10);
>> +
>> +	dev = clk_lookup(argv[1]);
>> +
>> +	if (dev)
>> +		clk = dev_get_clk_ptr(dev);
>> +
>> +	if (!clk) {
>> +		printf("clock '%s' not found.\n", argv[1]);
>> +		return -EINVAL;
>> +	}
>> +
>> +	freq = clk_set_rate(clk, freq);
>> +	if (freq < 0) {
>> +		printf("set_rate failed: %d\n", freq);
>> +		return CMD_RET_FAILURE;
>> +	}
>> +
>> +	printf("set_rate returns %u\n", freq);
>> +	return 0;
>> +}
>> +
>>   static struct cmd_tbl cmd_clk_sub[] = {
>>   	U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
>> +	U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
>>   };
>>   
>>   static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
>> @@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
>>   
>>   #ifdef CONFIG_SYS_LONGHELP
>>   static char clk_help_text[] =
>> -	"dump - Print clock frequencies";
>> +	"dump - Print clock frequencies\n"
>> +	"setfreq [clk] [freq] - Set clock frequency";
>>   #endif
>>   
>> -U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
>> +U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
>>

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 03/26] remoteproc: k3-r5: remove sysfw PM calls if not supported

[Tero Kristo]

On 15/11/2020 12:29, Lokesh Vutla wrote:
> 
> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> With the sysfw rearch, sysfw PM calls are no longer available from SPL
>> level. To properly support this, remove the is_on checks and the reset
>> assertion from the R5 remoteproc driver as these are not supported.
>> Attempting to access unavailable services will cause the device to hang.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   drivers/remoteproc/ti_k3_r5f_rproc.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
>> index 9332a63d21..b2902e7fd3 100644
>> --- a/drivers/remoteproc/ti_k3_r5f_rproc.c
>> +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
>> @@ -781,7 +781,9 @@ static int k3_r5f_probe(struct udevice *dev)
>>   {
>>   	struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
>>   	struct k3_r5f_core *core = dev_get_priv(dev);
>> +#ifdef CONFIG_CLK_TI_SCI
> 
> Since we are checking for device state, can you make this guard under power
> domain instead of clock?

Hmm right, that would work. Will change.

> 
>>   	bool r_state;
>> +#endif
>>   	int ret;
>>   
>>   	dev_dbg(dev, "%s\n", __func__);
>> @@ -804,6 +806,7 @@ static int k3_r5f_probe(struct udevice *dev)
>>   		return ret;
>>   	}
>>   
>> +#ifdef CONFIG_CLK_TI_SCI
> 
> Can you also add a comment here on why we are doing this?

I can add an inline comment for this.

-Tero

> 
> Thanks and regards,
> Lokesh
> 
>>   	ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
>>   					       &r_state, &core->in_use);
>>   	if (ret)
>> @@ -817,6 +820,7 @@ static int k3_r5f_probe(struct udevice *dev)
>>   
>>   	/* Make sure Local reset is asserted. Redundant? */
>>   	reset_assert(&core->reset);
>> +#endif
>>   
>>   	ret = k3_r5f_rproc_configure(core);
>>   	if (ret) {
>>

--
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[PATCH 00/26] TI J7 SoC HSM Rearch support series

[Tero Kristo]

On 16/11/2020 06:13, Lokesh Vutla wrote:
> 
> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> Hello,
>>
>> On TI J7 SoCs the device manager firmware is now split into two
>> portions instead of the existing one which supported all services via a
>> single firmware image running on DMSC core. Now, the existing DMSC core
>> is dedicated for secure services only, and the PM and RM functionality
>> is moved under a separate firmware image running on MCU R5 core. This
>> is completely transparent for the firmware users, as the existing
>> messaging mechanism (TI-SCI) routes everything to proper destination,
>> except for anything that runs on MCU R5, and in our case it happens
>> to be R5 SPL bootloader.
> 
> Can you update board/ti/j721e/README with the detail of the boot flow and build
> steps?

Sure, I can craft additional patch for that purpose. Its good that j7 
has its separate doc actually, so am65x can stay in its current form.

-Tero

> 
> Thanks and regards,
> Lokesh
> 

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 19/26] arm: mach-k3: j721e: force enable A72 core 0 during spl shutdown

[Tero Kristo]

On 16/11/2020 06:21, Lokesh Vutla wrote:
> 
> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> With the new raw register mode access PM drivers, A72 core is not
>> enabled via ti-sci services, leading into bad usecounts for the core.
>> This effectively shuts down the A72 core when SPL goes down. Prevent the
> 
> When you meant SPL that is R5 going down correct?. But in this case R5 can never
> go down no? I am still trying to understand what happens if this patch is not
> applied.
> 
> Is it that R5 gets reset before jumping to DM firmware? Also at this point DM
> services are not available no? who services this get_device request?

This does not touch R5 as you see from the code, the device ID touched 
is A72SS0. Basically what happens is that A72 is booted directly by R5 
SPL, but once u-boot shutdown services kick in, they terminate A72 
power-domain because it is no longer used by any of the device drivers. 
Sysfw usecount is increased by A72 ATF, which keeps the core enabled in 
pure sysfw case, but our R5 SPL drivers do not have this info so they 
terminate it forcibly.

However, this might not be needed at all in the latest version of the 
code, as we always start a firmware image on MCU R5 and the 
release_resources_for_core_shutdown never gets called. Let me retry this 
once I re-spin this series.

-Tero

> 
> Thanks and regards,
> Lokesh
> 
>> problem by force enabling the A72 core once, which increases the use
>> count.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-k3/j721e_init.c | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
>> index a36e4ed603..d00a9477a2 100644
>> --- a/arch/arm/mach-k3/j721e_init.c
>> +++ b/arch/arm/mach-k3/j721e_init.c
>> @@ -306,6 +306,7 @@ u32 spl_boot_device(void)
>>   
>>   #ifdef CONFIG_SYS_K3_SPL_ATF
>>   
>> +#define J721E_DEV_A72SS0_CORE0			202
>>   #define J721E_DEV_MCU_RTI0			262
>>   #define J721E_DEV_MCU_RTI1			263
>>   #define J721E_DEV_MCU_ARMSS0_CPU0		250
>> @@ -324,10 +325,23 @@ void release_resources_for_core_shutdown(void)
>>   		J721E_DEV_MCU_RTI1,
>>   	};
>>   
>> +	const u32 get_device_ids[] = {
>> +		J721E_DEV_A72SS0_CORE0
>> +	};
>> +
>>   	ti_sci = get_ti_sci_handle();
>>   	dev_ops = &ti_sci->ops.dev_ops;
>>   	proc_ops = &ti_sci->ops.proc_ops;
>>   
>> +	/* Iterate through list of devices to get (enable) */
>> +	for (i = 0; i < ARRAY_SIZE(get_device_ids); i++) {
>> +		u32 id = get_device_ids[i];
>> +
>> +		ret = dev_ops->get_device(ti_sci, id);
>> +		if (ret)
>> +			panic("Failed to get device %u (%d)\n", id, ret);
>> +	}
>> +
>>   	/* Iterate through list of devices to put (shutdown) */
>>   	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
>>   		u32 id = put_device_ids[i];
>>

--
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[PATCH 20/26] arm: mach-k3: do board config for PM and RM only if supported

[Tero Kristo]

On 16/11/2020 06:23, Lokesh Vutla wrote:
> 
> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> If the raw PM support is built in, we are operating in the split
>> firmware approach mode where RM and PM support is not available. In this
>> case, skip the board config for these two.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>> ---
>>   arch/arm/mach-k3/sysfw-loader.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
>> index 78c158c63f..154d2df049 100644
>> --- a/arch/arm/mach-k3/sysfw-loader.c
>> +++ b/arch/arm/mach-k3/sysfw-loader.c
>> @@ -158,11 +158,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
>>   		      ret);
>>   
>>   	/* Apply power/clock (PM) specific configuration to SYSFW */
>> +#ifdef CONFIG_CLK_TI_SCI
> 
> IMHO, using CONFIG_CLK_TI_SCI is hack here. Can we showhow derive this
> information based on the images loaded in FIT?

At this point we have only loaded the sysfw image. DM image against 
which we could check this will only be loaded during A72 SPL FIT loading 
process, and it will only happen later.

-Tero

> 
> Thanks and regards,
> Lokesh
> 
>>   	ret = board_ops->board_config_pm(ti_sci,
>>   					 (u64)(u32)cfg_fragment_addr,
>>   					 (u32)cfg_fragment_size);
>>   	if (ret)
>>   		panic("Failed to set board PM configuration (%d)\n", ret);
>> +#endif
>>   
>>   	/* Extract resource management (RM) specific configuration from FIT */
>>   	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
>> @@ -171,12 +173,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
>>   		panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
>>   		      ret);
>>   
>> +#ifdef CONFIG_CLK_TI_SCI
>>   	/* Apply resource management (RM) configuration to SYSFW */
>>   	ret = board_ops->board_config_rm(ti_sci,
>>   					 (u64)(u32)cfg_fragment_addr,
>>   					 (u32)cfg_fragment_size);
>>   	if (ret)
>>   		panic("Failed to set board RM configuration (%d)\n", ret);
>> +#endif
>>   
>>   	/* Extract security specific configuration from FIT */
>>   	ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
>>

--
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[PATCH 21/26] arm: mach-k3: common: Drop main r5 start

[Tero Kristo]

On 16/11/2020 06:24, Lokesh Vutla wrote:
> 
> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> From: Dave Gerlach <d-gerlach@ti.com>
>>
>> Only start-up the non-linux remote cores if we are running in legacy
>> boot mode. HSM rearch is not yet supporting this.

This one, we can check against DM_FW image presence as it has been 
loaded already.

-Tero

>>
>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>> ---
>>   arch/arm/mach-k3/common.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
>> index 418d053610..5582ea6d7e 100644
>> --- a/arch/arm/mach-k3/common.c
>> +++ b/arch/arm/mach-k3/common.c
>> @@ -211,7 +211,9 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
>>   		panic("rproc failed to be initialized (%d)\n", ret);
>>   
>>   	init_env();
>> +#ifdef CONFIG_CLK_TI_SCI
> 
> Again. This config ussage is a hack. Can we get a better way to do these things?
> 
> Thanks and regards,
> Lokesh
> 
>>   	start_non_linux_remote_cores();
>> +#endif
>>   	if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
>>   		size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
>>   				     &loadaddr);
>>

--
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[PATCH 08/26] clk: add support for setting clk rate from cmdline

[Lukasz Majewski]

Hi Tero,

> On 15/11/2020 12:29, Lokesh Vutla wrote:
> > +Lucasz  
> 
> This is just a nice to have patch. Found it quite useful while
> debugging the new drivers so decided to share.
> 
> -Tero
> 
> > 
> > On 10/11/20 2:35 pm, Tero Kristo wrote:  
> >> Add new clk subcommand "clk setfreq", for setting up a clock rate
> >> directly from u-boot cmdline. This is handy for any debugging
> >> purposes towards clocks.
> >>
> >> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> >> ---
> >>   cmd/clk.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
> >>   1 file changed, 47 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/cmd/clk.c b/cmd/clk.c
> >> index 0245b97136..fd7944c02e 100644
> >> --- a/cmd/clk.c
> >> +++ b/cmd/clk.c
> >> @@ -98,8 +98,52 @@ static int do_clk_dump(struct cmd_tbl *cmdtp,
> >> int flag, int argc, return ret;
> >>   }
> >>   
> >> +struct udevice *clk_lookup(const char *name)
> >> +{
> >> +	int i = 0;
> >> +	struct udevice *dev;
> >> +
> >> +	do {
> >> +		uclass_get_device(UCLASS_CLK, i++, &dev);
> >> +		if (!strcmp(name, dev->name))
> >> +			return dev;
> >> +	} while (dev);
> >> +
> >> +	return NULL;
> >> +}
> >> +
> >> +static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int
> >> argc,
> >> +			  char *const argv[])
> >> +{
> >> +	struct clk *clk = NULL;
> >> +	s32 freq;
> >> +	struct udevice *dev;
> >> +
> >> +	freq = simple_strtoul(argv[2], NULL, 10);
> >> +
> >> +	dev = clk_lookup(argv[1]);
> >> +
> >> +	if (dev)
> >> +		clk = dev_get_clk_ptr(dev);
> >> +
> >> +	if (!clk) {
> >> +		printf("clock '%s' not found.\n", argv[1]);
> >> +		return -EINVAL;
> >> +	}
> >> +
> >> +	freq = clk_set_rate(clk, freq);
> >> +	if (freq < 0) {
> >> +		printf("set_rate failed: %d\n", freq);
> >> +		return CMD_RET_FAILURE;
> >> +	}
> >> +
> >> +	printf("set_rate returns %u\n", freq);
> >> +	return 0;
> >> +}
> >> +
> >>   static struct cmd_tbl cmd_clk_sub[] = {
> >>   	U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
> >> +	U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
> >>   };
> >>   
> >>   static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
> >> @@ -124,7 +168,8 @@ static int do_clk(struct cmd_tbl *cmdtp, int
> >> flag, int argc, 
> >>   #ifdef CONFIG_SYS_LONGHELP
> >>   static char clk_help_text[] =
> >> -	"dump - Print clock frequencies";
> >> +	"dump - Print clock frequencies\n"
> >> +	"setfreq [clk] [freq] - Set clock frequency";
> >>   #endif
> >>   
> >> -U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
> >> +U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
> >>  
> 
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Acked-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[PATCH 00/26] TI J7 SoC HSM Rearch support series

[Tom Rini]

On Mon, Nov 16, 2020 at 02:13:03PM +0200, Tero Kristo wrote:
> On 16/11/2020 06:13, Lokesh Vutla wrote:
> > 
> > 
> > On 10/11/20 2:35 pm, Tero Kristo wrote:
> > > Hello,
> > > 
> > > On TI J7 SoCs the device manager firmware is now split into two
> > > portions instead of the existing one which supported all services via a
> > > single firmware image running on DMSC core. Now, the existing DMSC core
> > > is dedicated for secure services only, and the PM and RM functionality
> > > is moved under a separate firmware image running on MCU R5 core. This
> > > is completely transparent for the firmware users, as the existing
> > > messaging mechanism (TI-SCI) routes everything to proper destination,
> > > except for anything that runs on MCU R5, and in our case it happens
> > > to be R5 SPL bootloader.
> > 
> > Can you update board/ti/j721e/README with the detail of the boot flow and build
> > steps?
> 
> Sure, I can craft additional patch for that purpose. Its good that j7 has
> its separate doc actually, so am65x can stay in its current form.

And can we please find some time to convert all of these to rST and move
under doc/board/ ?  Thanks!

-- 
Tom
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[PATCH 20/26] arm: mach-k3: do board config for PM and RM only if supported

[Lokesh Vutla]

On 16/11/20 5:57 pm, Tero Kristo wrote:
> On 16/11/2020 06:23, Lokesh Vutla wrote:
>>
>>
>> On 10/11/20 2:35 pm, Tero Kristo wrote:
>>> If the raw PM support is built in, we are operating in the split
>>> firmware approach mode where RM and PM support is not available. In this
>>> case, skip the board config for these two.
>>>
>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>> ---
>>> ? arch/arm/mach-k3/sysfw-loader.c | 4 ++++
>>> ? 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
>>> index 78c158c63f..154d2df049 100644
>>> --- a/arch/arm/mach-k3/sysfw-loader.c
>>> +++ b/arch/arm/mach-k3/sysfw-loader.c
>>> @@ -158,11 +158,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
>>> ??????????????? ret);
>>> ? ????? /* Apply power/clock (PM) specific configuration to SYSFW */
>>> +#ifdef CONFIG_CLK_TI_SCI
>>
>> IMHO, using CONFIG_CLK_TI_SCI is hack here. Can we showhow derive this
>> information based on the images loaded in FIT?
> 
> At this point we have only loaded the sysfw image. DM image against which we

This sysfw.itb contains all the board configurations?
If yes, then we are adding board configurations in sysfw.itb that does not
belong here.

If no, then can we check for the entries before loading?

Thanks and regards,
Lokesh

> could check this will only be loaded during A72 SPL FIT loading process, and it
> will only happen later.
> 
> -Tero
> 
>>
>> Thanks and regards,
>> Lokesh
>>
>>> ????? ret = board_ops->board_config_pm(ti_sci,
>>> ?????????????????????? (u64)(u32)cfg_fragment_addr,
>>> ?????????????????????? (u32)cfg_fragment_size);
>>> ????? if (ret)
>>> ????????? panic("Failed to set board PM configuration (%d)\n", ret);
>>> +#endif
>>> ? ????? /* Extract resource management (RM) specific configuration from FIT */
>>> ????? ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
>>> @@ -171,12 +173,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
>>> ????????? panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
>>> ??????????????? ret);
>>> ? +#ifdef CONFIG_CLK_TI_SCI
>>> ????? /* Apply resource management (RM) configuration to SYSFW */
>>> ????? ret = board_ops->board_config_rm(ti_sci,
>>> ?????????????????????? (u64)(u32)cfg_fragment_addr,
>>> ?????????????????????? (u32)cfg_fragment_size);
>>> ????? if (ret)
>>> ????????? panic("Failed to set board RM configuration (%d)\n", ret);
>>> +#endif
>>> ? ????? /* Extract security specific configuration from FIT */
>>> ????? ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
>>>
> 
> -- 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH 20/26] arm: mach-k3: do board config for PM and RM only if supported

[Tero Kristo]

On 17/11/2020 08:14, Lokesh Vutla wrote:
> 
> 
> On 16/11/20 5:57 pm, Tero Kristo wrote:
>> On 16/11/2020 06:23, Lokesh Vutla wrote:
>>>
>>>
>>> On 10/11/20 2:35 pm, Tero Kristo wrote:
>>>> If the raw PM support is built in, we are operating in the split
>>>> firmware approach mode where RM and PM support is not available. In this
>>>> case, skip the board config for these two.
>>>>
>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>> ---
>>>>  ? arch/arm/mach-k3/sysfw-loader.c | 4 ++++
>>>>  ? 1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
>>>> index 78c158c63f..154d2df049 100644
>>>> --- a/arch/arm/mach-k3/sysfw-loader.c
>>>> +++ b/arch/arm/mach-k3/sysfw-loader.c
>>>> @@ -158,11 +158,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
>>>>  ??????????????? ret);
>>>>  ? ????? /* Apply power/clock (PM) specific configuration to SYSFW */
>>>> +#ifdef CONFIG_CLK_TI_SCI
>>>
>>> IMHO, using CONFIG_CLK_TI_SCI is hack here. Can we showhow derive this
>>> information based on the images loaded in FIT?
>>
>> At this point we have only loaded the sysfw image. DM image against which we
> 
> This sysfw.itb contains all the board configurations?
> If yes, then we are adding board configurations in sysfw.itb that does not
> belong here.
> 
> If no, then can we check for the entries before loading?

Technically feasible yes, let me check with Dave offline what we can 
craft for this (the image generation part was done by him); the firmware 
image generator does something along these lines already, basically 
splitting the cfg portions to different images.

-Tero

> 
> Thanks and regards,
> Lokesh
> 
>> could check this will only be loaded during A72 SPL FIT loading process, and it
>> will only happen later.
>>
>> -Tero
>>
>>>
>>> Thanks and regards,
>>> Lokesh
>>>
>>>>  ????? ret = board_ops->board_config_pm(ti_sci,
>>>>  ?????????????????????? (u64)(u32)cfg_fragment_addr,
>>>>  ?????????????????????? (u32)cfg_fragment_size);
>>>>  ????? if (ret)
>>>>  ????????? panic("Failed to set board PM configuration (%d)\n", ret);
>>>> +#endif
>>>>  ? ????? /* Extract resource management (RM) specific configuration from FIT */
>>>>  ????? ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
>>>> @@ -171,12 +173,14 @@ static void k3_sysfw_configure_using_fit(void *fit,
>>>>  ????????? panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
>>>>  ??????????????? ret);
>>>>  ? +#ifdef CONFIG_CLK_TI_SCI
>>>>  ????? /* Apply resource management (RM) configuration to SYSFW */
>>>>  ????? ret = board_ops->board_config_rm(ti_sci,
>>>>  ?????????????????????? (u64)(u32)cfg_fragment_addr,
>>>>  ?????????????????????? (u32)cfg_fragment_size);
>>>>  ????? if (ret)
>>>>  ????????? panic("Failed to set board RM configuration (%d)\n", ret);
>>>> +#endif
>>>>  ? ????? /* Extract security specific configuration from FIT */
>>>>  ????? ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
>>>>
>>
>> -- 

--
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[PATCH 20/26] arm: mach-k3: do board config for PM and RM only if supported

[Tero Kristo]

On 17/11/2020 11:22, Tero Kristo wrote:
> On 17/11/2020 08:14, Lokesh Vutla wrote:
>>
>>
>> On 16/11/20 5:57 pm, Tero Kristo wrote:
>>> On 16/11/2020 06:23, Lokesh Vutla wrote:
>>>>
>>>>
>>>> On 10/11/20 2:35 pm, Tero Kristo wrote:
>>>>> If the raw PM support is built in, we are operating in the split
>>>>> firmware approach mode where RM and PM support is not available. In 
>>>>> this
>>>>> case, skip the board config for these two.
>>>>>
>>>>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>>>>> ---
>>>>> ?? arch/arm/mach-k3/sysfw-loader.c | 4 ++++
>>>>> ?? 1 file changed, 4 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-k3/sysfw-loader.c 
>>>>> b/arch/arm/mach-k3/sysfw-loader.c
>>>>> index 78c158c63f..154d2df049 100644
>>>>> --- a/arch/arm/mach-k3/sysfw-loader.c
>>>>> +++ b/arch/arm/mach-k3/sysfw-loader.c
>>>>> @@ -158,11 +158,13 @@ static void k3_sysfw_configure_using_fit(void 
>>>>> *fit,
>>>>> ???????????????? ret);
>>>>> ?? ????? /* Apply power/clock (PM) specific configuration to SYSFW */
>>>>> +#ifdef CONFIG_CLK_TI_SCI
>>>>
>>>> IMHO, using CONFIG_CLK_TI_SCI is hack here. Can we showhow derive this
>>>> information based on the images loaded in FIT?
>>>
>>> At this point we have only loaded the sysfw image. DM image against 
>>> which we
>>
>> This sysfw.itb contains all the board configurations?
>> If yes, then we are adding board configurations in sysfw.itb that does 
>> not
>> belong here.
>>
>> If no, then can we check for the entries before loading?
> 
> Technically feasible yes, let me check with Dave offline what we can 
> craft for this (the image generation part was done by him); the firmware 
> image generator does something along these lines already, basically 
> splitting the cfg portions to different images.

Ok, after some offline discussions, we ended up with a solution that for 
the sysfw_loader portion at least we have to use a config option, as 
otherwise the build process becomes completely broken with multiple 
cross dependencies towards/between external build tools etc... To make 
things a bit more clear though, I'll add a new config option called 
CONFIG_TI_DM_FW, which would indicate that we are using a separate DM 
firmware image in the system. This avoids overloading the 
CONFIG_CLK_TI_SCI or something else, even if these two effectively 
follow each other in their value.

I'll re-work the relevant patches around this and re-post.

-Tero

> 
> -Tero
> 
>>
>> Thanks and regards,
>> Lokesh
>>
>>> could check this will only be loaded during A72 SPL FIT loading 
>>> process, and it
>>> will only happen later.
>>>
>>> -Tero
>>>
>>>>
>>>> Thanks and regards,
>>>> Lokesh
>>>>
>>>>> ?????? ret = board_ops->board_config_pm(ti_sci,
>>>>> ??????????????????????? (u64)(u32)cfg_fragment_addr,
>>>>> ??????????????????????? (u32)cfg_fragment_size);
>>>>> ?????? if (ret)
>>>>> ?????????? panic("Failed to set board PM configuration (%d)\n", ret);
>>>>> +#endif
>>>>> ?? ????? /* Extract resource management (RM) specific configuration 
>>>>> from FIT */
>>>>> ?????? ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
>>>>> @@ -171,12 +173,14 @@ static void k3_sysfw_configure_using_fit(void 
>>>>> *fit,
>>>>> ?????????? panic("Error accessing %s node in FIT (%d)\n", 
>>>>> SYSFW_CFG_RM,
>>>>> ???????????????? ret);
>>>>> ?? +#ifdef CONFIG_CLK_TI_SCI
>>>>> ?????? /* Apply resource management (RM) configuration to SYSFW */
>>>>> ?????? ret = board_ops->board_config_rm(ti_sci,
>>>>> ??????????????????????? (u64)(u32)cfg_fragment_addr,
>>>>> ??????????????????????? (u32)cfg_fragment_size);
>>>>> ?????? if (ret)
>>>>> ?????????? panic("Failed to set board RM configuration (%d)\n", ret);
>>>>> +#endif
>>>>> ?? ????? /* Extract security specific configuration from FIT */
>>>>> ?????? ret = fit_get_data_by_name(fit, images, SYSFW_CFG_SEC,
>>>>>
>>>
>>> -- 
> 

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