[PATCH 1/4] ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM

[PATCH 1/4] ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM

[Marek Vasut]

The default state of SD bus and clock line is logical HI. SD card IO is
open-drain and pulls the bus lines LO. Always enable the SD bus pull ups
to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus
voltage level shifter, the pull ups are built into the level shifter,
however that has no negative impact.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
---
 arch/arm/dts/stm32mp15xx-dhcom.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index f022d8395c..9049245c5b 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -339,6 +339,20 @@
 	status = "okay";
 };
 
+&sdmmc1_b4_pins_a {
+	/*
+	 * SD bus pull-up resistors:
+	 * - optional on SoMs with SD voltage translator
+	 * - mandatory on SoMs without SD voltage translator
+	 */
+	pins1 {
+		bias-pull-up;
+	};
+	pins2 {
+		bias-pull-up;
+	};
+};
+
 &sdmmc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
-- 
2.29.2

[PATCH 2/4] ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock

[Marek Vasut]

The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter
or without one on the SDMMC1 interface. Because the SDMMC1 interface is
limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback
clock to permit operation of the same U-Boot image on both SoM with and
without voltage level shifter.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
---
 arch/arm/dts/stm32mp15xx-dhcom.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index 9049245c5b..dafcce4323 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -333,7 +333,6 @@
 	disable-wp;
 	st,sig-dir;
 	st,neg-edge;
-	st,use-ckin;
 	bus-width = <4>;
 	vmmc-supply = <&vdd_sd>;
 	status = "okay";
-- 
2.29.2

[PATCH 3/4] ARM: dts: stm32: Enable SDMMC3 on DH DRC02

[Marek Vasut]

The DH DRC02 board has an on-board microSD slot,
add DT properties to enable the slot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
---
NOTE: Large part of this should be in the DHCOM SoM DT, however
      a DT sync should only happen after Linux 5.10.y and U-Boot
      2021.01 are out.
---
 arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
index 5a237a3b7b..e8508aa4d5 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
@@ -105,9 +105,18 @@
 	 * On DRC02, the SoM does not have SDIO WiFi. The pins
 	 * are used for on-board microSD slot instead.
 	 */
-	/delete-property/broken-cd;
-	cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	pinctrl-names = "default", "opendrain", "sleep";
+	pinctrl-0 = <&sdmmc3_b4_pins_a>;
+	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+	cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
 	disable-wp;
+	st,neg-edge;
+	bus-width = <4>;
+	vmmc-supply = <&v3v3>;
+	vqmmc-supply = <&v3v3>;
+	mmc-ddr-3_3v;
+	status = "okay";
 };
 
 &spi1 {
-- 
2.29.2

[PATCH 4/4] ARM: dts: stm32: Add USB OTG ID pin on DH AV96

[Marek Vasut]

Add USB OTG ID pin mux and switch the USB OTG port
from peripheral to OTG mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
---
 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
index 88f25d89b2..9b5dda318e 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
@@ -192,7 +192,8 @@
 };
 
 &usbotg_hs {
-	dr_mode = "peripheral";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	pinctrl-names = "default";
 	phys = <&usbphyc_port1 0>;
 	phy-names = "usb2-phy";
 	status = "okay";
-- 
2.29.2

[PATCH 4/4] ARM: dts: stm32: Add USB OTG ID pin on DH AV96

[Patrick DELAUNAY]

Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mardi 1 d?cembre 2020 11:29
>
> Add USB OTG ID pin mux and switch the USB OTG port from peripheral to OTG mode.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
>   arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> index 88f25d89b2..9b5dda318e 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
> @@ -192,7 +192,8 @@
>   };
>   
>   &usbotg_hs {
> -	dr_mode = "peripheral";
> +	pinctrl-0 = <&usbotg_hs_pins_a>;
> +	pinctrl-names = "default";
>   	phys = <&usbphyc_port1 0>;
>   	phy-names = "usb2-phy";
>   	status = "okay";
> --
> 2.29.2
>

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Thanks

Patrick

FW: [PATCH 1/4] ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM

[Patrick DELAUNAY]

Hi Marek,

From: Marek Vasut <marex@denx.de>
> Sent: mardi 1 d?cembre 2020 11:29
>
> The default state of SD bus and clock line is logical HI. SD card IO is open-drain and pulls the bus lines LO. Always enable the SD bus pull ups to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus voltage level shifter, the pull ups are built into the level shifter, however that has no negative impact.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
>   arch/arm/dts/stm32mp15xx-dhcom.dtsi | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> index f022d8395c..9049245c5b 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> @@ -339,6 +339,20 @@
>   	status = "okay";
>   };
>   
> +&sdmmc1_b4_pins_a {
> +	/*
> +	 * SD bus pull-up resistors:
> +	 * - optional on SoMs with SD voltage translator
> +	 * - mandatory on SoMs without SD voltage translator
> +	 */
> +	pins1 {
> +		bias-pull-up;
> +	};
> +	pins2 {
> +		bias-pull-up;
> +	};
> +};
> +
>   &sdmmc2 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
> --
> 2.29.2
>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

For the serie:? the target is next or it is a bugfix for master / v2021.01 ?

Thanks

Patrick

[PATCH 2/4] ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock

[Patrick DELAUNAY]

Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mardi 1 d?cembre 2020 11:29
>
> The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter or without one on the SDMMC1 interface. Because the SDMMC1 interface is limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback clock to permit operation of the same U-Boot image on both SoM with and without voltage level shifter.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
>   arch/arm/dts/stm32mp15xx-dhcom.dtsi | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> index 9049245c5b..dafcce4323 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> @@ -333,7 +333,6 @@
>   	disable-wp;
>   	st,sig-dir;
>   	st,neg-edge;
> -	st,use-ckin;
>   	bus-width = <4>;
>   	vmmc-supply = <&vdd_sd>;
>   	status = "okay";
> --
> 2.29.2
>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Thanks

Patrick

[PATCH 3/4] ARM: dts: stm32: Enable SDMMC3 on DH DRC02

[Patrick DELAUNAY]

Hi Marek,
> From: Marek Vasut <marex@denx.de>
> Sent: mardi 1 d?cembre 2020 11:29
>
> The DH DRC02 board has an on-board microSD slot, add DT properties to enable the slot.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
> NOTE: Large part of this should be in the DHCOM SoM DT, however
>        a DT sync should only happen after Linux 5.10.y and U-Boot
>        2021.01 are out.
> ---
>   arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> index 5a237a3b7b..e8508aa4d5 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts
> @@ -105,9 +105,18 @@
>   	 * On DRC02, the SoM does not have SDIO WiFi. The pins
>   	 * are used for on-board microSD slot instead.
>   	 */
> -	/delete-property/broken-cd;
> -	cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
> +	pinctrl-names = "default", "opendrain", "sleep";
> +	pinctrl-0 = <&sdmmc3_b4_pins_a>;
> +	pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
> +	pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
> +	cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
>   	disable-wp;
> +	st,neg-edge;
> +	bus-width = <4>;To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Patrice CHOTARD <patrice.chotard@st.com>; Patrick DELAUNAY <patrick.delaunay@st.com>
> Subject: [PATCH 2/4] ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock
> Importance: High
>
>
> +	vmmc-supply = <&v3v3>;
> +	vqmmc-supply = <&v3v3>;
> +	mmc-ddr-3_3v;
> +	status = "okay";
>   };
>   
>   &spi1 {
> --
> 2.29.2
>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Thanks

Patrick

FW: [PATCH 1/4] ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM

[Marek Vasut]

On 12/8/20 6:20 PM, Patrick DELAUNAY wrote:
> Hi Marek,

Hi,

[...]

> For the serie:? the target is next or it is a bugfix for master / 
> v2021.01 ?

This is for 2021.01 , it corrects a couple of random things here and there.

FW: [PATCH 1/4] ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM

[Patrick DELAUNAY]

Hi Marek,

On 12/8/20 6:26 PM, Marek Vasut wrote:
> On 12/8/20 6:20 PM, Patrick DELAUNAY wrote:
>> Hi Marek,
>
> Hi,
>
> [...]
>
>> For the serie:? the target is next or it is a bugfix for master / 
>> v2021.01 ?
>
> This is for 2021.01 , it corrects a couple of random things here and 
> there.


For the serie:

Applied to u-boot-stm/master.

Thanks

Patrick