* [Intel-gfx] [RFC 0/2] Display glitches fixes
@ 2020-11-30 9:16 Anshuman Gupta
2020-11-30 9:16 ` [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required Anshuman Gupta
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: Anshuman Gupta @ 2020-11-30 9:16 UTC (permalink / raw)
To: intel-gfx
This series addressed the display glitches observed on
TGL chrome-OS platform.
Anshuman Gupta (2):
drm/i915/dp: optimize pps_lock wherever required
drm/i915/display: Protect pipe_update against dc3co exit
drivers/gpu/drm/i915/display/intel_display.c | 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++-
2 files changed, 48 insertions(+), 2 deletions(-)
--
2.26.2
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^ permalink raw reply [flat|nested] 17+ messages in thread* [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required 2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta @ 2020-11-30 9:16 ` Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes Patchwork 2 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-11-30 9:16 UTC (permalink / raw) To: intel-gfx Reading backlight status from PPS register doesn't require AUX power on the platform which has South Display Engine on PCH. It invokes a unnecessary power well enable/disable noise. optimize it wherever is possible. Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3896d08c4177..37371aa5f7c5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -892,6 +892,47 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) return 0; } +/* + * Platform with PCH based SDE doesn't require to enable AUX power + * for simple PPS register access like whether backlight is enabled. + * use pch_pps_lock()/pch_pps_unlock() wherever we don't require + * aux power to avoid unnecessary power well enable/disable back + * and forth. + */ +static intel_wakeref_t +pch_pps_lock(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + intel_wakeref_t wakeref; + + if (!HAS_PCH_SPLIT(dev_priv)) + wakeref = intel_display_power_get(dev_priv, + intel_aux_power_domain(dp_to_dig_port(intel_dp))); + else + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + + mutex_lock(&dev_priv->pps_mutex); + + return wakeref; +} + +static intel_wakeref_t +pch_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + mutex_unlock(&dev_priv->pps_mutex); + + if (!HAS_PCH_SPLIT(dev_priv)) + intel_display_power_put(dev_priv, + intel_aux_power_domain(dp_to_dig_port(intel_dp)), + wakeref); + else + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return 0; +} + #define with_pps_lock(dp, wf) \ for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) @@ -3449,8 +3490,10 @@ static void intel_edp_backlight_power(struct intel_connector *connector, bool is_enabled; is_enabled = false; - with_pps_lock(intel_dp, wakeref) - is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; + wakeref = pch_pps_lock(intel_dp); + is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; + pch_pps_unlock(intel_dp, wakeref); + if (is_enabled == enable) return; -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta @ 2020-11-30 9:16 ` Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes Patchwork 2 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-11-30 9:16 UTC (permalink / raw) To: intel-gfx; +Cc: imre.deak, ville.syrjala, Anshuman Gupta, stable At usual case DC3CO exit happen automatically by DMC f/w whenever PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. But there are certain scenario where DC3CO Disallowed by driver asynchronous with flips. In such scenario display engine could be already in DC3CO state and driver has disallowed it, It initiates DC3CO exit sequence in DMC f/w which requires a dc3co exit delay of 200us in driver. It requires to protect intel_pipe_update_{update_end} with dc3co exit delay. Cc: Imre Deak <imre.deak@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ba26545392bc..3b81b98c0daf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, else intel_fbc_enable(state, crtc); + /* Protect intel_pipe_update_{start,end} with power_domians lock */ + mutex_lock(&dev_priv->power_domains.lock); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, i9xx_update_planes_on_crtc(state, crtc); intel_pipe_update_end(new_crtc_state); + mutex_unlock(&dev_prive->power_domains.lock); /* * We usually enable FIFO underrun interrupts as part of the -- 2.26.2 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-11-30 9:16 ` Anshuman Gupta 0 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-11-30 9:16 UTC (permalink / raw) To: intel-gfx; +Cc: stable At usual case DC3CO exit happen automatically by DMC f/w whenever PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. But there are certain scenario where DC3CO Disallowed by driver asynchronous with flips. In such scenario display engine could be already in DC3CO state and driver has disallowed it, It initiates DC3CO exit sequence in DMC f/w which requires a dc3co exit delay of 200us in driver. It requires to protect intel_pipe_update_{update_end} with dc3co exit delay. Cc: Imre Deak <imre.deak@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ba26545392bc..3b81b98c0daf 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, else intel_fbc_enable(state, crtc); + /* Protect intel_pipe_update_{start,end} with power_domians lock */ + mutex_lock(&dev_priv->power_domains.lock); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, i9xx_update_planes_on_crtc(state, crtc); intel_pipe_update_end(new_crtc_state); + mutex_unlock(&dev_prive->power_domains.lock); /* * We usually enable FIFO underrun interrupts as part of the -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-11-30 9:16 ` [Intel-gfx] " Anshuman Gupta @ 2020-11-30 15:28 ` Imre Deak -1 siblings, 0 replies; 17+ messages in thread From: Imre Deak @ 2020-11-30 15:28 UTC (permalink / raw) To: Anshuman Gupta; +Cc: intel-gfx, ville.syrjala, stable On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > At usual case DC3CO exit happen automatically by DMC f/w whenever > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > But there are certain scenario where DC3CO Disallowed by driver > asynchronous with flips. In such scenario display engine could > be already in DC3CO state and driver has disallowed it, > It initiates DC3CO exit sequence in DMC f/w which requires a > dc3co exit delay of 200us in driver. > It requires to protect intel_pipe_update_{update_end} with > dc3co exit delay. > > Cc: Imre Deak <imre.deak@intel.com> > Cc: <stable@vger.kernel.org> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> To make sure that it doesn't hide the root cause (or affects unrelated platforms), I'd only add locking around DC3co changes with a new lock, using lock/unlock helpers in intel_display_power.c called from intel_pipe_update_start/end. Also please submit this patch separately, w/o the optimization in patch 1/2, so we know that this change fixes the problem. --Imre > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index ba26545392bc..3b81b98c0daf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > else > intel_fbc_enable(state, crtc); > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > + mutex_lock(&dev_priv->power_domains.lock); > /* Perform vblank evasion around commit operation */ > intel_pipe_update_start(new_crtc_state); > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > i9xx_update_planes_on_crtc(state, crtc); > > intel_pipe_update_end(new_crtc_state); > + mutex_unlock(&dev_prive->power_domains.lock); > > /* > * We usually enable FIFO underrun interrupts as part of the > -- > 2.26.2 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-11-30 15:28 ` Imre Deak 0 siblings, 0 replies; 17+ messages in thread From: Imre Deak @ 2020-11-30 15:28 UTC (permalink / raw) To: Anshuman Gupta; +Cc: intel-gfx, stable On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > At usual case DC3CO exit happen automatically by DMC f/w whenever > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > But there are certain scenario where DC3CO Disallowed by driver > asynchronous with flips. In such scenario display engine could > be already in DC3CO state and driver has disallowed it, > It initiates DC3CO exit sequence in DMC f/w which requires a > dc3co exit delay of 200us in driver. > It requires to protect intel_pipe_update_{update_end} with > dc3co exit delay. > > Cc: Imre Deak <imre.deak@intel.com> > Cc: <stable@vger.kernel.org> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> To make sure that it doesn't hide the root cause (or affects unrelated platforms), I'd only add locking around DC3co changes with a new lock, using lock/unlock helpers in intel_display_power.c called from intel_pipe_update_start/end. Also please submit this patch separately, w/o the optimization in patch 1/2, so we know that this change fixes the problem. --Imre > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index ba26545392bc..3b81b98c0daf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > else > intel_fbc_enable(state, crtc); > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > + mutex_lock(&dev_priv->power_domains.lock); > /* Perform vblank evasion around commit operation */ > intel_pipe_update_start(new_crtc_state); > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > i9xx_update_planes_on_crtc(state, crtc); > > intel_pipe_update_end(new_crtc_state); > + mutex_unlock(&dev_prive->power_domains.lock); > > /* > * We usually enable FIFO underrun interrupts as part of the > -- > 2.26.2 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-11-30 15:28 ` [Intel-gfx] " Imre Deak @ 2020-11-30 16:16 ` Anshuman Gupta -1 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-11-30 16:16 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx, ville.syrjala, stable On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > But there are certain scenario where DC3CO Disallowed by driver > > asynchronous with flips. In such scenario display engine could > > be already in DC3CO state and driver has disallowed it, > > It initiates DC3CO exit sequence in DMC f/w which requires a > > dc3co exit delay of 200us in driver. > > It requires to protect intel_pipe_update_{update_end} with > > dc3co exit delay. > > > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > To make sure that it doesn't hide the root cause (or affects unrelated > platforms), I'd only add locking around DC3co changes with a new lock, > using lock/unlock helpers in intel_display_power.c called from > intel_pipe_update_start/end. > > Also please submit this patch separately, w/o the optimization in patch > 1/2, so we know that this change fixes the problem. Thanks imre for review comments, i will send a new patch with review comments fixed. Anshuman Gupta. > > --Imre > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ba26545392bc..3b81b98c0daf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > else > > intel_fbc_enable(state, crtc); > > > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > > + mutex_lock(&dev_priv->power_domains.lock); > > /* Perform vblank evasion around commit operation */ > > intel_pipe_update_start(new_crtc_state); > > > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > i9xx_update_planes_on_crtc(state, crtc); > > > > intel_pipe_update_end(new_crtc_state); > > + mutex_unlock(&dev_prive->power_domains.lock); > > > > /* > > * We usually enable FIFO underrun interrupts as part of the > > -- > > 2.26.2 > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-11-30 16:16 ` Anshuman Gupta 0 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-11-30 16:16 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx, stable On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > But there are certain scenario where DC3CO Disallowed by driver > > asynchronous with flips. In such scenario display engine could > > be already in DC3CO state and driver has disallowed it, > > It initiates DC3CO exit sequence in DMC f/w which requires a > > dc3co exit delay of 200us in driver. > > It requires to protect intel_pipe_update_{update_end} with > > dc3co exit delay. > > > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > To make sure that it doesn't hide the root cause (or affects unrelated > platforms), I'd only add locking around DC3co changes with a new lock, > using lock/unlock helpers in intel_display_power.c called from > intel_pipe_update_start/end. > > Also please submit this patch separately, w/o the optimization in patch > 1/2, so we know that this change fixes the problem. Thanks imre for review comments, i will send a new patch with review comments fixed. Anshuman Gupta. > > --Imre > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ba26545392bc..3b81b98c0daf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > else > > intel_fbc_enable(state, crtc); > > > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > > + mutex_lock(&dev_priv->power_domains.lock); > > /* Perform vblank evasion around commit operation */ > > intel_pipe_update_start(new_crtc_state); > > > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > i9xx_update_planes_on_crtc(state, crtc); > > > > intel_pipe_update_end(new_crtc_state); > > + mutex_unlock(&dev_prive->power_domains.lock); > > > > /* > > * We usually enable FIFO underrun interrupts as part of the > > -- > > 2.26.2 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-11-30 15:28 ` [Intel-gfx] " Imre Deak @ 2020-12-04 8:10 ` Anshuman Gupta -1 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-12-04 8:10 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx, ville.syrjala, stable On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > But there are certain scenario where DC3CO Disallowed by driver > > asynchronous with flips. In such scenario display engine could > > be already in DC3CO state and driver has disallowed it, > > It initiates DC3CO exit sequence in DMC f/w which requires a > > dc3co exit delay of 200us in driver. > > It requires to protect intel_pipe_update_{update_end} with > > dc3co exit delay. > > > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > To make sure that it doesn't hide the root cause (or affects unrelated > platforms), I'd only add locking around DC3co changes with a new lock, > using lock/unlock helpers in intel_display_power.c called from > intel_pipe_update_start/end. > > Also please submit this patch separately, w/o the optimization in patch > 1/2, so we know that this change fixes the problem. This patch doesn't seems to fix the issue. Looks like there is some other set of display register updates before completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. Thanks, Anshuman Gupta. > > --Imre > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ba26545392bc..3b81b98c0daf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > else > > intel_fbc_enable(state, crtc); > > > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > > + mutex_lock(&dev_priv->power_domains.lock); > > /* Perform vblank evasion around commit operation */ > > intel_pipe_update_start(new_crtc_state); > > > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > i9xx_update_planes_on_crtc(state, crtc); > > > > intel_pipe_update_end(new_crtc_state); > > + mutex_unlock(&dev_prive->power_domains.lock); > > > > /* > > * We usually enable FIFO underrun interrupts as part of the > > -- > > 2.26.2 > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-12-04 8:10 ` Anshuman Gupta 0 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-12-04 8:10 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx, stable On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > But there are certain scenario where DC3CO Disallowed by driver > > asynchronous with flips. In such scenario display engine could > > be already in DC3CO state and driver has disallowed it, > > It initiates DC3CO exit sequence in DMC f/w which requires a > > dc3co exit delay of 200us in driver. > > It requires to protect intel_pipe_update_{update_end} with > > dc3co exit delay. > > > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: <stable@vger.kernel.org> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > To make sure that it doesn't hide the root cause (or affects unrelated > platforms), I'd only add locking around DC3co changes with a new lock, > using lock/unlock helpers in intel_display_power.c called from > intel_pipe_update_start/end. > > Also please submit this patch separately, w/o the optimization in patch > 1/2, so we know that this change fixes the problem. This patch doesn't seems to fix the issue. Looks like there is some other set of display register updates before completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. Thanks, Anshuman Gupta. > > --Imre > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ba26545392bc..3b81b98c0daf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15924,6 +15924,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > else > > intel_fbc_enable(state, crtc); > > > > + /* Protect intel_pipe_update_{start,end} with power_domians lock */ > > + mutex_lock(&dev_priv->power_domains.lock); > > /* Perform vblank evasion around commit operation */ > > intel_pipe_update_start(new_crtc_state); > > > > @@ -15935,6 +15937,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > i9xx_update_planes_on_crtc(state, crtc); > > > > intel_pipe_update_end(new_crtc_state); > > + mutex_unlock(&dev_prive->power_domains.lock); > > > > /* > > * We usually enable FIFO underrun interrupts as part of the > > -- > > 2.26.2 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-12-04 8:10 ` [Intel-gfx] " Anshuman Gupta @ 2020-12-04 15:51 ` Ville Syrjälä -1 siblings, 0 replies; 17+ messages in thread From: Ville Syrjälä @ 2020-12-04 15:51 UTC (permalink / raw) To: Anshuman Gupta; +Cc: Imre Deak, intel-gfx, stable On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote: > On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > > But there are certain scenario where DC3CO Disallowed by driver > > > asynchronous with flips. In such scenario display engine could > > > be already in DC3CO state and driver has disallowed it, > > > It initiates DC3CO exit sequence in DMC f/w which requires a > > > dc3co exit delay of 200us in driver. > > > It requires to protect intel_pipe_update_{update_end} with > > > dc3co exit delay. > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > Cc: <stable@vger.kernel.org> > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > To make sure that it doesn't hide the root cause (or affects unrelated > > platforms), I'd only add locking around DC3co changes with a new lock, > > using lock/unlock helpers in intel_display_power.c called from > > intel_pipe_update_start/end. > > > > Also please submit this patch separately, w/o the optimization in patch > > 1/2, so we know that this change fixes the problem. > This patch doesn't seems to fix the issue. > Looks like there is some other set of display register updates before > completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. Not really sure I understand the DC3CO issue here, nor how grabbing a mutex across the update could help. But anyways, maybe we should just: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2e2dd746921f..96276f0feddc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) drm_atomic_helper_wait_for_dependencies(&state->base); - if (state->modeset) - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * the culprit. */ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); - intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); } + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); /* To get the DMC out of equation entirely for all plane updates? -- Ville Syrjälä Intel ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-12-04 15:51 ` Ville Syrjälä 0 siblings, 0 replies; 17+ messages in thread From: Ville Syrjälä @ 2020-12-04 15:51 UTC (permalink / raw) To: Anshuman Gupta; +Cc: intel-gfx, stable On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote: > On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > > But there are certain scenario where DC3CO Disallowed by driver > > > asynchronous with flips. In such scenario display engine could > > > be already in DC3CO state and driver has disallowed it, > > > It initiates DC3CO exit sequence in DMC f/w which requires a > > > dc3co exit delay of 200us in driver. > > > It requires to protect intel_pipe_update_{update_end} with > > > dc3co exit delay. > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > Cc: <stable@vger.kernel.org> > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > To make sure that it doesn't hide the root cause (or affects unrelated > > platforms), I'd only add locking around DC3co changes with a new lock, > > using lock/unlock helpers in intel_display_power.c called from > > intel_pipe_update_start/end. > > > > Also please submit this patch separately, w/o the optimization in patch > > 1/2, so we know that this change fixes the problem. > This patch doesn't seems to fix the issue. > Looks like there is some other set of display register updates before > completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. Not really sure I understand the DC3CO issue here, nor how grabbing a mutex across the update could help. But anyways, maybe we should just: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2e2dd746921f..96276f0feddc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) drm_atomic_helper_wait_for_dependencies(&state->base); - if (state->modeset) - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * the culprit. */ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); - intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); } + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); /* To get the DMC out of equation entirely for all plane updates? -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-12-04 15:51 ` [Intel-gfx] " Ville Syrjälä @ 2020-12-07 7:57 ` Anshuman Gupta -1 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-12-07 7:57 UTC (permalink / raw) To: Ville Syrjälä; +Cc: Imre Deak, intel-gfx, stable On 2020-12-04 at 17:51:34 +0200, Ville Syrjälä wrote: > On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote: > > On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > > > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > > > But there are certain scenario where DC3CO Disallowed by driver > > > > asynchronous with flips. In such scenario display engine could > > > > be already in DC3CO state and driver has disallowed it, > > > > It initiates DC3CO exit sequence in DMC f/w which requires a > > > > dc3co exit delay of 200us in driver. > > > > It requires to protect intel_pipe_update_{update_end} with > > > > dc3co exit delay. > > > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > Cc: <stable@vger.kernel.org> > > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > > > To make sure that it doesn't hide the root cause (or affects unrelated > > > platforms), I'd only add locking around DC3co changes with a new lock, > > > using lock/unlock helpers in intel_display_power.c called from > > > intel_pipe_update_start/end. > > > > > > Also please submit this patch separately, w/o the optimization in patch > > > 1/2, so we know that this change fixes the problem. > > This patch doesn't seems to fix the issue. > > Looks like there is some other set of display register updates before > > completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. > > Not really sure I understand the DC3CO issue here, nor how grabbing a > mutex across the update could help. Thanks Ville for providing your input here, the display glitches is fixed by https://patchwork.freedesktop.org/patch/405585/?series=84394&rev=2 patch in case of brightness being updated simultaneously with flips, so it was our wild guess that if intel_pipe_update_start triggers before completing DC3CO exit delay in tgl_disable_dc3co could cause the display glitches but that was not true. > > But anyways, maybe we should just: > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 2e2dd746921f..96276f0feddc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > drm_atomic_helper_wait_for_dependencies(&state->base); > > - if (state->modeset) > - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); Certainly this should fix the issue. I will try this out but i feel this could cause heavy lock contention around power_domains->lock in case brightness being updated rapidly as the scenario of this issue. We would also need https://patchwork.freedesktop.org/patch/405585/?series=84394&rev=2 patch as well ? Thanks, Anshuman Gupta. > > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { > @@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > * the culprit. > */ > intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); > - intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > } > + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); > > /* > > To get the DMC out of equation entirely for all plane updates? > > -- > Ville Syrjälä > Intel ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-12-07 7:57 ` Anshuman Gupta 0 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-12-07 7:57 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, stable On 2020-12-04 at 17:51:34 +0200, Ville Syrjälä wrote: > On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote: > > On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > > > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > > > But there are certain scenario where DC3CO Disallowed by driver > > > > asynchronous with flips. In such scenario display engine could > > > > be already in DC3CO state and driver has disallowed it, > > > > It initiates DC3CO exit sequence in DMC f/w which requires a > > > > dc3co exit delay of 200us in driver. > > > > It requires to protect intel_pipe_update_{update_end} with > > > > dc3co exit delay. > > > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > Cc: <stable@vger.kernel.org> > > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > > > To make sure that it doesn't hide the root cause (or affects unrelated > > > platforms), I'd only add locking around DC3co changes with a new lock, > > > using lock/unlock helpers in intel_display_power.c called from > > > intel_pipe_update_start/end. > > > > > > Also please submit this patch separately, w/o the optimization in patch > > > 1/2, so we know that this change fixes the problem. > > This patch doesn't seems to fix the issue. > > Looks like there is some other set of display register updates before > > completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. > > Not really sure I understand the DC3CO issue here, nor how grabbing a > mutex across the update could help. Thanks Ville for providing your input here, the display glitches is fixed by https://patchwork.freedesktop.org/patch/405585/?series=84394&rev=2 patch in case of brightness being updated simultaneously with flips, so it was our wild guess that if intel_pipe_update_start triggers before completing DC3CO exit delay in tgl_disable_dc3co could cause the display glitches but that was not true. > > But anyways, maybe we should just: > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 2e2dd746921f..96276f0feddc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > drm_atomic_helper_wait_for_dependencies(&state->base); > > - if (state->modeset) > - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); Certainly this should fix the issue. I will try this out but i feel this could cause heavy lock contention around power_domains->lock in case brightness being updated rapidly as the scenario of this issue. We would also need https://patchwork.freedesktop.org/patch/405585/?series=84394&rev=2 patch as well ? Thanks, Anshuman Gupta. > > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { > @@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > * the culprit. > */ > intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); > - intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > } > + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); > > /* > > To get the DMC out of equation entirely for all plane updates? > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit 2020-12-04 15:51 ` [Intel-gfx] " Ville Syrjälä @ 2020-12-08 9:11 ` Anshuman Gupta -1 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-12-08 9:11 UTC (permalink / raw) To: Ville Syrjälä, imre.deak; +Cc: intel-gfx, stable On 2020-12-04 at 17:51:34 +0200, Ville Syrjälä wrote: > On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote: > > On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > > > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > > > But there are certain scenario where DC3CO Disallowed by driver > > > > asynchronous with flips. In such scenario display engine could > > > > be already in DC3CO state and driver has disallowed it, > > > > It initiates DC3CO exit sequence in DMC f/w which requires a > > > > dc3co exit delay of 200us in driver. > > > > It requires to protect intel_pipe_update_{update_end} with > > > > dc3co exit delay. > > > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > Cc: <stable@vger.kernel.org> > > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > > > To make sure that it doesn't hide the root cause (or affects unrelated > > > platforms), I'd only add locking around DC3co changes with a new lock, > > > using lock/unlock helpers in intel_display_power.c called from > > > intel_pipe_update_start/end. > > > > > > Also please submit this patch separately, w/o the optimization in patch > > > 1/2, so we know that this change fixes the problem. > > This patch doesn't seems to fix the issue. > > Looks like there is some other set of display register updates before > > completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. > > Not really sure I understand the DC3CO issue here, nor how grabbing a > mutex across the update could help. > > But anyways, maybe we should just: > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 2e2dd746921f..96276f0feddc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > drm_atomic_helper_wait_for_dependencies(&state->base); > > - if (state->modeset) > - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); > > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { > @@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > * the culprit. > */ > intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); > - intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > } > + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); > > /* > > To get the DMC out of equation entirely for all plane updates? Hi Ville / Imre , Above suggested chnages is not helping to fix the display glitches. Could you please provide your inputs to debug the possible root cause considering the patch https://patchwork.freedesktop.org/patch/405585/?series=84394&rev=2 fixes the glitch. Thanks, Anshuman Gupta. > > -- > Ville Syrjälä > Intel ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit @ 2020-12-08 9:11 ` Anshuman Gupta 0 siblings, 0 replies; 17+ messages in thread From: Anshuman Gupta @ 2020-12-08 9:11 UTC (permalink / raw) To: Ville Syrjälä, imre.deak; +Cc: intel-gfx, stable On 2020-12-04 at 17:51:34 +0200, Ville Syrjälä wrote: > On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote: > > On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote: > > > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote: > > > > At usual case DC3CO exit happen automatically by DMC f/w whenever > > > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips. > > > > But there are certain scenario where DC3CO Disallowed by driver > > > > asynchronous with flips. In such scenario display engine could > > > > be already in DC3CO state and driver has disallowed it, > > > > It initiates DC3CO exit sequence in DMC f/w which requires a > > > > dc3co exit delay of 200us in driver. > > > > It requires to protect intel_pipe_update_{update_end} with > > > > dc3co exit delay. > > > > > > > > Cc: Imre Deak <imre.deak@intel.com> > > > > Cc: <stable@vger.kernel.org> > > > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > > > > > To make sure that it doesn't hide the root cause (or affects unrelated > > > platforms), I'd only add locking around DC3co changes with a new lock, > > > using lock/unlock helpers in intel_display_power.c called from > > > intel_pipe_update_start/end. > > > > > > Also please submit this patch separately, w/o the optimization in patch > > > 1/2, so we know that this change fixes the problem. > > This patch doesn't seems to fix the issue. > > Looks like there is some other set of display register updates before > > completing the dc3co exit delay beyond intel_pipe_update_start/end causing this issue. > > Not really sure I understand the DC3CO issue here, nor how grabbing a > mutex across the update could help. > > But anyways, maybe we should just: > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 2e2dd746921f..96276f0feddc 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > drm_atomic_helper_wait_for_dependencies(&state->base); > > - if (state->modeset) > - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); > + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); > > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { > @@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > * the culprit. > */ > intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); > - intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > } > + intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); > intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); > > /* > > To get the DMC out of equation entirely for all plane updates? Hi Ville / Imre , Above suggested chnages is not helping to fix the display glitches. Could you please provide your inputs to debug the possible root cause considering the patch https://patchwork.freedesktop.org/patch/405585/?series=84394&rev=2 fixes the glitch. Thanks, Anshuman Gupta. > > -- > Ville Syrjälä > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes 2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] " Anshuman Gupta @ 2020-11-30 15:50 ` Patchwork 2 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2020-11-30 15:50 UTC (permalink / raw) To: Anshuman Gupta; +Cc: intel-gfx == Series Details == Series: Display glitches fixes URL : https://patchwork.freedesktop.org/series/84394/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/display/intel_display.o drivers/gpu/drm/i915/display/intel_display.c: In function ‘intel_update_crtc’: drivers/gpu/drm/i915/display/intel_display.c:15940:16: error: ‘dev_prive’ undeclared (first use in this function); did you mean ‘dev_priv’? mutex_unlock(&dev_prive->power_domains.lock); ^~~~~~~~~ dev_priv drivers/gpu/drm/i915/display/intel_display.c:15940:16: note: each undeclared identifier is reported only once for each function it appears in scripts/Makefile.build:283: recipe for target 'drivers/gpu/drm/i915/display/intel_display.o' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_display.o] Error 1 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:500: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1799: recipe for target 'drivers' failed make: *** [drivers] Error 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2020-12-08 9:25 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-11-30 9:16 [Intel-gfx] [RFC 0/2] Display glitches fixes Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] [RFC 1/2] drm/i915/dp: optimize pps_lock wherever required Anshuman Gupta 2020-11-30 9:16 ` [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit Anshuman Gupta 2020-11-30 9:16 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:28 ` Imre Deak 2020-11-30 15:28 ` [Intel-gfx] " Imre Deak 2020-11-30 16:16 ` Anshuman Gupta 2020-11-30 16:16 ` [Intel-gfx] " Anshuman Gupta 2020-12-04 8:10 ` Anshuman Gupta 2020-12-04 8:10 ` [Intel-gfx] " Anshuman Gupta 2020-12-04 15:51 ` Ville Syrjälä 2020-12-04 15:51 ` [Intel-gfx] " Ville Syrjälä 2020-12-07 7:57 ` Anshuman Gupta 2020-12-07 7:57 ` [Intel-gfx] " Anshuman Gupta 2020-12-08 9:11 ` Anshuman Gupta 2020-12-08 9:11 ` [Intel-gfx] " Anshuman Gupta 2020-11-30 15:50 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Display glitches fixes Patchwork
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