[PATCH v1 0/2] Add drivers for Intel Keem Bay SoC timer block

[PATCH v1 0/2] Add drivers for Intel Keem Bay SoC timer block

[vijayakannan.ayyathurai]

From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

Hi.

This patch set adds the driver for Intel Keem Bay SoC timer block,
which contains 32-bit general purpose timers, a 64 bit free running counter
and a random number generator.

Patch 1 holds the Device Tree binding documentation and
Patch 2 holds the Device Driver.

This driver was tested on the Keem Bay evaluation module board.

Thanks,
Vijay

Vijayakannan Ayyathurai (2):
  dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer
  clocksource: Add Intel Keem Bay Timer Support

 .../bindings/timer/intel,keembay-timer.yaml   |  72 ++++++
 drivers/clocksource/Kconfig                   |  10 +
 drivers/clocksource/Makefile                  |   1 +
 drivers/clocksource/timer-keembay.c           | 221 ++++++++++++++++++
 4 files changed, 304 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
 create mode 100644 drivers/clocksource/timer-keembay.c


base-commit: 418baf2c28f3473039f2f7377760bd8f6897ae18
prerequisite-patch-id: 822987dcf4c969ef6ac70359b088af06ba39042b
prerequisite-patch-id: 0a348762b660d0d817b8e70cc71647e83173c78c
prerequisite-patch-id: 54c661a006c7362053cb7602448d6c77419d5cf9
prerequisite-patch-id: d140d8534fb828778e0652fe5fcf6282e027f985
-- 
2.17.1

[PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer

[vijayakannan.ayyathurai]

From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

Add Device Tree bindings for the Timer IP, which used as clocksource and
clockevent in the Intel Keem Bay SoC.

Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Acked-by: Mark Gross <mgross@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 .../bindings/timer/intel,keembay-timer.yaml   | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
new file mode 100644
index 000000000000..396a698967ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay SoC Timers
+
+maintainers:
+  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+description:
+  Intel Keem Bay SoC Timers block contains 8 32-bit general purpose timers,
+  a free running 64-bit counter, a random number generator and a watchdog
+  timer. Each gpt can generate an individual interrupt.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          enum:
+            - intel,keembay-timer
+            - intel,keembay-counter
+
+  reg:
+    maxItems: 2
+
+  clocks:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - intel,keembay-timer
+    then:
+      properties:
+        interrupts:
+          maxItems: 1
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #define KEEM_BAY_A53_TIM
+
+    timer@20330010 {
+        compatible = "intel,keembay-timer";
+        reg = <0x20330010 0xc>,
+              <0x20331000 0xc>;
+        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+    };
+
+    counter@203300e8 {
+        compatible = "intel,keembay-counter";
+        reg = <0x203300e8 0xc>,
+              <0x20331000 0xc>;
+        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+    };
-- 
2.17.1

[PATCH v1 2/2] clocksource: Add Intel Keem Bay Timer Support

[vijayakannan.ayyathurai]

From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

Add generic clocksource and clockevent driver for the timer IP
used in Intel Keem Bay SoC.

One free running Counter used as a clocksource device and one Timer
used as a clockevent device. Both are enabled through TIM_GEN_CONFIG
register. This register is in the DT resource index 1.

Timer/Counter base register is in the DT resource index 0
and it's map/unmap handled by TIMER OF api.

Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
Acked-by: Mark Gross <mgross@linux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clocksource/Kconfig         |  10 ++
 drivers/clocksource/Makefile        |   1 +
 drivers/clocksource/timer-keembay.c | 221 ++++++++++++++++++++++++++++
 3 files changed, 232 insertions(+)
 create mode 100644 drivers/clocksource/timer-keembay.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 68b087bff59c..b1f29e12c571 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -738,4 +738,14 @@ config MICROCHIP_PIT64B
 	  modes and high resolution. It is used as a clocksource
 	  and a clockevent.
 
+config KEEMBAY_TIMER
+	bool "Intel Keem Bay timer driver"
+	depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
+	select TIMER_OF
+	help
+	  This option enables the support for the Intel Keem Bay general
+	  purpose timer and free running counter driver. Each timer can
+	  generate an individual interrupt and the 64 bit counter can also
+	  be used as one of the clock source.
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 1c444cc3bb44..f6cfc362b406 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -94,3 +94,4 @@ obj-$(CONFIG_CSKY_MP_TIMER)		+= timer-mp-csky.o
 obj-$(CONFIG_GX6605S_TIMER)		+= timer-gx6605s.o
 obj-$(CONFIG_HYPERV_TIMER)		+= hyperv_timer.o
 obj-$(CONFIG_MICROCHIP_PIT64B)		+= timer-microchip-pit64b.o
+obj-$(CONFIG_KEEMBAY_TIMER)		+= timer-keembay.o
diff --git a/drivers/clocksource/timer-keembay.c b/drivers/clocksource/timer-keembay.c
new file mode 100644
index 000000000000..41b9bbb3382d
--- /dev/null
+++ b/drivers/clocksource/timer-keembay.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay Timer driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include <linux/bits.h>
+#include <linux/interrupt.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/sizes.h>
+
+#include "timer-of.h"
+
+/* Registers offset */
+#define TIM_CNT_VAL_OFFSET		0
+#define TIM_RELOAD_VAL_OFFSET		SZ_4
+#define TIM_CONFIG_OFFSET		SZ_8
+
+/* Bit fields of TIM_GEN_CONFIG register */
+#define TIM_CONFIG_PRESCALER_ENABLE	BIT(2)
+
+/* Bit fields of TIM_CONFIG registers */
+#define TIM_CONFIG_INTERRUPT_PENDING	BIT(4)
+#define TIM_CONFIG_INTERRUPT_ENABLE	BIT(2)
+#define TIM_CONFIG_RESTART		BIT(1)
+#define TIM_CONFIG_ENABLE		BIT(0)
+
+#define TIM_RATING			200
+#define TIM_CLKSRC_BITS			SZ_64
+
+struct keembay_init_data {
+	struct timer_of	*cfg;
+	void __iomem	*base;
+	u32		mask;
+};
+
+static inline void keembay_timer_disable(void __iomem *base)
+{
+	writel(0, base + TIM_CONFIG_OFFSET);
+}
+
+static inline void keembay_timer_enable(void __iomem *base, u32 flags)
+{
+	writel(TIM_CONFIG_ENABLE | flags, base + TIM_CONFIG_OFFSET);
+}
+
+static inline void keembay_timer_update_counter(void __iomem *base, u32 val)
+{
+	writel(val, base + TIM_CNT_VAL_OFFSET);
+	writel(val, base + TIM_RELOAD_VAL_OFFSET);
+}
+
+static int keembay_timer_set_next_event(unsigned long evt,
+					struct clock_event_device *ce)
+{
+	u32 flags = TIM_CONFIG_INTERRUPT_ENABLE;
+	struct timer_of *to = to_timer_of(ce);
+
+	/* setup and enable oneshot timer */
+	keembay_timer_disable(timer_of_base(to));
+	keembay_timer_update_counter(timer_of_base(to), evt);
+	keembay_timer_enable(timer_of_base(to), flags);
+
+	return 0;
+}
+
+static int keembay_timer_periodic(struct clock_event_device *ce)
+{
+	u32 flags = TIM_CONFIG_INTERRUPT_ENABLE | TIM_CONFIG_RESTART;
+	struct timer_of *to = to_timer_of(ce);
+
+	/* setup and enable periodic timer */
+	keembay_timer_disable(timer_of_base(to));
+	keembay_timer_update_counter(timer_of_base(to), timer_of_period(to));
+	keembay_timer_enable(timer_of_base(to), flags);
+
+	return 0;
+}
+
+static int keembay_timer_shutdown(struct clock_event_device *ce)
+{
+	struct timer_of *to = to_timer_of(ce);
+
+	keembay_timer_disable(timer_of_base(to));
+
+	return 0;
+}
+
+static irqreturn_t keembay_timer_isr(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+	struct timer_of *to = to_timer_of(evt);
+	u32 val;
+
+	val = readl(timer_of_base(to) + TIM_CONFIG_OFFSET);
+	val &= ~TIM_CONFIG_INTERRUPT_PENDING;
+	writel(val, timer_of_base(to) + TIM_CONFIG_OFFSET);
+
+	if (clockevent_state_oneshot(evt))
+		keembay_timer_disable(timer_of_base(to));
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static int __init keembay_init_pre(struct device_node *np,
+				   struct keembay_init_data *data)
+{
+	struct timer_of *to = data->cfg;
+	u32 val;
+	int ret;
+
+	data->base = of_iomap(np, 1);
+	if (!data->base)
+		return -ENXIO;
+
+	val = readl(data->base + TIM_CONFIG_OFFSET);
+	if (!(val & data->mask)) {
+		iounmap(data->base);
+		return -ENODEV;
+	}
+
+	ret = timer_of_init(np, to);
+	if (ret)
+		iounmap(data->base);
+
+	return ret;
+}
+
+static void keembay_init_post(struct device_node *np,
+			      struct keembay_init_data *data)
+{
+	iounmap(data->base);
+}
+
+static struct timer_of keembay_ce_to = {
+	.flags	= TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+	.clkevt = {
+		.name			= "keembay_timer",
+		.features		= CLOCK_EVT_FEAT_PERIODIC |
+					  CLOCK_EVT_FEAT_ONESHOT,
+		.rating			= TIM_RATING,
+		.set_next_event		= keembay_timer_set_next_event,
+		.set_state_periodic	= keembay_timer_periodic,
+		.set_state_shutdown	= keembay_timer_shutdown,
+	},
+	.of_irq = {
+		.handler = keembay_timer_isr,
+		.flags = IRQF_TIMER | IRQF_IRQPOLL,
+	},
+};
+
+static int __init keembay_timer_init(struct device_node *np)
+{
+	struct keembay_init_data data;
+	u32 val;
+	int ret;
+
+	data.mask = TIM_CONFIG_PRESCALER_ENABLE;
+	data.cfg = &keembay_ce_to;
+	ret = keembay_init_pre(np, &data);
+	if (ret)
+		return ret;
+
+	val = readl(data.base + TIM_RELOAD_VAL_OFFSET);
+
+	keembay_ce_to.clkevt.cpumask = cpumask_of(0);
+	keembay_ce_to.of_clk.rate = keembay_ce_to.of_clk.rate / (val + 1);
+
+	keembay_timer_disable(timer_of_base(&keembay_ce_to));
+
+	keembay_init_post(np, &data);
+
+	clockevents_config_and_register(&keembay_ce_to.clkevt,
+					timer_of_rate(&keembay_ce_to), 1,
+					U32_MAX);
+	return 0;
+}
+
+static struct timer_of keembay_cs_to = {
+	.flags	= TIMER_OF_BASE | TIMER_OF_CLOCK,
+};
+
+static u64 notrace keembay_clocksource_read(struct clocksource *cs)
+{
+	return lo_hi_readq(timer_of_base(&keembay_cs_to));
+}
+
+static struct clocksource keembay_counter = {
+	.name			= "keembay_sys_counter",
+	.rating			= TIM_RATING,
+	.read			= keembay_clocksource_read,
+	.mask			= CLOCKSOURCE_MASK(TIM_CLKSRC_BITS),
+	.flags			= CLOCK_SOURCE_IS_CONTINUOUS |
+				  CLOCK_SOURCE_SUSPEND_NONSTOP,
+};
+
+static int __init keembay_counter_init(struct device_node *np)
+{
+	struct keembay_init_data data;
+	int ret;
+
+	data.mask = TIM_CONFIG_ENABLE;
+	data.cfg = &keembay_cs_to;
+	ret = keembay_init_pre(np, &data);
+	if (ret)
+		return ret;
+
+	keembay_init_post(np, &data);
+
+	return clocksource_register_hz(&keembay_counter,
+				       timer_of_rate(&keembay_cs_to));
+}
+
+TIMER_OF_DECLARE(keembay_timer, "intel,keembay-timer", keembay_timer_init);
+TIMER_OF_DECLARE(keembay_sys_counter, "intel,keembay-counter",
+		 keembay_counter_init);
-- 
2.17.1

Re: [PATCH v1 2/2] clocksource: Add Intel Keem Bay Timer Support

[Daniel Lezcano]

On 26/11/2020 11:34, vijayakannan.ayyathurai@intel.com wrote:
> From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> 
> Add generic clocksource and clockevent driver for the timer IP
> used in Intel Keem Bay SoC.
> 
> One free running Counter used as a clocksource device and one Timer
> used as a clockevent device. Both are enabled through TIM_GEN_CONFIG
> register. This register is in the DT resource index 1.
> 
> Timer/Counter base register is in the DT resource index 0
> and it's map/unmap handled by TIMER OF api.
> 
> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> Acked-by: Mark Gross <mgross@linux.intel.com>
> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/clocksource/Kconfig         |  10 ++
>  drivers/clocksource/Makefile        |   1 +
>  drivers/clocksource/timer-keembay.c | 221 ++++++++++++++++++++++++++++
>  3 files changed, 232 insertions(+)
>  create mode 100644 drivers/clocksource/timer-keembay.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 68b087bff59c..b1f29e12c571 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -738,4 +738,14 @@ config MICROCHIP_PIT64B
>  	  modes and high resolution. It is used as a clocksource
>  	  and a clockevent.
>  
> +config KEEMBAY_TIMER
> +	bool "Intel Keem Bay timer driver"
> +	depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)

The timer drivers subsystem wants silent options and let the platform to
select the timer.

Please select the timer in arch/arm64/Kconfig.platforms in the
ARCH_KEEMBAY section.

So it would come:

config KEEMBAY_TIMER
	bool "bla bla" if COMPILE_TEST



> +	select TIMER_OF
> +	help
> +	  This option enables the support for the Intel Keem Bay general
> +	  purpose timer and free running counter driver. Each timer can
> +	  generate an individual interrupt and the 64 bit counter can also
> +	  be used as one of the clock source.
> +

[ ... ]

> +static struct timer_of keembay_ce_to = {
> +	.flags	= TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
> +	.clkevt = {
> +		.name			= "keembay_timer",
> +		.features		= CLOCK_EVT_FEAT_PERIODIC |
> +					  CLOCK_EVT_FEAT_ONESHOT,

May be consider CLOCK_EVT_FEAT_DYNIRQ ?

see commit d2348fb6fdc6d67

Other than that, LGTM

Thanks

  -- Daniel

-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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Re: [PATCH v1 2/2] clocksource: Add Intel Keem Bay Timer Support

[Daniel Lezcano]

On 26/11/2020 11:34, vijayakannan.ayyathurai@intel.com wrote:
> From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> 
> Add generic clocksource and clockevent driver for the timer IP
> used in Intel Keem Bay SoC.
> 
> One free running Counter used as a clocksource device and one Timer
> used as a clockevent device. Both are enabled through TIM_GEN_CONFIG
> register. This register is in the DT resource index 1.
> 
> Timer/Counter base register is in the DT resource index 0
> and it's map/unmap handled by TIMER OF api.
> 
> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> Acked-by: Mark Gross <mgross@linux.intel.com>
> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/clocksource/Kconfig         |  10 ++
>  drivers/clocksource/Makefile        |   1 +
>  drivers/clocksource/timer-keembay.c | 221 ++++++++++++++++++++++++++++
>  3 files changed, 232 insertions(+)
>  create mode 100644 drivers/clocksource/timer-keembay.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 68b087bff59c..b1f29e12c571 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -738,4 +738,14 @@ config MICROCHIP_PIT64B
>  	  modes and high resolution. It is used as a clocksource
>  	  and a clockevent.
>  
> +config KEEMBAY_TIMER
> +	bool "Intel Keem Bay timer driver"
> +	depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)

The timer drivers subsystem wants silent options and let the platform to
select the timer.

Please select the timer in arch/arm64/Kconfig.platforms in the
ARCH_KEEMBAY section.

So it would come:

config KEEMBAY_TIMER
	bool "bla bla" if COMPILE_TEST



> +	select TIMER_OF
> +	help
> +	  This option enables the support for the Intel Keem Bay general
> +	  purpose timer and free running counter driver. Each timer can
> +	  generate an individual interrupt and the 64 bit counter can also
> +	  be used as one of the clock source.
> +

[ ... ]

> +static struct timer_of keembay_ce_to = {
> +	.flags	= TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
> +	.clkevt = {
> +		.name			= "keembay_timer",
> +		.features		= CLOCK_EVT_FEAT_PERIODIC |
> +					  CLOCK_EVT_FEAT_ONESHOT,

May be consider CLOCK_EVT_FEAT_DYNIRQ ?

see commit d2348fb6fdc6d67

Other than that, LGTM

Thanks

  -- Daniel

-- 
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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RE: [PATCH v1 2/2] clocksource: Add Intel Keem Bay Timer Support

[Ayyathurai, Vijayakannan]

Hi Daniel,
Thanks for reviewing this patch.

> From: Daniel Lezcano <daniel.lezcano@linaro.org>
> >
> > +++ b/drivers/clocksource/Kconfig
> > @@ -738,4 +738,14 @@ config MICROCHIP_PIT64B
> >  	  modes and high resolution. It is used as a clocksource
> >  	  and a clockevent.
> >
> > +config KEEMBAY_TIMER
> > +	bool "Intel Keem Bay timer driver"
> > +	depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
> 
> The timer drivers subsystem wants silent options and let the platform to
> select the timer.
> 
> Please select the timer in arch/arm64/Kconfig.platforms in the
> ARCH_KEEMBAY section.
> 
> So it would come:
> 
> config KEEMBAY_TIMER
> 	bool "bla bla" if COMPILE_TEST
> 

Ok. I will check that and update in next version.

> 
> 
> > +	select TIMER_OF
> > +	help
> > +	  This option enables the support for the Intel Keem Bay general
> > +	  purpose timer and free running counter driver. Each timer can
> > +	  generate an individual interrupt and the 64 bit counter can also
> > +	  be used as one of the clock source.
> > +
> 
> [ ... ]
> 
> > +static struct timer_of keembay_ce_to = {
> > +	.flags	= TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
> > +	.clkevt = {
> > +		.name			= "keembay_timer",
> > +		.features		= CLOCK_EVT_FEAT_PERIODIC |
> > +					  CLOCK_EVT_FEAT_ONESHOT,
> 
> May be consider CLOCK_EVT_FEAT_DYNIRQ ?
> 
> see commit d2348fb6fdc6d67
> 

Sure. I will add it in the next version.

> Other than that, LGTM
> 
> Thanks
> 
>   -- Daniel
> 

Thanks,
Vijay

Re: [PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer

[Rob Herring]

On Thu, Nov 26, 2020 at 06:34:08PM +0800, vijayakannan.ayyathurai@intel.com wrote:
> From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> 
> Add Device Tree bindings for the Timer IP, which used as clocksource and
> clockevent in the Intel Keem Bay SoC.
> 
> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> Acked-by: Mark Gross <mgross@linux.intel.com>
> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  .../bindings/timer/intel,keembay-timer.yaml   | 72 +++++++++++++++++++
>  1 file changed, 72 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> 
> diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> new file mode 100644
> index 000000000000..396a698967ca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Keem Bay SoC Timers
> +
> +maintainers:
> +  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> +
> +description:
> +  Intel Keem Bay SoC Timers block contains 8 32-bit general purpose timers,
> +  a free running 64-bit counter, a random number generator and a watchdog
> +  timer. Each gpt can generate an individual interrupt.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          enum:
> +            - intel,keembay-timer
> +            - intel,keembay-counter
> +
> +  reg:
> +    maxItems: 2
> +
> +  clocks:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - intel,keembay-timer
> +    then:
> +      properties:
> +        interrupts:
> +          maxItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #define KEEM_BAY_A53_TIM
> +
> +    timer@20330010 {
> +        compatible = "intel,keembay-timer";
> +        reg = <0x20330010 0xc>,
> +              <0x20331000 0xc>;
> +        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> +    };
> +
> +    counter@203300e8 {
> +        compatible = "intel,keembay-counter";
> +        reg = <0x203300e8 0xc>,
> +              <0x20331000 0xc>;

You have overlapping reg regions here. Don't do that. Define the DT 
in terms of the h/w, not how you want to split things for Linux.

It looks like a single h/w block providing multiple functions.

> +        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> +    };
> -- 
> 2.17.1
> 

Re: [PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer

[Andy Shevchenko]

On Tue, Dec 08, 2020 at 10:12:47AM -0600, Rob Herring wrote:
> On Thu, Nov 26, 2020 at 06:34:08PM +0800, vijayakannan.ayyathurai@intel.com wrote:
> > From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> > 
> > Add Device Tree bindings for the Timer IP, which used as clocksource and
> > clockevent in the Intel Keem Bay SoC.

...

> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #define KEEM_BAY_A53_TIM
> > +
> > +    timer@20330010 {
> > +        compatible = "intel,keembay-timer";
> > +        reg = <0x20330010 0xc>,
> > +              <0x20331000 0xc>;
> > +        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > +    };
> > +
> > +    counter@203300e8 {
> > +        compatible = "intel,keembay-counter";
> > +        reg = <0x203300e8 0xc>,
> > +              <0x20331000 0xc>;
> 
> You have overlapping reg regions here. Don't do that. Define the DT 
> in terms of the h/w, not how you want to split things for Linux.
> 
> It looks like a single h/w block providing multiple functions.

Actually a good catch.

Perhaps it needs to have a parent device that provides three resources (one
common and one per each of two functions) and in the driver it should consume
them accordingly. Though I'm not an expert in DT, does it sound correct from
your perspective?

> > +        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > +    };

-- 
With Best Regards,
Andy Shevchenko

RE: [PATCH v1 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer

[Ayyathurai, Vijayakannan]

Hi Rob,

> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> On Tue, Dec 08, 2020 at 10:12:47AM -0600, Rob Herring wrote:
> > > From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
> > >
> > > Add Device Tree bindings for the Timer IP, which used as clocksource and
> > > clockevent in the Intel Keem Bay SoC.
> 
> ...
> 
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +    #include <dt-bindings/interrupt-controller/irq.h>
> > > +    #define KEEM_BAY_A53_TIM
> > > +
> > > +    timer@20330010 {
> > > +        compatible = "intel,keembay-timer";
> > > +        reg = <0x20330010 0xc>,
> > > +              <0x20331000 0xc>;
> > > +        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > > +        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > > +    };
> > > +
> > > +    counter@203300e8 {
> > > +        compatible = "intel,keembay-counter";
> > > +        reg = <0x203300e8 0xc>,
> > > +              <0x20331000 0xc>;
> >
> > You have overlapping reg regions here. Don't do that. Define the DT
> > in terms of the h/w, not how you want to split things for Linux.
> >
> > It looks like a single h/w block providing multiple functions.
> 
> Actually a good catch.
> 
> Perhaps it needs to have a parent device that provides three resources (one
> common and one per each of two functions) and in the driver it should
> consume
> them accordingly. Though I'm not an expert in DT, does it sound correct from
> your perspective?
> 

May I know your feedback for the below way, which Andy suggested.
I will adapt the driver based on this in the next version.

timer@20331000 {
    compatible = "intel,keembay-timer";
    reg = <20331000 0xc>;
    
    gpt@20330010 {
        compatible = "intel,keembay-gpt";
        reg = <20330010 0xc>;
        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
    };

    counter@203300e8 {
        compatible = "intel,keembay-counter";
        reg = <203300e8 0xc>;
        clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
    };
};

Thanks,
Vijay