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From: Matt Roper <matthew.d.roper@intel.com>
To: Aditya Swarup <aditya.swarup@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>,
	intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls
Date: Mon, 11 Jan 2021 20:05:20 -0800	[thread overview]
Message-ID: <20210112040520.GE21197@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20201205010844.361880-13-aditya.swarup@intel.com>

On Fri, Dec 04, 2020 at 05:08:34PM -0800, Aditya Swarup wrote:
> - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E.
> - Add ADLS specific port mappings for vbt port dvo settings.
> - Select appropriate AUX CH specific to ADLS based on port mapping.

The aux stuff is getting really messy; we're definitely going to have to
move to a table-based approach for some of this stuff soon to keep it
from getting too out of hand.

The changes here look correct for the current style though.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++-----
>  1 file changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 9dc67c03ffc0..8f166f49b6cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
>  		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
>  		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
>  	};
> +	/*
> +	 * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
> +	 * PORT_F and PORT_G, we need to map that to correct VBT sections.
> +	 */
> +	static const int adls_port_mapping[][3] = {
> +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> +		[PORT_B] = { -1 },
> +		[PORT_C] = { -1 },
> +		[PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> +		[PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> +		[PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> +		[PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
> +	};
>  
> -	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +	if (IS_ALDERLAKE_S(dev_priv))
> +		return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
> +					  ARRAY_SIZE(adls_port_mapping[0]),
> +					  adls_port_mapping,
> +					  dvo_port);
> +	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>  		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
>  					  ARRAY_SIZE(rkl_port_mapping[0]),
>  					  rkl_port_mapping,
> @@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
>  		return aux_ch;
>  	}
>  
> +	/*
> +	 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
> +	 * map to DDI A,B,TC1,TC2 respectively.
> +	 *
> +	 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
> +	 * map to DDI A,TC1,TC2,TC3,TC4 respectively.
> +	 */
>  	switch (info->alternate_aux_channel) {
>  	case DP_AUX_A:
>  		aux_ch = AUX_CH_A;
>  		break;
>  	case DP_AUX_B:
> -		aux_ch = AUX_CH_B;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC1;
> +		else
> +			aux_ch = AUX_CH_B;
>  		break;
>  	case DP_AUX_C:
> -		/*
> -		 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
> -		 * map to DDI A,B,TC1,TC2 respectively.
> -		 */
> -		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
> -			AUX_CH_USBC1 : AUX_CH_C;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC2;
> +		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +			aux_ch = AUX_CH_USBC1;
> +		else
> +			aux_ch = AUX_CH_C;
>  		break;
>  	case DP_AUX_D:
> -		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
> -			AUX_CH_USBC2 : AUX_CH_D;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC3;
> +		else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> +			aux_ch = AUX_CH_USBC2;
> +		else
> +			aux_ch = AUX_CH_D;
>  		break;
>  	case DP_AUX_E:
> -		aux_ch = AUX_CH_E;
> +		if (IS_ALDERLAKE_S(dev_priv))
> +			aux_ch = AUX_CH_USBC4;
> +		else
> +			aux_ch = AUX_CH_E;
>  		break;
>  	case DP_AUX_F:
>  		aux_ch = AUX_CH_F;
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-01-12  4:05 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-05  1:08 [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 01/22] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 02/22] drm/i915/tgl: Add bound checks and simplify TGL REVID macros Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2021-01-05 21:04   ` Souza, Jose
2020-12-05  1:08 ` [Intel-gfx] [PATCH 04/22] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 05/22] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 06/22] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2021-01-12  3:33   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2021-01-12  3:47   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2021-01-12 23:47   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display " Aditya Swarup
2021-01-12  3:54   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2021-01-12  4:19   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2021-01-12  4:05   ` Matt Roper [this message]
2020-12-05  1:08 ` [Intel-gfx] [PATCH 13/22] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 14/22] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 15/22] drm/i915/adl_s: Add display WAs for ADL-S Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 16/22] drm/i915/adl_s: Add GT and CTX " Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2021-01-27 14:29   ` Lucas De Marchi
2020-12-05  1:08 ` [Intel-gfx] [PATCH 18/22] drm/i915/adl_s: Add power wells Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 19/22] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 20/22] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 21/22] drm/i915/adl_s: Load DMC Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 22/22] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-12-05  1:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev3) Patchwork
2020-12-05  1:22 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-12-05  1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-05  5:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-21 10:40 ` [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S Jani Nikula

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