Re: [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved

From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Aditya Swarup <aditya.swarup@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved
Date: Wed, 27 Jan 2021 06:29:29 -0800	[thread overview]
Message-ID: <20210127142929.7uq5kewj5umvhfnu@ldmartin-desk1> (raw)
In-Reply-To: <20201205010844.361880-18-aditya.swarup@intel.com>

On Fri, Dec 04, 2020 at 05:08:39PM -0800, Aditya Swarup wrote:
>From: Caz Yokoyama <caz.yokoyama@intel.com>
>
>The crwebview indicates on ADL-S that some of our MCHBAR
>registers have moved from their traditional 0x50XX offsets to
>new locations. The meaning and bit layout of the registers
>remain same.
>
>v2: Simplify logic to a single if else chain and fix indents.(Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Jani Nikula <jani.nikula@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Cc: Imre Deak <imre.deak@intel.com>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h   |  5 +++++
> drivers/gpu/drm/i915/intel_dram.c | 23 +++++++++++++++++------
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index ce4ef7fa4000..55e186293fbb 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10865,6 +10865,8 @@ enum skl_power_gate {
> #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
> #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
>
>+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
>+
> #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
> #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
> #define  SKL_DRAM_S_SHIFT			16
>@@ -10892,6 +10894,9 @@ enum skl_power_gate {
> #define  CNL_DRAM_RANK_3			(0x2 << 9)
> #define  CNL_DRAM_RANK_4			(0x3 << 9)
>
>+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6054)
>+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6058)
>+
> /*
>  * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>  * since on HSW we can't write to it using intel_uncore_write.
>diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>index 4754296a250e..fc9942139ccc 100644
>--- a/drivers/gpu/drm/i915/intel_dram.c
>+++ b/drivers/gpu/drm/i915/intel_dram.c
>@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
> {
> 	struct dram_info *dram_info = &i915->dram_info;
> 	struct dram_channel_info ch0 = {}, ch1 = {};
>+	i915_reg_t ch0_reg, ch1_reg;
> 	u32 val;
> 	int ret;
>
>-	val = intel_uncore_read(&i915->uncore,
>-				SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
>+	if (IS_ALDERLAKE_S(i915)) {
>+		ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
>+		ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
>+	} else {
>+		ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
>+		ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;

this is not right and breaks all the other platforms.

Also this patch conflicts with
https://patchwork.freedesktop.org/series/86092/
and general direction that we should get these values from pcode rather
than keep changing the offset we use to avoid MCHBAR.

Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx