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From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 20/22] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
Date: Fri,  4 Dec 2020 17:08:42 -0800	[thread overview]
Message-ID: <20201205010844.361880-21-aditya.swarup@intel.com> (raw)
In-Reply-To: <20201205010844.361880-1-aditya.swarup@intel.com>

From: José Roberto de Souza <jose.souza@intel.com>

- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
  the cursor plane, let's group the handling together under
  HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.

BSpec: 49251
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h             | 3 +++
 drivers/gpu/drm/i915/i915_irq.c             | 2 +-
 drivers/gpu/drm/i915/intel_device_info.c    | 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2d820ff2b236..10176b174e50 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -366,7 +366,7 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 
 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 {
-	if (IS_ROCKETLAKE(i915))
+	if (HAS_D12_PLANE_MINIMIZATION(i915))
 		return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 	else
 		return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91bd262dd871..1d710d9d8dee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1796,6 +1796,9 @@ extern const struct i915_rev_steppings adls_revids[];
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
 
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+					      IS_ALDERLAKE_S(dev_priv))
+
 static inline bool intel_vtd_active(void)
 {
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d1b4893d6c92..bcb0f7c96c65 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-	if (IS_ROCKETLAKE(dev_priv))
+	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
 	else if (INTEL_GEN(dev_priv) >= 11)
 		return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index da651ef10014..c94a52642f32 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 4;
 	else if (INTEL_GEN(dev_priv) >= 11)
-- 
2.27.0

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  parent reply	other threads:[~2020-12-05  1:09 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-05  1:08 [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 01/22] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 02/22] drm/i915/tgl: Add bound checks and simplify TGL REVID macros Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2021-01-05 21:04   ` Souza, Jose
2020-12-05  1:08 ` [Intel-gfx] [PATCH 04/22] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 05/22] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 06/22] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2021-01-12  3:33   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2021-01-12  3:47   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2021-01-12 23:47   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display " Aditya Swarup
2021-01-12  3:54   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2021-01-12  4:19   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2021-01-12  4:05   ` Matt Roper
2020-12-05  1:08 ` [Intel-gfx] [PATCH 13/22] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 14/22] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 15/22] drm/i915/adl_s: Add display WAs for ADL-S Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 16/22] drm/i915/adl_s: Add GT and CTX " Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2021-01-27 14:29   ` Lucas De Marchi
2020-12-05  1:08 ` [Intel-gfx] [PATCH 18/22] drm/i915/adl_s: Add power wells Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 19/22] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-12-05  1:08 ` Aditya Swarup [this message]
2020-12-05  1:08 ` [Intel-gfx] [PATCH 21/22] drm/i915/adl_s: Load DMC Aditya Swarup
2020-12-05  1:08 ` [Intel-gfx] [PATCH 22/22] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-12-05  1:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev3) Patchwork
2020-12-05  1:22 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-12-05  1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-05  5:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-21 10:40 ` [Intel-gfx] [PATCH 00/22] Introduce Alderlake-S Jani Nikula

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