* [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
@ 2021-01-12 21:54 ` Philippe Mathieu-Daudé
2021-01-13 2:04 ` Jiaxun Yang
2021-01-21 19:50 ` Richard Henderson
2021-01-12 21:55 ` [PATCH 2/6] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
` (6 subsequent siblings)
7 siblings, 2 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:54 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
There is no issue having multiple enum declarations with
the same value. As we are going to remove the OPC_MULT_G_2E
definition in few commits, restore the OPC_ADDUH_QB_DSP and
OPC_MUL_PH_DSP definitions and use them where they belong.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a2b3026132d..cbd152eff50 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -399,16 +399,14 @@ enum {
OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
- /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
- /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
+ OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3,
OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
/* MIPS DSP GPR-Based Shift Sub-class */
OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
/* MIPS DSP Multiply Sub-class insns */
- /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
- /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
+ OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3,
OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
/* DSP Bit/Manipulation Sub-class */
@@ -566,7 +564,6 @@ enum {
OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
};
-#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
#define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum {
/* MIPS DSP Arithmetic Sub-class */
@@ -22681,8 +22678,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_load_gpr(v2_t, v2);
switch (op1) {
- /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
- case OPC_MULT_G_2E:
+ case OPC_ADDUH_QB_DSP:
check_dsp_r2(ctx);
switch (op2) {
case OPC_ADDUH_QB:
@@ -23376,11 +23372,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_load_gpr(v2_t, v2);
switch (op1) {
- /*
- * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
- * the same mask and op1.
- */
- case OPC_MULT_G_2E:
+ case OPC_MUL_PH_DSP:
check_dsp_r2(ctx);
switch (op2) {
case OPC_MUL_PH:
@@ -27337,7 +27329,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1.
*/
- if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
+ if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) {
op2 = MASK_ADDUH_QB(ctx->opcode);
switch (op2) {
case OPC_ADDUH_QB:
--
2.26.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
2021-01-12 21:54 ` [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
@ 2021-01-13 2:04 ` Jiaxun Yang
2021-01-21 19:50 ` Richard Henderson
1 sibling, 0 replies; 25+ messages in thread
From: Jiaxun Yang @ 2021-01-13 2:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
> There is no issue having multiple enum declarations with
> the same value. As we are going to remove the OPC_MULT_G_2E
> definition in few commits, restore the OPC_ADDUH_QB_DSP and
> OPC_MUL_PH_DSP definitions and use them where they belong.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> target/mips/translate.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index a2b3026132d..cbd152eff50 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -399,16 +399,14 @@ enum {
> OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
> OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
> OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
> - /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
> - /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
> + OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3,
> OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
> OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
> /* MIPS DSP GPR-Based Shift Sub-class */
> OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
> OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
> /* MIPS DSP Multiply Sub-class insns */
> - /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
> - /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
> + OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3,
> OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
> OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
> /* DSP Bit/Manipulation Sub-class */
> @@ -566,7 +564,6 @@ enum {
> OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
> };
>
> -#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
> #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
> enum {
> /* MIPS DSP Arithmetic Sub-class */
> @@ -22681,8 +22678,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
> gen_load_gpr(v2_t, v2);
>
> switch (op1) {
> - /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
> - case OPC_MULT_G_2E:
> + case OPC_ADDUH_QB_DSP:
> check_dsp_r2(ctx);
> switch (op2) {
> case OPC_ADDUH_QB:
> @@ -23376,11 +23372,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
> gen_load_gpr(v2_t, v2);
>
> switch (op1) {
> - /*
> - * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
> - * the same mask and op1.
> - */
> - case OPC_MULT_G_2E:
> + case OPC_MUL_PH_DSP:
> check_dsp_r2(ctx);
> switch (op2) {
> case OPC_MUL_PH:
> @@ -27337,7 +27329,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
> * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
> * the same mask and op1.
> */
> - if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
> + if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) {
> op2 = MASK_ADDUH_QB(ctx->opcode);
> switch (op2) {
> case OPC_ADDUH_QB:
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
2021-01-12 21:54 ` [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
2021-01-13 2:04 ` Jiaxun Yang
@ 2021-01-21 19:50 ` Richard Henderson
1 sibling, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 19:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
> There is no issue having multiple enum declarations with
> the same value. As we are going to remove the OPC_MULT_G_2E
> definition in few commits, restore the OPC_ADDUH_QB_DSP and
> OPC_MUL_PH_DSP definitions and use them where they belong.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 2/6] target/mips: Convert Loongson DDIV.G opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
2021-01-12 21:54 ` [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
@ 2021-01-12 21:55 ` Philippe Mathieu-Daudé
2021-01-21 19:54 ` Richard Henderson
2021-01-12 21:55 ` [PATCH 3/6] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
` (5 subsequent siblings)
7 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:55 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Introduce decode_loongson() to decode all Loongson vendor
specific opcodes. Start converting a single opcode: DDIV.G
(divide 64-bit signed integers).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/godson2.decode | 16 +++++++
target/mips/loong-ext.decode | 17 +++++++
target/mips/loong_translate.c | 89 +++++++++++++++++++++++++++++++++++
target/mips/translate.c | 28 ++---------
target/mips/meson.build | 3 ++
6 files changed, 131 insertions(+), 23 deletions(-)
create mode 100644 target/mips/godson2.decode
create mode 100644 target/mips/loong-ext.decode
create mode 100644 target/mips/loong_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 11730f5b2e6..b67c45012b8 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -164,5 +164,6 @@ void msa_translate_init(void);
/* decodetree generated */
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
+bool decode_loongson(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
new file mode 100644
index 00000000000..cbe22285740
--- /dev/null
+++ b/target/mips/godson2.decode
@@ -0,0 +1,16 @@
+# Godson2 Integer instructions
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# Godson-2E Software Manual
+# (Document Number: godson2e-user-manual-V0.6)
+#
+
+&muldiv rs rt rd
+
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+
+DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
new file mode 100644
index 00000000000..557fe06c14a
--- /dev/null
+++ b/target/mips/loong-ext.decode
@@ -0,0 +1,17 @@
+# Loongson Extension instructions
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# STLS2F01 User Manual
+# Appendix A: new integer instructions
+# (Document Number: UM0447)
+#
+
+&muldiv rs rt rd !extern
+
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+
+DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
new file mode 100644
index 00000000000..c452472e7a7
--- /dev/null
+++ b/target/mips/loong_translate.c
@@ -0,0 +1,89 @@
+/*
+ * MIPS Loongson translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2011 Richard Henderson <rth@twiddle.net>
+ * Copyright (c) 2021 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-godson2.c.inc"
+#include "decode-loong-ext.c.inc"
+
+/*
+ * Word or double-word Fixed-point instructions.
+ * --------------------------------------------
+ *
+ * Fixed-point multiplies and divisions write only one result
+ * into general-purpose registers.
+ */
+
+static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2, *l3;
+
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_local_new();
+ t1 = tcg_temp_local_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ l3 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l3);
+ gen_set_label(l1);
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
+ tcg_gen_mov_tl(cpu_gpr[rd], t0);
+
+ tcg_gen_br(l3);
+ gen_set_label(l2);
+ tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
+ gen_set_label(l3);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIV_G(s, a->rt, a->rs, a->rd);
+}
+
+bool decode_loongson(DisasContext *ctx, uint32_t insn)
+{
+ if ((ctx->insn_flags & INSN_LOONGSON2E)
+ && decode_godson2(ctx, ctx->opcode)) {
+ return true;
+ }
+ if ((ctx->insn_flags & ASE_LEXT) && decode_loong_ext(ctx, ctx->opcode)) {
+ return true;
+ }
+ return false;
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cbd152eff50..c427ea98952 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -343,7 +343,6 @@ enum {
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
- OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
@@ -385,7 +384,6 @@ enum {
OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
@@ -5108,25 +5106,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DDIV_G_2E:
- case OPC_DDIV_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
- tcg_gen_mov_tl(cpu_gpr[rd], t0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l3);
- }
- break;
case OPC_DDIVU_G_2E:
case OPC_DDIVU_G_2F:
{
@@ -27180,7 +27159,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DDIV_G_2F:
case OPC_DDIVU_G_2F:
case OPC_DMOD_G_2F:
case OPC_DMODU_G_2F:
@@ -27590,7 +27568,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DDIV_G_2E:
case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
@@ -28976,6 +28953,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* Transition to the auto-generated decoder. */
+ /* Vendor specific extensions */
+ if (decode_loongson(ctx, ctx->opcode)) {
+ return;
+ }
+
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
return;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 9741545440c..0b6067f96c3 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,6 @@
gen = [
+ decodetree.process('godson2.decode', extra_args: ['--static-decode=decode_godson2']),
+ decodetree.process('loong-ext.decode', extra_args: ['--static-decode=decode_loong_ext']),
decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
@@ -15,6 +17,7 @@
'dsp_helper.c',
'fpu_helper.c',
'lmmi_helper.c',
+ 'loong_translate.c',
'msa_helper.c',
'msa_translate.c',
'op_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 2/6] target/mips: Convert Loongson DDIV.G opcodes to decodetree
2021-01-12 21:55 ` [PATCH 2/6] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
@ 2021-01-21 19:54 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 19:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Introduce decode_loongson() to decode all Loongson vendor
> specific opcodes. Start converting a single opcode: DDIV.G
> (divide 64-bit signed integers).
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 1 +
> target/mips/godson2.decode | 16 +++++++
> target/mips/loong-ext.decode | 17 +++++++
> target/mips/loong_translate.c | 89 +++++++++++++++++++++++++++++++++++
> target/mips/translate.c | 28 ++---------
> target/mips/meson.build | 3 ++
> 6 files changed, 131 insertions(+), 23 deletions(-)
> create mode 100644 target/mips/godson2.decode
> create mode 100644 target/mips/loong-ext.decode
> create mode 100644 target/mips/loong_translate.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 3/6] target/mips: Convert Loongson DIV.G opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
2021-01-12 21:54 ` [PATCH 1/6] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
2021-01-12 21:55 ` [PATCH 2/6] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
@ 2021-01-12 21:55 ` Philippe Mathieu-Daudé
2021-01-12 21:59 ` Philippe Mathieu-Daudé
2021-01-21 19:56 ` Richard Henderson
2021-01-12 21:55 ` [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
` (4 subsequent siblings)
7 siblings, 2 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:55 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
'is_double' argument so it can generate DIV.G (divide 32-bit
signed integers).
With this commit we explicit the template used to generate
opcode for 32/64-bit word variants. Next commits will be less
verbose by providing both variants at once.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/godson2.decode | 1 +
target/mips/loong-ext.decode | 1 +
target/mips/loong_translate.c | 28 ++++++++++++++++++++++------
target/mips/translate.c | 26 --------------------------
4 files changed, 24 insertions(+), 32 deletions(-)
diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
index cbe22285740..b56a93a1999 100644
--- a/target/mips/godson2.decode
+++ b/target/mips/godson2.decode
@@ -13,4 +13,5 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
index 557fe06c14a..331c2226ae3 100644
--- a/target/mips/loong-ext.decode
+++ b/target/mips/loong-ext.decode
@@ -14,4 +14,5 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
index c452472e7a7..634d4ba8031 100644
--- a/target/mips/loong_translate.c
+++ b/target/mips/loong_translate.c
@@ -27,15 +27,18 @@
* into general-purpose registers.
*/
-static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
+static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
{
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
- if (TARGET_LONG_BITS != 64) {
- return false;
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
}
- check_mips_64(s);
if (rd == 0) {
/* Treat as NOP. */
@@ -51,18 +54,26 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ext32s_tl(t1, t1);
+ }
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? -1LL << 63 : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
gen_set_label(l3);
tcg_temp_free(t0);
@@ -71,9 +82,14 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
return true;
}
+static bool trans_DIV_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, false);
+}
+
static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
{
- return gen_lext_DIV_G(s, a->rt, a->rs, a->rd);
+ return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
}
bool decode_loongson(DisasContext *ctx, uint32_t insn)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c427ea98952..7cefff44d74 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -342,7 +342,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
@@ -380,7 +379,6 @@ enum {
/* Loongson 2E */
OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
- OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
@@ -5023,28 +5021,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_DIV_G_2E:
- case OPC_DIV_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_ext32s_tl(t0, t0);
- tcg_gen_ext32s_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
- tcg_gen_mov_tl(cpu_gpr[rd], t0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l3);
- }
- break;
case OPC_DIVU_G_2E:
case OPC_DIVU_G_2F:
{
@@ -27124,7 +27100,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
- case OPC_DIV_G_2F:
case OPC_DIVU_G_2F:
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
@@ -27297,7 +27272,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_DIV_G_2E:
case OPC_DIVU_G_2E:
case OPC_MOD_G_2E:
case OPC_MODU_G_2E:
--
2.26.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 3/6] target/mips: Convert Loongson DIV.G opcodes to decodetree
2021-01-12 21:55 ` [PATCH 3/6] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
@ 2021-01-12 21:59 ` Philippe Mathieu-Daudé
2021-01-21 19:56 ` Richard Henderson
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:59 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On Tue, Jan 12, 2021 at 10:55 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
> 'is_double' argument so it can generate DIV.G (divide 32-bit
> signed integers).
>
> With this commit we explicit the template used to generate
> opcode for 32/64-bit word variants. Next commits will be less
> verbose by providing both variants at once.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/godson2.decode | 1 +
> target/mips/loong-ext.decode | 1 +
> target/mips/loong_translate.c | 28 ++++++++++++++++++++++------
> target/mips/translate.c | 26 --------------------------
> 4 files changed, 24 insertions(+), 32 deletions(-)
...
> @@ -51,18 +54,26 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
> gen_load_gpr(t0, rs);
> gen_load_gpr(t1, rt);
>
> + if (!is_double) {
> + tcg_gen_ext32s_tl(t0, t0);
> + tcg_gen_ext32s_tl(t0, t0);
Oops copy/paste problem...
> + tcg_gen_ext32s_tl(t1, t1);
> + }
> tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
> tcg_gen_movi_tl(cpu_gpr[rd], 0);
> tcg_gen_br(l3);
> gen_set_label(l1);
...
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 3/6] target/mips: Convert Loongson DIV.G opcodes to decodetree
2021-01-12 21:55 ` [PATCH 3/6] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
2021-01-12 21:59 ` Philippe Mathieu-Daudé
@ 2021-01-21 19:56 ` Richard Henderson
1 sibling, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 19:56 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
> 'is_double' argument so it can generate DIV.G (divide 32-bit
> signed integers).
>
> With this commit we explicit the template used to generate
> opcode for 32/64-bit word variants. Next commits will be less
> verbose by providing both variants at once.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/godson2.decode | 1 +
> target/mips/loong-ext.decode | 1 +
> target/mips/loong_translate.c | 28 ++++++++++++++++++++++------
> target/mips/translate.c | 26 --------------------------
> 4 files changed, 24 insertions(+), 32 deletions(-)
With the double-extend pasto fixed,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-01-12 21:55 ` [PATCH 3/6] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
@ 2021-01-12 21:55 ` Philippe Mathieu-Daudé
2021-01-21 19:58 ` Richard Henderson
2021-01-12 21:55 ` [PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
` (3 subsequent siblings)
7 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:55 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
(divide 64-bit unsigned integers) opcodes to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/godson2.decode | 2 ++
target/mips/loong-ext.decode | 2 ++
target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
target/mips/translate.c | 37 -----------------------
4 files changed, 59 insertions(+), 37 deletions(-)
diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
index b56a93a1999..0d5a72064d2 100644
--- a/target/mips/godson2.decode
+++ b/target/mips/godson2.decode
@@ -14,4 +14,6 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
+DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
+DDIVU.G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
index 331c2226ae3..2e98262b81d 100644
--- a/target/mips/loong-ext.decode
+++ b/target/mips/loong-ext.decode
@@ -16,3 +16,5 @@
DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
+DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
+DDIVU.G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
index 634d4ba8031..7b3304ec749 100644
--- a/target/mips/loong_translate.c
+++ b/target/mips/loong_translate.c
@@ -92,6 +92,61 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_local_new();
+ t1 = tcg_temp_local_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ gen_set_label(l2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_DIVU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true);
+}
+
bool decode_loongson(DisasContext *ctx, uint32_t insn)
{
if ((ctx->insn_flags & INSN_LOONGSON2E)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7cefff44d74..69463e3b42d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -342,8 +342,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
- OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
@@ -379,10 +377,8 @@ enum {
/* Loongson 2E */
OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
- OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
@@ -5021,22 +5017,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_DIVU_G_2E:
- case OPC_DIVU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l2);
- }
- break;
case OPC_MOD_G_2E:
case OPC_MOD_G_2F:
{
@@ -5082,19 +5062,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DDIVU_G_2E:
- case OPC_DDIVU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l2);
- }
- break;
case OPC_DMOD_G_2E:
case OPC_DMOD_G_2F:
{
@@ -27100,7 +27067,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
- case OPC_DIVU_G_2F:
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
case OPC_MOD_G_2F:
@@ -27134,7 +27100,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DDIVU_G_2F:
case OPC_DMOD_G_2F:
case OPC_DMODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
@@ -27272,7 +27237,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_DIVU_G_2E:
case OPC_MOD_G_2E:
case OPC_MODU_G_2E:
case OPC_MULT_G_2E:
@@ -27542,7 +27506,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E:
--
2.26.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
2021-01-12 21:55 ` [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
@ 2021-01-21 19:58 ` Richard Henderson
2021-08-10 5:51 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 19:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
> (divide 64-bit unsigned integers) opcodes to decodetree.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/godson2.decode | 2 ++
> target/mips/loong-ext.decode | 2 ++
> target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
> target/mips/translate.c | 37 -----------------------
> 4 files changed, 59 insertions(+), 37 deletions(-)
>
> diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
> index b56a93a1999..0d5a72064d2 100644
> --- a/target/mips/godson2.decode
> +++ b/target/mips/godson2.decode
> @@ -14,4 +14,6 @@
> @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
>
> DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
> +DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
> DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
> +DDIVU.G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
> diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
> index 331c2226ae3..2e98262b81d 100644
> --- a/target/mips/loong-ext.decode
> +++ b/target/mips/loong-ext.decode
> @@ -16,3 +16,5 @@
>
> DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
> DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
> +DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
> +DDIVU.G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
> diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
> index 634d4ba8031..7b3304ec749 100644
> --- a/target/mips/loong_translate.c
> +++ b/target/mips/loong_translate.c
> @@ -92,6 +92,61 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
> return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
> }
>
> +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
> + bool is_double)
> +{
> + TCGv t0, t1;
> + TCGLabel *l1, *l2;
> +
> + if (is_double) {
> + if (TARGET_LONG_BITS != 64) {
> + return false;
> + }
> + check_mips_64(s);
> + }
> +
> + if (rd == 0) {
> + /* Treat as NOP. */
> + return true;
> + }
> +
> + t0 = tcg_temp_local_new();
> + t1 = tcg_temp_local_new();
> + l1 = gen_new_label();
> + l2 = gen_new_label();
> +
> + gen_load_gpr(t0, rs);
> + gen_load_gpr(t1, rt);
> +
> + if (!is_double) {
> + tcg_gen_ext32u_tl(t0, t0);
> + tcg_gen_ext32u_tl(t1, t1);
> + }
> + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
> + tcg_gen_movi_tl(cpu_gpr[rd], 0);
> +
> + tcg_gen_br(l2);
> + gen_set_label(l1);
> + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
> + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
this extend should be conditional on !is_double.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
2021-01-21 19:58 ` Richard Henderson
@ 2021-08-10 5:51 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-10 5:51 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/21/21 8:58 PM, Richard Henderson wrote:
> On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
>> Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
>> (divide 64-bit unsigned integers) opcodes to decodetree.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> target/mips/godson2.decode | 2 ++
>> target/mips/loong-ext.decode | 2 ++
>> target/mips/loong_translate.c | 55 +++++++++++++++++++++++++++++++++++
>> target/mips/translate.c | 37 -----------------------
>> 4 files changed, 59 insertions(+), 37 deletions(-)
>> +static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
>> + bool is_double)
>> +{
>> + TCGv t0, t1;
>> + TCGLabel *l1, *l2;
>> +
>> + if (is_double) {
>> + if (TARGET_LONG_BITS != 64) {
>> + return false;
>> + }
>> + check_mips_64(s);
>> + }
>> +
>> + if (rd == 0) {
>> + /* Treat as NOP. */
>> + return true;
>> + }
>> +
>> + t0 = tcg_temp_local_new();
>> + t1 = tcg_temp_local_new();
>> + l1 = gen_new_label();
>> + l2 = gen_new_label();
>> +
>> + gen_load_gpr(t0, rs);
>> + gen_load_gpr(t1, rt);
>> +
>> + if (!is_double) {
>> + tcg_gen_ext32u_tl(t0, t0);
>> + tcg_gen_ext32u_tl(t1, t1);
>> + }
>> + tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
>> + tcg_gen_movi_tl(cpu_gpr[rd], 0);
>> +
>> + tcg_gen_br(l2);
>> + gen_set_label(l1);
>> + tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
>> + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
>
> this extend should be conditional on !is_double.
Oops, thanks!
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-01-12 21:55 ` [PATCH 4/6] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
@ 2021-01-12 21:55 ` Philippe Mathieu-Daudé
2021-01-21 20:00 ` Richard Henderson
2021-01-12 21:55 ` [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
` (2 subsequent siblings)
7 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:55 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the following opcodes to decodetree:
- MOD.G - mod 32-bit signed integers
- MODU.G - mod 32-bit unsigned integers
- DMOD.G - mod 64-bit signed integers
- DMODU.G - mod 64-bit unsigned integers
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/godson2.decode | 5 ++
target/mips/loong-ext.decode | 5 ++
target/mips/loong_translate.c | 116 ++++++++++++++++++++++++++++++++++
target/mips/translate.c | 86 -------------------------
4 files changed, 126 insertions(+), 86 deletions(-)
diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
index 0d5a72064d2..805452fa975 100644
--- a/target/mips/godson2.decode
+++ b/target/mips/godson2.decode
@@ -17,3 +17,8 @@ DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
DDIVU.G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
+
+MOD.G 011111 ..... ..... ..... 00000 100010 @rs_rt_rd
+MODU.G 011111 ..... ..... ..... 00000 100011 @rs_rt_rd
+DMOD.G 011111 ..... ..... ..... 00000 100110 @rs_rt_rd
+DMODU.G 011111 ..... ..... ..... 00000 100111 @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
index 2e98262b81d..b0715894ee1 100644
--- a/target/mips/loong-ext.decode
+++ b/target/mips/loong-ext.decode
@@ -18,3 +18,8 @@ DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
DDIVU.G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
+
+MOD.G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd
+DMOD.G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd
+MODU.G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd
+DMODU.G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
index 7b3304ec749..50609ce4178 100644
--- a/target/mips/loong_translate.c
+++ b/target/mips/loong_translate.c
@@ -147,6 +147,122 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2, *l3;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_local_new();
+ t1 = tcg_temp_local_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ l3 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? -1LL << 63 : INT_MIN, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
+ gen_set_label(l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l3);
+ gen_set_label(l2);
+ tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l3);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_MOD_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, true);
+}
+
+static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_local_new();
+ t1 = tcg_temp_local_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l2);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_MODU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
+}
+
bool decode_loongson(DisasContext *ctx, uint32_t insn)
{
if ((ctx->insn_flags & INSN_LOONGSON2E)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 69463e3b42d..144e51b063a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -342,10 +342,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
- OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
- OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
- OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2,
@@ -379,10 +375,6 @@ enum {
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
- OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
- OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
- OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
/* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
@@ -4995,10 +4987,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
t0 = tcg_temp_new();
t1 = tcg_temp_new();
break;
- default:
- t0 = tcg_temp_local_new();
- t1 = tcg_temp_local_new();
- break;
}
gen_load_gpr(t0, rs);
@@ -5017,42 +5005,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_MOD_G_2E:
- case OPC_MOD_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l3);
- }
- break;
- case OPC_MODU_G_2E:
- case OPC_MODU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l2);
- }
- break;
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULT_G_2F:
@@ -5062,36 +5014,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DMOD_G_2E:
- case OPC_DMOD_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l3);
- }
- break;
- case OPC_DMODU_G_2E:
- case OPC_DMODU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l2);
- }
- break;
#endif
}
@@ -27069,8 +26991,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
- case OPC_MOD_G_2F:
- case OPC_MODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -27100,8 +27020,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DMOD_G_2F:
- case OPC_DMODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -27237,8 +27155,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_MOD_G_2E:
- case OPC_MODU_G_2E:
case OPC_MULT_G_2E:
case OPC_MULTU_G_2E:
/*
@@ -27508,8 +27424,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
- case OPC_DMOD_G_2E:
- case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
--
2.26.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
2021-01-12 21:55 ` [PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
@ 2021-01-21 20:00 ` Richard Henderson
0 siblings, 0 replies; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 20:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert the following opcodes to decodetree:
>
> - MOD.G - mod 32-bit signed integers
> - MODU.G - mod 32-bit unsigned integers
> - DMOD.G - mod 64-bit signed integers
> - DMODU.G - mod 64-bit unsigned integers
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/godson2.decode | 5 ++
> target/mips/loong-ext.decode | 5 ++
> target/mips/loong_translate.c | 116 ++++++++++++++++++++++++++++++++++
> target/mips/translate.c | 86 -------------------------
> 4 files changed, 126 insertions(+), 86 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-01-12 21:55 ` [PATCH 5/6] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
@ 2021-01-12 21:55 ` Philippe Mathieu-Daudé
2021-01-21 20:06 ` Richard Henderson
2021-01-13 2:15 ` [PATCH 0/6] target/mips: Convert Loongson LEXT " Jiaxun Yang
2021-01-21 20:07 ` Richard Henderson
7 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-12 21:55 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno
Convert the following opcodes to decodetree:
- MULT.G - multiply 32-bit signed integers
- MULTU.G - multiply 32-bit unsigned integers
- DMULT.G - multiply 64-bit signed integers
- DMULTU.G - multiply 64-bit unsigned integers
Now that all opcodes from the extension have been converted, we
can remove completely gen_loongson_integer() and its 2 calls in
decode_opc_special2_legacy() and decode_opc_special3_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/godson2.decode | 5 ++
target/mips/loong-ext.decode | 5 ++
target/mips/loong_translate.c | 58 ++++++++++++++++++++++
target/mips/translate.c | 92 +----------------------------------
4 files changed, 70 insertions(+), 90 deletions(-)
diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
index 805452fa975..cf12d9072ec 100644
--- a/target/mips/godson2.decode
+++ b/target/mips/godson2.decode
@@ -13,6 +13,11 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+MULT.G 011111 ..... ..... ..... 00000 011000 @rs_rt_rd
+MULTU.G 011111 ..... ..... ..... 00000 011001 @rs_rt_rd
+DMULT.G 011111 ..... ..... ..... 00000 011100 @rs_rt_rd
+DMULTU.G 011111 ..... ..... ..... 00000 011101 @rs_rt_rd
+
DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
index b0715894ee1..2281afaad95 100644
--- a/target/mips/loong-ext.decode
+++ b/target/mips/loong-ext.decode
@@ -14,6 +14,11 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+MULT.G 011100 ..... ..... ..... 00000 010000 @rs_rt_rd
+DMULT.G 011100 ..... ..... ..... 00000 010001 @rs_rt_rd
+MULTU.G 011100 ..... ..... ..... 00000 010010 @rs_rt_rd
+DMULTU.G 011100 ..... ..... ..... 00000 010011 @rs_rt_rd
+
DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
index 50609ce4178..2af94535921 100644
--- a/target/mips/loong_translate.c
+++ b/target/mips/loong_translate.c
@@ -263,6 +263,64 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double, bool is_unsigned)
+{
+ TCGv t0, t1;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (is_unsigned && !is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_MULT_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, false);
+}
+
+static bool trans_MULTU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, true);
+}
+
+static bool trans_DMULT_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, false);
+}
+
+static bool trans_DMULTU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, true);
+}
+
bool decode_loongson(DisasContext *ctx, uint32_t insn)
{
if ((ctx->insn_flags & INSN_LOONGSON2E)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 144e51b063a..5b5fe31c534 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -337,11 +337,6 @@ enum {
OPC_MUL = 0x02 | OPC_SPECIAL2,
OPC_MSUB = 0x04 | OPC_SPECIAL2,
OPC_MSUBU = 0x05 | OPC_SPECIAL2,
- /* Loongson 2F */
- OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
- OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
- OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
- OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2,
@@ -370,12 +365,6 @@ enum {
OPC_RDHWR = 0x3B | OPC_SPECIAL3,
OPC_GINV = 0x3D | OPC_SPECIAL3,
- /* Loongson 2E */
- OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
- OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
- OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
- OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
-
/* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
/* MIPS DSP Arithmetic */
@@ -4962,65 +4951,6 @@ static void gen_cl(DisasContext *ctx, uint32_t opc,
}
}
-/* Godson integer instructions */
-static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
- int rd, int rs, int rt)
-{
- TCGv t0, t1;
-
- if (rd == 0) {
- /* Treat as NOP. */
- return;
- }
-
- switch (opc) {
- case OPC_MULT_G_2E:
- case OPC_MULT_G_2F:
- case OPC_MULTU_G_2E:
- case OPC_MULTU_G_2F:
-#if defined(TARGET_MIPS64)
- case OPC_DMULT_G_2E:
- case OPC_DMULT_G_2F:
- case OPC_DMULTU_G_2E:
- case OPC_DMULTU_G_2F:
-#endif
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- break;
- }
-
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
-
- switch (opc) {
- case OPC_MULT_G_2E:
- case OPC_MULT_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- break;
- case OPC_MULTU_G_2E:
- case OPC_MULTU_G_2F:
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- break;
-#if defined(TARGET_MIPS64)
- case OPC_DMULT_G_2E:
- case OPC_DMULT_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- break;
- case OPC_DMULTU_G_2E:
- case OPC_DMULTU_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- break;
-#endif
- }
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
-}
-
/* Loongson multimedia instructions */
static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
{
@@ -26989,11 +26919,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
- case OPC_MULT_G_2F:
- case OPC_MULTU_G_2F:
- check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
case OPC_CLO:
case OPC_CLZ:
check_insn(ctx, ISA_MIPS_R1);
@@ -27018,11 +26943,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
- case OPC_DMULT_G_2F:
- case OPC_DMULTU_G_2F:
- check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
#endif
default: /* Invalid */
MIPS_INVAL("special2_legacy");
@@ -27155,10 +27075,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_MULT_G_2E:
- case OPC_MULTU_G_2E:
+ case OPC_MUL_PH_DSP:
/*
- * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
+ * OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1.
*/
if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) {
@@ -27189,8 +27108,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_reserved_instruction(ctx);
break;
}
- } else if (ctx->insn_flags & INSN_LOONGSON2E) {
- gen_loongson_integer(ctx, op1, rd, rs, rt);
} else {
gen_reserved_instruction(ctx);
}
@@ -27422,11 +27339,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DMULT_G_2E:
- case OPC_DMULTU_G_2E:
- check_insn(ctx, INSN_LOONGSON2E);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
case OPC_ABSQ_S_QH_DSP:
op2 = MASK_ABSQ_S_QH(ctx->opcode);
switch (op2) {
--
2.26.2
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
2021-01-12 21:55 ` [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
@ 2021-01-21 20:06 ` Richard Henderson
2023-08-31 19:12 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 20:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
> Convert the following opcodes to decodetree:
>
> - MULT.G - multiply 32-bit signed integers
> - MULTU.G - multiply 32-bit unsigned integers
> - DMULT.G - multiply 64-bit signed integers
> - DMULTU.G - multiply 64-bit unsigned integers
>
> Now that all opcodes from the extension have been converted, we
> can remove completely gen_loongson_integer() and its 2 calls in
> decode_opc_special2_legacy() and decode_opc_special3_legacy().
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/godson2.decode | 5 ++
> target/mips/loong-ext.decode | 5 ++
> target/mips/loong_translate.c | 58 ++++++++++++++++++++++
> target/mips/translate.c | 92 +----------------------------------
> 4 files changed, 70 insertions(+), 90 deletions(-)
>
> diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
> index 805452fa975..cf12d9072ec 100644
> --- a/target/mips/godson2.decode
> +++ b/target/mips/godson2.decode
> @@ -13,6 +13,11 @@
>
> @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
>
> +MULT.G 011111 ..... ..... ..... 00000 011000 @rs_rt_rd
> +MULTU.G 011111 ..... ..... ..... 00000 011001 @rs_rt_rd
> +DMULT.G 011111 ..... ..... ..... 00000 011100 @rs_rt_rd
> +DMULTU.G 011111 ..... ..... ..... 00000 011101 @rs_rt_rd
> +
> DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
> DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
> DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
> diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
> index b0715894ee1..2281afaad95 100644
> --- a/target/mips/loong-ext.decode
> +++ b/target/mips/loong-ext.decode
> @@ -14,6 +14,11 @@
>
> @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
>
> +MULT.G 011100 ..... ..... ..... 00000 010000 @rs_rt_rd
> +DMULT.G 011100 ..... ..... ..... 00000 010001 @rs_rt_rd
> +MULTU.G 011100 ..... ..... ..... 00000 010010 @rs_rt_rd
> +DMULTU.G 011100 ..... ..... ..... 00000 010011 @rs_rt_rd
> +
> DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
> DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
> DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
> diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
> index 50609ce4178..2af94535921 100644
> --- a/target/mips/loong_translate.c
> +++ b/target/mips/loong_translate.c
> @@ -263,6 +263,64 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
> return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
> }
>
> +static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
> + bool is_double, bool is_unsigned)
> +{
> + TCGv t0, t1;
> +
> + if (is_double) {
> + if (TARGET_LONG_BITS != 64) {
> + return false;
> + }
> + check_mips_64(s);
> + }
> +
> + if (rd == 0) {
> + /* Treat as NOP. */
> + return true;
> + }
> +
> + t0 = tcg_temp_new();
> + t1 = tcg_temp_new();
> +
> + gen_load_gpr(t0, rs);
> + gen_load_gpr(t1, rt);
> +
> + if (is_unsigned && !is_double) {
> + tcg_gen_ext32u_tl(t0, t0);
> + tcg_gen_ext32u_tl(t1, t1);
> + }
While this is a faithful conversion of the existing code, these extensions make
no difference to the result. They are redundant with
> + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
> + if (!is_double) {
> + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
this one, which discards any bit that might have been set by the input bits
that are cleared.
There is no actual difference between MULT.G and MULTU.G, or DMULT.G and
DMULTU.G, because they don't record the most significant bits of the infinite
result in any way.
> +static bool trans_MULT_G(DisasContext *s, arg_muldiv *a)
> +{
> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, false);
> +}
> +
> +static bool trans_MULTU_G(DisasContext *s, arg_muldiv *a)
> +{
> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, true);
> +}
> +
> +static bool trans_DMULT_G(DisasContext *s, arg_muldiv *a)
> +{
> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, false);
> +}
> +
> +static bool trans_DMULTU_G(DisasContext *s, arg_muldiv *a)
> +{
> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, true);
> +}
So... if you want to clean this up afterward, or before is up to you.
r~
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
2021-01-21 20:06 ` Richard Henderson
@ 2023-08-31 19:12 ` Philippe Mathieu-Daudé
2023-08-31 20:31 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-31 19:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aurelien Jarno, Huacai Chen, Jiaxun Yang
On 21/1/21 21:06, Richard Henderson wrote:
> On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
>> Convert the following opcodes to decodetree:
>>
>> - MULT.G - multiply 32-bit signed integers
>> - MULTU.G - multiply 32-bit unsigned integers
>> - DMULT.G - multiply 64-bit signed integers
>> - DMULTU.G - multiply 64-bit unsigned integers
>>
>> Now that all opcodes from the extension have been converted, we
>> can remove completely gen_loongson_integer() and its 2 calls in
>> decode_opc_special2_legacy() and decode_opc_special3_legacy().
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> target/mips/godson2.decode | 5 ++
>> target/mips/loong-ext.decode | 5 ++
>> target/mips/loong_translate.c | 58 ++++++++++++++++++++++
>> target/mips/translate.c | 92 +----------------------------------
>> 4 files changed, 70 insertions(+), 90 deletions(-)
>>
>> diff --git a/target/mips/godson2.decode b/target/mips/godson2.decode
>> index 805452fa975..cf12d9072ec 100644
>> --- a/target/mips/godson2.decode
>> +++ b/target/mips/godson2.decode
>> @@ -13,6 +13,11 @@
>>
>> @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
>>
>> +MULT.G 011111 ..... ..... ..... 00000 011000 @rs_rt_rd
>> +MULTU.G 011111 ..... ..... ..... 00000 011001 @rs_rt_rd
>> +DMULT.G 011111 ..... ..... ..... 00000 011100 @rs_rt_rd
>> +DMULTU.G 011111 ..... ..... ..... 00000 011101 @rs_rt_rd
>> +
>> DIV.G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
>> DIVU.G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
>> DDIV.G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
>> diff --git a/target/mips/loong-ext.decode b/target/mips/loong-ext.decode
>> index b0715894ee1..2281afaad95 100644
>> --- a/target/mips/loong-ext.decode
>> +++ b/target/mips/loong-ext.decode
>> @@ -14,6 +14,11 @@
>>
>> @rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
>>
>> +MULT.G 011100 ..... ..... ..... 00000 010000 @rs_rt_rd
>> +DMULT.G 011100 ..... ..... ..... 00000 010001 @rs_rt_rd
>> +MULTU.G 011100 ..... ..... ..... 00000 010010 @rs_rt_rd
>> +DMULTU.G 011100 ..... ..... ..... 00000 010011 @rs_rt_rd
>> +
>> DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
>> DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
>> DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
>> diff --git a/target/mips/loong_translate.c b/target/mips/loong_translate.c
>> index 50609ce4178..2af94535921 100644
>> --- a/target/mips/loong_translate.c
>> +++ b/target/mips/loong_translate.c
>> @@ -263,6 +263,64 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
>> return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
>> }
>>
>> +static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
>> + bool is_double, bool is_unsigned)
>> +{
>> + TCGv t0, t1;
>> +
>> + if (is_double) {
>> + if (TARGET_LONG_BITS != 64) {
>> + return false;
>> + }
>> + check_mips_64(s);
>> + }
>> +
>> + if (rd == 0) {
>> + /* Treat as NOP. */
>> + return true;
>> + }
>> +
>> + t0 = tcg_temp_new();
>> + t1 = tcg_temp_new();
>> +
>> + gen_load_gpr(t0, rs);
>> + gen_load_gpr(t1, rt);
>> +
>> + if (is_unsigned && !is_double) {
>> + tcg_gen_ext32u_tl(t0, t0);
>> + tcg_gen_ext32u_tl(t1, t1);
>> + }
>
> While this is a faithful conversion of the existing code, these extensions make
> no difference to the result. They are redundant with
>
>> + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
>> + if (!is_double) {
>> + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
>
> this one, which discards any bit that might have been set by the input bits
> that are cleared.
I see.
> There is no actual difference between MULT.G and MULTU.G, or DMULT.G and
> DMULTU.G, because they don't record the most significant bits of the infinite
> result in any way.
Right.
>> +static bool trans_MULT_G(DisasContext *s, arg_muldiv *a)
>> +{
>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, false);
>> +}
>> +
>> +static bool trans_MULTU_G(DisasContext *s, arg_muldiv *a)
>> +{
>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, true);
>> +}
>> +
>> +static bool trans_DMULT_G(DisasContext *s, arg_muldiv *a)
>> +{
>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, false);
>> +}
>> +
>> +static bool trans_DMULTU_G(DisasContext *s, arg_muldiv *a)
>> +{
>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, true);
>> +}
>
> So... if you want to clean this up afterward, or before is up to you.
IIUC you are suggesting this simplification:
-- >8 --
diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode
index 4fb8fdba9c..86015ac8e5 100644
--- a/target/mips/tcg/godson2.decode
+++ b/target/mips/tcg/godson2.decode
@@ -15,6 +15,4 @@
-MULT_G 011111 ..... ..... ..... 00000 011000 @rs_rt_rd
-MULTU_G 011111 ..... ..... ..... 00000 011001 @rs_rt_rd
-DMULT_G 011111 ..... ..... ..... 00000 011100 @rs_rt_rd
-DMULTU_G 011111 ..... ..... ..... 00000 011101 @rs_rt_rd
+MULTu_G 011111 ..... ..... ..... 00000 01100- @rs_rt_rd
+DMULTu_G 011111 ..... ..... ..... 00000 01110- @rs_rt_rd
diff --git a/target/mips/tcg/loong-ext.decode
b/target/mips/tcg/loong-ext.decode
index d2c46d3110..b05236eb41 100644
--- a/target/mips/tcg/loong-ext.decode
+++ b/target/mips/tcg/loong-ext.decode
@@ -16,6 +16,4 @@
-MULT_G 011100 ..... ..... ..... 00000 010000 @rs_rt_rd
-DMULT_G 011100 ..... ..... ..... 00000 010001 @rs_rt_rd
-MULTU_G 011100 ..... ..... ..... 00000 010010 @rs_rt_rd
-DMULTU_G 011100 ..... ..... ..... 00000 010011 @rs_rt_rd
+MULTu_G 011100 ..... ..... ..... 00000 0100-0 @rs_rt_rd
+DMULTu_G 011100 ..... ..... ..... 00000 0100-1 @rs_rt_rd
diff --git a/target/mips/tcg/loong_translate.c
b/target/mips/tcg/loong_translate.c
index 672d8b6163..4b6bdf28be 100644
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -253,3 +253,3 @@ static bool trans_DMODU_G(DisasContext *s,
arg_muldiv *a)
static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
- bool is_double, bool is_unsigned)
+ bool is_double)
{
@@ -275,6 +275,2 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd,
int rs, int rt,
- if (is_unsigned && !is_double) {
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- }
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
@@ -287,20 +283,10 @@ static bool gen_lext_MULT_G(DisasContext *s, int
rd, int rs, int rt,
-static bool trans_MULT_G(DisasContext *s, arg_muldiv *a)
+static bool trans_MULTu_G(DisasContext *s, arg_muldiv *a)
{
- return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, false);
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false);
}
-static bool trans_MULTU_G(DisasContext *s, arg_muldiv *a)
+static bool trans_DMULTu_G(DisasContext *s, arg_muldiv *a)
{
- return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, true);
-}
-
-static bool trans_DMULT_G(DisasContext *s, arg_muldiv *a)
-{
- return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, false);
-}
-
-static bool trans_DMULTU_G(DisasContext *s, arg_muldiv *a)
-{
- return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, true);
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true);
}
---
Is that correct?
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
2023-08-31 19:12 ` Philippe Mathieu-Daudé
@ 2023-08-31 20:31 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-31 20:31 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Aurelien Jarno, Huacai Chen, Jiaxun Yang
On 31/8/23 21:12, Philippe Mathieu-Daudé wrote:
> On 21/1/21 21:06, Richard Henderson wrote:
>> On 1/12/21 11:55 AM, Philippe Mathieu-Daudé wrote:
>>> Convert the following opcodes to decodetree:
>>>
>>> - MULT.G - multiply 32-bit signed integers
>>> - MULTU.G - multiply 32-bit unsigned integers
>>> - DMULT.G - multiply 64-bit signed integers
>>> - DMULTU.G - multiply 64-bit unsigned integers
>>>
>>> Now that all opcodes from the extension have been converted, we
>>> can remove completely gen_loongson_integer() and its 2 calls in
>>> decode_opc_special2_legacy() and decode_opc_special3_legacy().
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>> target/mips/godson2.decode | 5 ++
>>> target/mips/loong-ext.decode | 5 ++
>>> target/mips/loong_translate.c | 58 ++++++++++++++++++++++
>>> target/mips/translate.c | 92 +----------------------------------
>>> 4 files changed, 70 insertions(+), 90 deletions(-)
>>> +static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
>>> + bool is_double, bool is_unsigned)
>>> +{
>>> + TCGv t0, t1;
>>> +
>>> + if (is_double) {
>>> + if (TARGET_LONG_BITS != 64) {
>>> + return false;
>>> + }
>>> + check_mips_64(s);
>>> + }
>>> +
>>> + if (rd == 0) {
>>> + /* Treat as NOP. */
>>> + return true;
>>> + }
>>> +
>>> + t0 = tcg_temp_new();
>>> + t1 = tcg_temp_new();
>>> +
>>> + gen_load_gpr(t0, rs);
>>> + gen_load_gpr(t1, rt);
>>> +
>>> + if (is_unsigned && !is_double) {
>>> + tcg_gen_ext32u_tl(t0, t0);
>>> + tcg_gen_ext32u_tl(t1, t1);
>>> + }
>>
>> While this is a faithful conversion of the existing code, these
>> extensions make
>> no difference to the result. They are redundant with
>>
>>> + tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
>>> + if (!is_double) {
>>> + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
>>
>> this one, which discards any bit that might have been set by the input
>> bits
>> that are cleared.
>
> I see.
>
>> There is no actual difference between MULT.G and MULTU.G, or DMULT.G and
>> DMULTU.G, because they don't record the most significant bits of the
>> infinite
>> result in any way.
>
> Right.
>
>>> +static bool trans_MULT_G(DisasContext *s, arg_muldiv *a)
>>> +{
>>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, false);
>>> +}
>>> +
>>> +static bool trans_MULTU_G(DisasContext *s, arg_muldiv *a)
>>> +{
>>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false, true);
>>> +}
>>> +
>>> +static bool trans_DMULT_G(DisasContext *s, arg_muldiv *a)
>>> +{
>>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, false);
>>> +}
>>> +
>>> +static bool trans_DMULTU_G(DisasContext *s, arg_muldiv *a)
>>> +{
>>> + return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true, true);
>>> +}
>>
>> So... if you want to clean this up afterward, or before is up to you.
"before" ended being way simpler :>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2021-01-12 21:55 ` [PATCH 6/6] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
@ 2021-01-13 2:15 ` Jiaxun Yang
2021-01-13 8:06 ` Philippe Mathieu-Daudé
2021-01-21 20:07 ` Richard Henderson
7 siblings, 1 reply; 25+ messages in thread
From: Jiaxun Yang @ 2021-01-13 2:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
> Loongson is next step in the "MIPS decodetree conversion" epic.
> Start with the simplest extension.
>
> The diffstat addition comes from the TCG functions expanded.
> The code is easier to review now.
> IMO this is also a good template to show how easy a decodetree
> conversion can be (and how nice the .decode file is to review) :P
>
> Please review,
>
> Phil.
>
> Based-on: <20210112184156.2014305-1-f4bug@amsat.org>
> "decodetree: Allow 'dot' in opcode names"
>
> Philippe Mathieu-Daudé (6):
> target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
> target/mips: Convert Loongson DDIV.G opcodes to decodetree
> target/mips: Convert Loongson DIV.G opcodes to decodetree
> target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
> target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
> target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
>
> target/mips/translate.h | 1 +
> target/mips/godson2.decode | 29 +++
> target/mips/loong-ext.decode | 30 +++
Hi Philippe,
Thanks for the template!
Just a small question, where should we perform ISA availability check?
Before calling generated decoder or after decoded?
Loong-EXT is a super set of Loongson2F's Godson2 and MMI instructions,
how could we tell it?
Thanks.
- Jiaxun
> target/mips/loong_translate.c | 334 ++++++++++++++++++++++++++++++++++
> target/mips/translate.c | 287 ++---------------------------
> target/mips/meson.build | 3 +
> 6 files changed, 409 insertions(+), 275 deletions(-)
> create mode 100644 target/mips/godson2.decode
> create mode 100644 target/mips/loong-ext.decode
> create mode 100644 target/mips/loong_translate.c
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-13 2:15 ` [PATCH 0/6] target/mips: Convert Loongson LEXT " Jiaxun Yang
@ 2021-01-13 8:06 ` Philippe Mathieu-Daudé
2021-01-13 8:09 ` Philippe Mathieu-Daudé
2021-01-13 8:11 ` Jiaxun Yang
0 siblings, 2 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-13 8:06 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On 1/13/21 3:15 AM, Jiaxun Yang wrote:
> 在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
>> Loongson is next step in the "MIPS decodetree conversion" epic.
>> Start with the simplest extension.
>>
>> The diffstat addition comes from the TCG functions expanded.
>> The code is easier to review now.
>> IMO this is also a good template to show how easy a decodetree
>> conversion can be (and how nice the .decode file is to review) :P
>>
>> Please review,
>>
>> Phil.
>>
>> Based-on: <20210112184156.2014305-1-f4bug@amsat.org>
>> "decodetree: Allow 'dot' in opcode names"
>>
>> Philippe Mathieu-Daudé (6):
>> target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
>> target/mips: Convert Loongson DDIV.G opcodes to decodetree
>> target/mips: Convert Loongson DIV.G opcodes to decodetree
>> target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
>> target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
>> target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
>>
>> target/mips/translate.h | 1 +
>> target/mips/godson2.decode | 29 +++
>> target/mips/loong-ext.decode | 30 +++
>
> Hi Philippe,
>
> Thanks for the template!
>
> Just a small question, where should we perform ISA availability check?
> Before calling generated decoder or after decoded?
The check is done before in decode_loongson:
bool decode_loongson(DisasContext *ctx, uint32_t insn)
{
if ((ctx->insn_flags & INSN_LOONGSON2E)
// if ISA available ...
&& decode_godson2(ctx, ctx->opcode)) {
// and opcode supported
// return success
return true;
}
// else keep going ...
if ((ctx->insn_flags & ASE_LEXT)
&& decode_loong_ext(ctx, ctx->opcode)) {
return true;
}
// finally return false, if nothing else decoded
// gen_reserved_instruction will be called in the
// main decode loop.
return false;
}
>
> Loong-EXT is a super set of Loongson2F's Godson2 and MMI instructions,
> how could we tell it?
MMI instructions are currently handled by the ASE_LMMI flag,
a different decoder (which will also be handled by this function,
similarly to ASE_LEXT).
Regards,
Phil.
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-13 8:06 ` Philippe Mathieu-Daudé
@ 2021-01-13 8:09 ` Philippe Mathieu-Daudé
2021-01-13 8:11 ` Jiaxun Yang
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-13 8:09 UTC (permalink / raw)
To: Jiaxun Yang, qemu-devel@nongnu.org Developers
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On Wed, Jan 13, 2021 at 9:06 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 1/13/21 3:15 AM, Jiaxun Yang wrote:
> > Loong-EXT is a super set of Loongson2F's Godson2 and MMI instructions,
> > how could we tell it?
>
> MMI instructions are currently handled by the ASE_LMMI flag,
> a different decoder (which will also be handled by this function,
> similarly to ASE_LEXT).
(BTW no need to spend time converting ASE_LMMI, I already did it, I'm waiting
for the review outcome of this series before posting it).
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-13 8:06 ` Philippe Mathieu-Daudé
2021-01-13 8:09 ` Philippe Mathieu-Daudé
@ 2021-01-13 8:11 ` Jiaxun Yang
1 sibling, 0 replies; 25+ messages in thread
From: Jiaxun Yang @ 2021-01-13 8:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, BALATON Zoltan via
Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson, Aurelien Jarno
On Wed, Jan 13, 2021, at 4:06 PM, Philippe Mathieu-Daudé wrote:
> On 1/13/21 3:15 AM, Jiaxun Yang wrote:
> > 在 2021/1/13 上午5:54, Philippe Mathieu-Daudé 写道:
> >> Loongson is next step in the "MIPS decodetree conversion" epic.
> >> Start with the simplest extension.
> >>
> >> The diffstat addition comes from the TCG functions expanded.
> >> The code is easier to review now.
> >> IMO this is also a good template to show how easy a decodetree
> >> conversion can be (and how nice the .decode file is to review) :P
> >>
> >> Please review,
> >>
> >> Phil.
> >>
> >> Based-on: <20210112184156.2014305-1-f4bug@amsat.org>
> >> "decodetree: Allow 'dot' in opcode names"
> >>
> >> Philippe Mathieu-Daudé (6):
> >> target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
> >> target/mips: Convert Loongson DDIV.G opcodes to decodetree
> >> target/mips: Convert Loongson DIV.G opcodes to decodetree
> >> target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
> >> target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
> >> target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
> >>
> >> target/mips/translate.h | 1 +
> >> target/mips/godson2.decode | 29 +++
> >> target/mips/loong-ext.decode | 30 +++
> >
> > Hi Philippe,
> >
> > Thanks for the template!
> >
> > Just a small question, where should we perform ISA availability check?
> > Before calling generated decoder or after decoded?
>
> The check is done before in decode_loongson:
>
> bool decode_loongson(DisasContext *ctx, uint32_t insn)
> {
> if ((ctx->insn_flags & INSN_LOONGSON2E)
> // if ISA available ...
> && decode_godson2(ctx, ctx->opcode)) {
> // and opcode supported
> // return success
> return true;
> }
> // else keep going ...
>
> if ((ctx->insn_flags & ASE_LEXT)
> && decode_loong_ext(ctx, ctx->opcode)) {
> return true;
> }
>
> // finally return false, if nothing else decoded
> // gen_reserved_instruction will be called in the
> // main decode loop.
> return false;
> }
>
> >
> > Loong-EXT is a super set of Loongson2F's Godson2 and MMI instructions,
> > how could we tell it?
>
> MMI instructions are currently handled by the ASE_LMMI flag,
> a different decoder (which will also be handled by this function,
> similarly to ASE_LEXT).
SWC2/LWC2/SDC2/LDC2 family of LEXT instructions do exist on LEXT but not Loongson-2F.
Thanks.
>
> Regards,
>
> Phil.
>
--
- Jiaxun
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-12 21:54 [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2021-01-13 2:15 ` [PATCH 0/6] target/mips: Convert Loongson LEXT " Jiaxun Yang
@ 2021-01-21 20:07 ` Richard Henderson
2021-01-21 22:20 ` Philippe Mathieu-Daudé
2021-01-25 5:02 ` Jiaxun Yang
7 siblings, 2 replies; 25+ messages in thread
From: Richard Henderson @ 2021-01-21 20:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
> Based-on: <20210112184156.2014305-1-f4bug@amsat.org>
> "decodetree: Allow 'dot' in opcode names"
I'm still unconvinced about this. I've reviewed the code without regard to the
spelling in the decodetree files.
r~
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-21 20:07 ` Richard Henderson
@ 2021-01-21 22:20 ` Philippe Mathieu-Daudé
2021-01-25 5:02 ` Jiaxun Yang
1 sibling, 0 replies; 25+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
On 1/21/21 9:07 PM, Richard Henderson wrote:
> On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
>> Based-on: <20210112184156.2014305-1-f4bug@amsat.org>
>> "decodetree: Allow 'dot' in opcode names"
>
> I'm still unconvinced about this. I've reviewed the code without regard to the
> spelling in the decodetree files.
Understood.
Thanks for your review!
Phil.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/6] target/mips: Convert Loongson LEXT opcodes to decodetree
2021-01-21 20:07 ` Richard Henderson
2021-01-21 22:20 ` Philippe Mathieu-Daudé
@ 2021-01-25 5:02 ` Jiaxun Yang
1 sibling, 0 replies; 25+ messages in thread
From: Jiaxun Yang @ 2021-01-25 5:02 UTC (permalink / raw)
To: Richard Henderson, Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Huacai Chen, Aurelien Jarno
在 2021/1/22 上午4:07, Richard Henderson 写道:
> On 1/12/21 11:54 AM, Philippe Mathieu-Daudé wrote:
>> Based-on: <20210112184156.2014305-1-f4bug@amsat.org>
>> "decodetree: Allow 'dot' in opcode names"
> I'm still unconvinced about this. I've reviewed the code without regard to the
> spelling in the decodetree files.
Should we use '_' in decodetree to replace dot?
Thanks.
- Jiaxun
>
>
> r~
^ permalink raw reply [flat|nested] 25+ messages in thread