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From: Ben Widawsky <ben.widawsky@intel.com>
To: David Rientjes <rientjes@google.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org,
	linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>,
	Chris Browy <cbrowy@avery-design.com>,
	Christoph Hellwig <hch@infradead.org>,
	Jon Masters <jcm@jonmasters.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Rafael Wysocki <rafael.j.wysocki@intel.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	daniel.lll@alibaba-inc.com,
	"John Groves (jgroves)" <jgroves@micron.com>,
	"Kelley, Sean V" <sean.v.kelley@intel.com>
Subject: Re: [PATCH 03/14] cxl/mem: Find device capabilities
Date: Mon, 1 Feb 2021 14:50:52 -0800	[thread overview]
Message-ID: <20210201225052.vrrvuxrsgmddjzbb@intel.com> (raw)
In-Reply-To: <f86149f8-3aea-9d8c-caa9-62771bf22cb5@google.com>

On 21-02-01 14:45:00, David Rientjes wrote:
> On Mon, 1 Feb 2021, Ben Widawsky wrote:
> 
> > > > > > > > > +static int cxl_mem_setup_mailbox(struct cxl_mem *cxlm)
> > > > > > > > > +{
> > > > > > > > > +	const int cap = cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET);
> > > > > > > > > +
> > > > > > > > > +	cxlm->mbox.payload_size =
> > > > > > > > > +		1 << CXL_GET_FIELD(cap, CXLDEV_MB_CAP_PAYLOAD_SIZE);
> > > > > > > > > +
> > > > > > > > > +	/* 8.2.8.4.3 */
> > > > > > > > > +	if (cxlm->mbox.payload_size < 256) {
> > > > > > > > > +		dev_err(&cxlm->pdev->dev, "Mailbox is too small (%zub)",
> > > > > > > > > +			cxlm->mbox.payload_size);
> > > > > > > > > +		return -ENXIO;
> > > > > > > > > +	}
> > > > > > > > 
> > > > > > > > Any reason not to check cxlm->mbox.payload_size > (1 << 20) as well and 
> > > > > > > > return ENXIO if true?
> > > > > > > 
> > > > > > > If some crazy vendor wanted to ship a mailbox larger than 1M, why should the
> > > > > > > driver not allow it?
> > > > > > > 
> > > > > > 
> > > > > > Because the spec disallows it :)
> > > > > 
> > > > > I don't see it being the driver's responsibility to enforce spec correctness
> > > > > though. In certain cases, I need to use the spec, like I have to pick /some/
> > > > > mailbox timeout. For other cases... 
> > > > > 
> > > > > I'm not too familiar with what other similar drivers may or may not do in
> > > > > situations like this. The current 256 limit is mostly a reflection of that being
> > > > > too small to even support advertised mandatory commands. So things can't work in
> > > > > that scenario, but things can work if they have a larger register size (so long
> > > > > as the BAR advertises enough space).
> > > > > 
> > > > 
> > > > I don't think things can work above 1MB, either, though.  Section 
> > > > 8.2.8.4.5 specifies 20 bits to define the payload length, if this is 
> > > > larger than cxlm->mbox.payload_size it would venture into the reserved 
> > > > bits of the command register.
> > > > 
> > > > So is the idea to allow cxl_mem_setup_mailbox() to succeed with a payload 
> > > > size > 1MB and then only check 20 bits for the command register?
> > > 
> > > So it's probably a spec bug, but actually the payload size is 21 bits... I'll
> > > check if that was a mistake.
> > 
> > Well I guess they wanted to be able to specify 1M exactly... Spec should
> > probably say you can't go over 1M
> > 
> 
> I think that's what 8.2.8.4.3 says, no?  And then 8.2.8.4.5 says you 
> can use up to Payload Size.  That's why my recommendation was to enforce 
> this in cxl_mem_setup_mailbox() up front.

Yeah. I asked our spec people to update 8.2.8.4.5 to make it clearer. I'd argue
the intent is how you describe it, but the implementation isn't.

My argument was silly anyway because if you specify greater than 1M as your
payload, you will get EINVAL at the ioctl.

The value of how it works today is the driver will at least bind and allow you
to interact with it.

How strongly do you feel about this?
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WARNING: multiple messages have this Message-ID (diff)
From: Ben Widawsky <ben.widawsky@intel.com>
To: David Rientjes <rientjes@google.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org,
	linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>,
	Chris Browy <cbrowy@avery-design.com>,
	Christoph Hellwig <hch@infradead.org>,
	Dan Williams <dan.j.williams@intel.com>,
	Ira Weiny <ira.weiny@intel.com>, Jon Masters <jcm@jonmasters.org>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Rafael Wysocki <rafael.j.wysocki@intel.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	daniel.lll@alibaba-inc.com,
	"John Groves (jgroves)" <jgroves@micron.com>,
	"Kelley, Sean V" <sean.v.kelley@intel.com>
Subject: Re: [PATCH 03/14] cxl/mem: Find device capabilities
Date: Mon, 1 Feb 2021 14:50:52 -0800	[thread overview]
Message-ID: <20210201225052.vrrvuxrsgmddjzbb@intel.com> (raw)
In-Reply-To: <f86149f8-3aea-9d8c-caa9-62771bf22cb5@google.com>

On 21-02-01 14:45:00, David Rientjes wrote:
> On Mon, 1 Feb 2021, Ben Widawsky wrote:
> 
> > > > > > > > > +static int cxl_mem_setup_mailbox(struct cxl_mem *cxlm)
> > > > > > > > > +{
> > > > > > > > > +	const int cap = cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET);
> > > > > > > > > +
> > > > > > > > > +	cxlm->mbox.payload_size =
> > > > > > > > > +		1 << CXL_GET_FIELD(cap, CXLDEV_MB_CAP_PAYLOAD_SIZE);
> > > > > > > > > +
> > > > > > > > > +	/* 8.2.8.4.3 */
> > > > > > > > > +	if (cxlm->mbox.payload_size < 256) {
> > > > > > > > > +		dev_err(&cxlm->pdev->dev, "Mailbox is too small (%zub)",
> > > > > > > > > +			cxlm->mbox.payload_size);
> > > > > > > > > +		return -ENXIO;
> > > > > > > > > +	}
> > > > > > > > 
> > > > > > > > Any reason not to check cxlm->mbox.payload_size > (1 << 20) as well and 
> > > > > > > > return ENXIO if true?
> > > > > > > 
> > > > > > > If some crazy vendor wanted to ship a mailbox larger than 1M, why should the
> > > > > > > driver not allow it?
> > > > > > > 
> > > > > > 
> > > > > > Because the spec disallows it :)
> > > > > 
> > > > > I don't see it being the driver's responsibility to enforce spec correctness
> > > > > though. In certain cases, I need to use the spec, like I have to pick /some/
> > > > > mailbox timeout. For other cases... 
> > > > > 
> > > > > I'm not too familiar with what other similar drivers may or may not do in
> > > > > situations like this. The current 256 limit is mostly a reflection of that being
> > > > > too small to even support advertised mandatory commands. So things can't work in
> > > > > that scenario, but things can work if they have a larger register size (so long
> > > > > as the BAR advertises enough space).
> > > > > 
> > > > 
> > > > I don't think things can work above 1MB, either, though.  Section 
> > > > 8.2.8.4.5 specifies 20 bits to define the payload length, if this is 
> > > > larger than cxlm->mbox.payload_size it would venture into the reserved 
> > > > bits of the command register.
> > > > 
> > > > So is the idea to allow cxl_mem_setup_mailbox() to succeed with a payload 
> > > > size > 1MB and then only check 20 bits for the command register?
> > > 
> > > So it's probably a spec bug, but actually the payload size is 21 bits... I'll
> > > check if that was a mistake.
> > 
> > Well I guess they wanted to be able to specify 1M exactly... Spec should
> > probably say you can't go over 1M
> > 
> 
> I think that's what 8.2.8.4.3 says, no?  And then 8.2.8.4.5 says you 
> can use up to Payload Size.  That's why my recommendation was to enforce 
> this in cxl_mem_setup_mailbox() up front.

Yeah. I asked our spec people to update 8.2.8.4.5 to make it clearer. I'd argue
the intent is how you describe it, but the implementation isn't.

My argument was silly anyway because if you specify greater than 1M as your
payload, you will get EINVAL at the ioctl.

The value of how it works today is the driver will at least bind and allow you
to interact with it.

How strongly do you feel about this?

  reply	other threads:[~2021-02-01 22:50 UTC|newest]

Thread overview: 193+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-30  0:24 [PATCH 00/14] CXL 2.0 Support Ben Widawsky
2021-01-30  0:24 ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 01/14] cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30 23:51   ` David Rientjes
2021-01-30 23:51     ` David Rientjes
2021-02-01 17:21   ` Jonathan Cameron
2021-02-01 17:21     ` Jonathan Cameron
2021-02-01 17:34   ` Konrad Rzeszutek Wilk
2021-02-01 17:34     ` Konrad Rzeszutek Wilk
2021-02-02 17:58     ` Christoph Hellwig
2021-02-02 17:58       ` Christoph Hellwig
2021-02-02 18:00   ` Christoph Hellwig
2021-02-02 18:00     ` Christoph Hellwig
2021-01-30  0:24 ` [PATCH 02/14] cxl/mem: Map memory device registers Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30 23:51   ` David Rientjes
2021-01-30 23:51     ` David Rientjes
2021-02-01 16:46     ` Ben Widawsky
2021-02-01 16:46       ` Ben Widawsky
2021-02-01 18:19       ` Jonathan Cameron
2021-02-01 18:19         ` Jonathan Cameron
2021-02-01 17:36   ` Konrad Rzeszutek Wilk
2021-02-01 17:36     ` Konrad Rzeszutek Wilk
2021-02-02 18:04   ` Christoph Hellwig
2021-02-02 18:04     ` Christoph Hellwig
2021-02-02 18:31     ` Ben Widawsky
2021-02-02 18:31       ` Ben Widawsky
2021-02-03 17:12       ` Christoph Hellwig
2021-02-03 17:12         ` Christoph Hellwig
2021-01-30  0:24 ` [PATCH 03/14] cxl/mem: Find device capabilities Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30 23:51   ` David Rientjes
2021-01-30 23:51     ` David Rientjes
2021-02-01 16:53     ` Ben Widawsky
2021-02-01 16:53       ` Ben Widawsky
2021-02-01 21:51       ` David Rientjes
2021-02-01 21:51         ` David Rientjes
2021-02-01 21:58         ` Ben Widawsky
2021-02-01 21:58           ` Ben Widawsky
2021-02-01 22:23           ` David Rientjes
2021-02-01 22:23             ` David Rientjes
2021-02-01 22:28             ` Ben Widawsky
2021-02-01 22:28               ` Ben Widawsky
2021-02-01 22:33               ` Ben Widawsky
2021-02-01 22:33                 ` Ben Widawsky
2021-02-01 22:45                 ` David Rientjes
2021-02-01 22:45                   ` David Rientjes
2021-02-01 22:50                   ` Ben Widawsky [this message]
2021-02-01 22:50                     ` Ben Widawsky
2021-02-01 23:09                     ` David Rientjes
2021-02-01 23:09                       ` David Rientjes
2021-02-01 23:17                       ` Ben Widawsky
2021-02-01 23:17                         ` Ben Widawsky
2021-02-01 23:58                         ` David Rientjes
2021-02-01 23:58                           ` David Rientjes
2021-02-02  0:11                           ` Ben Widawsky
2021-02-02  0:11                             ` Ben Widawsky
2021-02-02  0:14                             ` Dan Williams
2021-02-02  0:14                               ` Dan Williams
2021-02-02  1:09                               ` David Rientjes
2021-02-02  1:09                                 ` David Rientjes
2021-02-01 22:02         ` Dan Williams
2021-02-01 22:02           ` Dan Williams
2021-02-01 17:41   ` Konrad Rzeszutek Wilk
2021-02-01 17:41     ` Konrad Rzeszutek Wilk
2021-02-01 17:50     ` Ben Widawsky
2021-02-01 17:50       ` Ben Widawsky
2021-02-01 18:08       ` Konrad Rzeszutek Wilk
2021-02-01 18:08         ` Konrad Rzeszutek Wilk
2021-02-02 18:10   ` Christoph Hellwig
2021-02-02 18:10     ` Christoph Hellwig
2021-02-02 18:24     ` Ben Widawsky
2021-02-02 18:24       ` Ben Widawsky
2021-02-03 17:15       ` Christoph Hellwig
2021-02-03 17:15         ` Christoph Hellwig
2021-02-03 17:23         ` Ben Widawsky
2021-02-03 17:23           ` Ben Widawsky
2021-02-03 21:23           ` Dan Williams
2021-02-03 21:23             ` Dan Williams
2021-02-04  7:16             ` Christoph Hellwig
2021-02-04  7:16               ` Christoph Hellwig
2021-02-04 15:29               ` Ben Widawsky
2021-02-04 15:29                 ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 04/14] cxl/mem: Implement polled mode mailbox Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30 23:51   ` David Rientjes
2021-01-30 23:51     ` David Rientjes
2021-02-01 20:00     ` Dan Williams
2021-02-01 20:00       ` Dan Williams
2021-02-02 22:57       ` Ben Widawsky
2021-02-02 22:57         ` Ben Widawsky
2021-02-02 23:54         ` Dan Williams
2021-02-02 23:54           ` Dan Williams
2021-02-03  0:54           ` Ben Widawsky
2021-02-03  0:54             ` Ben Widawsky
2021-02-02 22:50     ` Ben Widawsky
2021-02-02 22:50       ` Ben Widawsky
2021-02-01 17:54   ` Konrad Rzeszutek Wilk
2021-02-01 17:54     ` Konrad Rzeszutek Wilk
2021-02-01 19:13     ` Ben Widawsky
2021-02-01 19:13       ` Ben Widawsky
2021-02-01 19:28       ` Dan Williams
2021-02-01 19:28         ` Dan Williams
2021-02-04 21:53         ` [EXT] " John Groves (jgroves)
2021-02-04 22:24           ` Ben Widawsky
2021-02-04 22:24             ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 05/14] cxl/mem: Register CXL memX devices Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30  0:31   ` Dan Williams
2021-01-30  0:31     ` Dan Williams
2021-01-30 23:52   ` David Rientjes
2021-01-30 23:52     ` David Rientjes
2021-02-01 17:10     ` Ben Widawsky
2021-02-01 17:10       ` Ben Widawsky
2021-02-01 21:53       ` David Rientjes
2021-02-01 21:53         ` David Rientjes
2021-02-01 21:55         ` Dan Williams
2021-02-01 21:55           ` Dan Williams
2021-02-02 18:13   ` Christoph Hellwig
2021-02-02 18:13     ` Christoph Hellwig
2021-01-30  0:24 ` [PATCH 06/14] cxl/mem: Add basic IOCTL interface Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-02-02 18:15   ` Christoph Hellwig
2021-02-02 18:15     ` Christoph Hellwig
2021-02-02 18:33     ` Ben Widawsky
2021-02-02 18:33       ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 07/14] cxl/mem: Add send command Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-02-01 18:15   ` Konrad Rzeszutek Wilk
2021-02-01 18:15     ` Konrad Rzeszutek Wilk
2021-02-02 23:08     ` Ben Widawsky
2021-02-02 23:08       ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 08/14] taint: add taint for direct hardware access Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-02-01 18:18   ` Konrad Rzeszutek Wilk
2021-02-01 18:18     ` Konrad Rzeszutek Wilk
2021-02-01 18:34     ` Ben Widawsky
2021-02-01 18:34       ` Ben Widawsky
2021-02-01 19:01       ` Dan Williams
2021-02-01 19:01         ` Dan Williams
2021-02-02  2:49         ` Konrad Rzeszutek Wilk
2021-02-02  2:49           ` Konrad Rzeszutek Wilk
2021-02-02 17:46           ` Dan Williams
2021-02-02 17:46             ` Dan Williams
2021-02-08 22:00   ` Dan Williams
2021-02-08 22:00     ` Dan Williams
2021-02-08 22:09     ` Kees Cook
2021-02-08 22:09       ` Kees Cook
2021-02-08 23:05       ` Ben Widawsky
2021-02-08 23:05         ` Ben Widawsky
2021-02-08 23:36       ` Dan Williams
2021-02-08 23:36         ` Dan Williams
2021-02-09  1:03         ` Dan Williams
2021-02-09  1:03           ` Dan Williams
2021-02-09  3:36           ` Ben Widawsky
2021-02-09  3:36             ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 09/14] cxl/mem: Add a "RAW" send command Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-02-01 18:24   ` Konrad Rzeszutek Wilk
2021-02-01 18:24     ` Konrad Rzeszutek Wilk
2021-02-01 19:27     ` Ben Widawsky
2021-02-01 19:27       ` Ben Widawsky
2021-02-01 19:34       ` Konrad Rzeszutek Wilk
2021-02-01 19:34         ` Konrad Rzeszutek Wilk
2021-02-01 21:20         ` Dan Williams
2021-02-01 21:20           ` Dan Williams
2021-01-30  0:24 ` [PATCH 10/14] cxl/mem: Create concept of enabled commands Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 11/14] cxl/mem: Use CEL for enabling commands Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 12/14] cxl/mem: Add set of informational commands Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-01-30  0:24 ` [PATCH 13/14] cxl/mem: Add limited Get Log command (0401h) Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky
2021-02-01 18:28   ` Konrad Rzeszutek Wilk
2021-02-01 18:28     ` Konrad Rzeszutek Wilk
2021-02-02 23:51     ` Ben Widawsky
2021-02-02 23:51       ` Ben Widawsky
2021-02-02 23:57       ` Dan Williams
2021-02-02 23:57         ` Dan Williams
2021-02-03 17:16         ` Ben Widawsky
2021-02-03 17:16           ` Ben Widawsky
2021-02-03 18:14           ` Konrad Rzeszutek Wilk
2021-02-03 18:14             ` Konrad Rzeszutek Wilk
2021-02-03 20:31             ` Dan Williams
2021-02-03 20:31               ` Dan Williams
2021-02-04 18:55               ` Ben Widawsky
2021-02-04 18:55                 ` Ben Widawsky
2021-02-04 21:01                 ` Dan Williams
2021-02-04 21:01                   ` Dan Williams
2021-01-30  0:24 ` [PATCH 14/14] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky
2021-01-30  0:24   ` Ben Widawsky

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