From: Christoph Hellwig <hch@infradead.org> To: Ben Widawsky <ben.widawsky@intel.com> Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org, linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>, Chris Browy <cbrowy@avery-design.com>, Christoph Hellwig <hch@infradead.org>, Jon Masters <jcm@jonmasters.org>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Rafael Wysocki <rafael.j.wysocki@intel.com>, Randy Dunlap <rdunlap@infradead.org>, daniel.lll@alibaba-inc.com, "John Groves (jgroves)" <jgroves@micron.com>, "Kelley, Sean V" <sean.v.kelley@intel.com> Subject: Re: [PATCH 03/14] cxl/mem: Find device capabilities Date: Tue, 2 Feb 2021 18:10:16 +0000 [thread overview] Message-ID: <20210202181016.GD3708021@infradead.org> (raw) In-Reply-To: <20210130002438.1872527-4-ben.widawsky@intel.com> On Fri, Jan 29, 2021 at 04:24:27PM -0800, Ben Widawsky wrote: > #ifndef __CXL_H__ > #define __CXL_H__ > > +#include <linux/bitfield.h> > +#include <linux/bitops.h> > +#include <linux/io.h> > + > +#define CXL_SET_FIELD(value, field) \ > + ({ \ > + WARN_ON(!FIELD_FIT(field##_MASK, value)); \ > + FIELD_PREP(field##_MASK, value); \ > + }) > + > +#define CXL_GET_FIELD(word, field) FIELD_GET(field##_MASK, word) This looks like some massive obsfucation. What is the intent here? > + /* Cap 0001h - CXL_CAP_CAP_ID_DEVICE_STATUS */ > + struct { > + void __iomem *regs; > + } status; > + > + /* Cap 0002h - CXL_CAP_CAP_ID_PRIMARY_MAILBOX */ > + struct { > + void __iomem *regs; > + size_t payload_size; > + } mbox; > + > + /* Cap 4000h - CXL_CAP_CAP_ID_MEMDEV */ > + struct { > + void __iomem *regs; > + } mem; This style looks massively obsfucated. For one the comments look like absolute gibberish, but also what is the point of all these anonymous structures? > +#define cxl_reg(type) \ > + static inline void cxl_write_##type##_reg32(struct cxl_mem *cxlm, \ > + u32 reg, u32 value) \ > + { \ > + void __iomem *reg_addr = cxlm->type.regs; \ > + writel(value, reg_addr + reg); \ > + } \ > + static inline void cxl_write_##type##_reg64(struct cxl_mem *cxlm, \ > + u32 reg, u64 value) \ > + { \ > + void __iomem *reg_addr = cxlm->type.regs; \ > + writeq(value, reg_addr + reg); \ > + } \ What is the value add of all this obsfucation over the trivial calls to the write*/read* functions, possible with a locally declarate "void __iomem *" variable in the callers like in all normall drivers? Except for making the life of the poor soul trying to debug this code some time in the future really hard, of course. > + /* 8.2.8.4.3 */ ???? _______________________________________________ Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org To unsubscribe send an email to linux-nvdimm-leave@lists.01.org
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From: Christoph Hellwig <hch@infradead.org> To: Ben Widawsky <ben.widawsky@intel.com> Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org, linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>, Chris Browy <cbrowy@avery-design.com>, Christoph Hellwig <hch@infradead.org>, Dan Williams <dan.j.williams@intel.com>, Ira Weiny <ira.weiny@intel.com>, Jon Masters <jcm@jonmasters.org>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Rafael Wysocki <rafael.j.wysocki@intel.com>, Randy Dunlap <rdunlap@infradead.org>, Vishal Verma <vishal.l.verma@intel.com>, daniel.lll@alibaba-inc.com, "John Groves (jgroves)" <jgroves@micron.com>, "Kelley, Sean V" <sean.v.kelley@intel.com> Subject: Re: [PATCH 03/14] cxl/mem: Find device capabilities Date: Tue, 2 Feb 2021 18:10:16 +0000 [thread overview] Message-ID: <20210202181016.GD3708021@infradead.org> (raw) In-Reply-To: <20210130002438.1872527-4-ben.widawsky@intel.com> On Fri, Jan 29, 2021 at 04:24:27PM -0800, Ben Widawsky wrote: > #ifndef __CXL_H__ > #define __CXL_H__ > > +#include <linux/bitfield.h> > +#include <linux/bitops.h> > +#include <linux/io.h> > + > +#define CXL_SET_FIELD(value, field) \ > + ({ \ > + WARN_ON(!FIELD_FIT(field##_MASK, value)); \ > + FIELD_PREP(field##_MASK, value); \ > + }) > + > +#define CXL_GET_FIELD(word, field) FIELD_GET(field##_MASK, word) This looks like some massive obsfucation. What is the intent here? > + /* Cap 0001h - CXL_CAP_CAP_ID_DEVICE_STATUS */ > + struct { > + void __iomem *regs; > + } status; > + > + /* Cap 0002h - CXL_CAP_CAP_ID_PRIMARY_MAILBOX */ > + struct { > + void __iomem *regs; > + size_t payload_size; > + } mbox; > + > + /* Cap 4000h - CXL_CAP_CAP_ID_MEMDEV */ > + struct { > + void __iomem *regs; > + } mem; This style looks massively obsfucated. For one the comments look like absolute gibberish, but also what is the point of all these anonymous structures? > +#define cxl_reg(type) \ > + static inline void cxl_write_##type##_reg32(struct cxl_mem *cxlm, \ > + u32 reg, u32 value) \ > + { \ > + void __iomem *reg_addr = cxlm->type.regs; \ > + writel(value, reg_addr + reg); \ > + } \ > + static inline void cxl_write_##type##_reg64(struct cxl_mem *cxlm, \ > + u32 reg, u64 value) \ > + { \ > + void __iomem *reg_addr = cxlm->type.regs; \ > + writeq(value, reg_addr + reg); \ > + } \ What is the value add of all this obsfucation over the trivial calls to the write*/read* functions, possible with a locally declarate "void __iomem *" variable in the callers like in all normall drivers? Except for making the life of the poor soul trying to debug this code some time in the future really hard, of course. > + /* 8.2.8.4.3 */ ????
next prev parent reply other threads:[~2021-02-02 18:10 UTC|newest] Thread overview: 193+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-30 0:24 [PATCH 00/14] CXL 2.0 Support Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 01/14] cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 17:21 ` Jonathan Cameron 2021-02-01 17:21 ` Jonathan Cameron 2021-02-01 17:34 ` Konrad Rzeszutek Wilk 2021-02-01 17:34 ` Konrad Rzeszutek Wilk 2021-02-02 17:58 ` Christoph Hellwig 2021-02-02 17:58 ` Christoph Hellwig 2021-02-02 18:00 ` Christoph Hellwig 2021-02-02 18:00 ` Christoph Hellwig 2021-01-30 0:24 ` [PATCH 02/14] cxl/mem: Map memory device registers Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 16:46 ` Ben Widawsky 2021-02-01 16:46 ` Ben Widawsky 2021-02-01 18:19 ` Jonathan Cameron 2021-02-01 18:19 ` Jonathan Cameron 2021-02-01 17:36 ` Konrad Rzeszutek Wilk 2021-02-01 17:36 ` Konrad Rzeszutek Wilk 2021-02-02 18:04 ` Christoph Hellwig 2021-02-02 18:04 ` Christoph Hellwig 2021-02-02 18:31 ` Ben Widawsky 2021-02-02 18:31 ` Ben Widawsky 2021-02-03 17:12 ` Christoph Hellwig 2021-02-03 17:12 ` Christoph Hellwig 2021-01-30 0:24 ` [PATCH 03/14] cxl/mem: Find device capabilities Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 16:53 ` Ben Widawsky 2021-02-01 16:53 ` Ben Widawsky 2021-02-01 21:51 ` David Rientjes 2021-02-01 21:51 ` David Rientjes 2021-02-01 21:58 ` Ben Widawsky 2021-02-01 21:58 ` Ben Widawsky 2021-02-01 22:23 ` David Rientjes 2021-02-01 22:23 ` David Rientjes 2021-02-01 22:28 ` Ben Widawsky 2021-02-01 22:28 ` Ben Widawsky 2021-02-01 22:33 ` Ben Widawsky 2021-02-01 22:33 ` Ben Widawsky 2021-02-01 22:45 ` David Rientjes 2021-02-01 22:45 ` David Rientjes 2021-02-01 22:50 ` Ben Widawsky 2021-02-01 22:50 ` Ben Widawsky 2021-02-01 23:09 ` David Rientjes 2021-02-01 23:09 ` David Rientjes 2021-02-01 23:17 ` Ben Widawsky 2021-02-01 23:17 ` Ben Widawsky 2021-02-01 23:58 ` David Rientjes 2021-02-01 23:58 ` David Rientjes 2021-02-02 0:11 ` Ben Widawsky 2021-02-02 0:11 ` Ben Widawsky 2021-02-02 0:14 ` Dan Williams 2021-02-02 0:14 ` Dan Williams 2021-02-02 1:09 ` David Rientjes 2021-02-02 1:09 ` David Rientjes 2021-02-01 22:02 ` Dan Williams 2021-02-01 22:02 ` Dan Williams 2021-02-01 17:41 ` Konrad Rzeszutek Wilk 2021-02-01 17:41 ` Konrad Rzeszutek Wilk 2021-02-01 17:50 ` Ben Widawsky 2021-02-01 17:50 ` Ben Widawsky 2021-02-01 18:08 ` Konrad Rzeszutek Wilk 2021-02-01 18:08 ` Konrad Rzeszutek Wilk 2021-02-02 18:10 ` Christoph Hellwig [this message] 2021-02-02 18:10 ` Christoph Hellwig 2021-02-02 18:24 ` Ben Widawsky 2021-02-02 18:24 ` Ben Widawsky 2021-02-03 17:15 ` Christoph Hellwig 2021-02-03 17:15 ` Christoph Hellwig 2021-02-03 17:23 ` Ben Widawsky 2021-02-03 17:23 ` Ben Widawsky 2021-02-03 21:23 ` Dan Williams 2021-02-03 21:23 ` Dan Williams 2021-02-04 7:16 ` Christoph Hellwig 2021-02-04 7:16 ` Christoph Hellwig 2021-02-04 15:29 ` Ben Widawsky 2021-02-04 15:29 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 04/14] cxl/mem: Implement polled mode mailbox Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 20:00 ` Dan Williams 2021-02-01 20:00 ` Dan Williams 2021-02-02 22:57 ` Ben Widawsky 2021-02-02 22:57 ` Ben Widawsky 2021-02-02 23:54 ` Dan Williams 2021-02-02 23:54 ` Dan Williams 2021-02-03 0:54 ` Ben Widawsky 2021-02-03 0:54 ` Ben Widawsky 2021-02-02 22:50 ` Ben Widawsky 2021-02-02 22:50 ` Ben Widawsky 2021-02-01 17:54 ` Konrad Rzeszutek Wilk 2021-02-01 17:54 ` Konrad Rzeszutek Wilk 2021-02-01 19:13 ` Ben Widawsky 2021-02-01 19:13 ` Ben Widawsky 2021-02-01 19:28 ` Dan Williams 2021-02-01 19:28 ` Dan Williams 2021-02-04 21:53 ` [EXT] " John Groves (jgroves) 2021-02-04 22:24 ` Ben Widawsky 2021-02-04 22:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 05/14] cxl/mem: Register CXL memX devices Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:31 ` Dan Williams 2021-01-30 0:31 ` Dan Williams 2021-01-30 23:52 ` David Rientjes 2021-01-30 23:52 ` David Rientjes 2021-02-01 17:10 ` Ben Widawsky 2021-02-01 17:10 ` Ben Widawsky 2021-02-01 21:53 ` David Rientjes 2021-02-01 21:53 ` David Rientjes 2021-02-01 21:55 ` Dan Williams 2021-02-01 21:55 ` Dan Williams 2021-02-02 18:13 ` Christoph Hellwig 2021-02-02 18:13 ` Christoph Hellwig 2021-01-30 0:24 ` [PATCH 06/14] cxl/mem: Add basic IOCTL interface Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-02 18:15 ` Christoph Hellwig 2021-02-02 18:15 ` Christoph Hellwig 2021-02-02 18:33 ` Ben Widawsky 2021-02-02 18:33 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 07/14] cxl/mem: Add send command Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:15 ` Konrad Rzeszutek Wilk 2021-02-01 18:15 ` Konrad Rzeszutek Wilk 2021-02-02 23:08 ` Ben Widawsky 2021-02-02 23:08 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 08/14] taint: add taint for direct hardware access Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:18 ` Konrad Rzeszutek Wilk 2021-02-01 18:18 ` Konrad Rzeszutek Wilk 2021-02-01 18:34 ` Ben Widawsky 2021-02-01 18:34 ` Ben Widawsky 2021-02-01 19:01 ` Dan Williams 2021-02-01 19:01 ` Dan Williams 2021-02-02 2:49 ` Konrad Rzeszutek Wilk 2021-02-02 2:49 ` Konrad Rzeszutek Wilk 2021-02-02 17:46 ` Dan Williams 2021-02-02 17:46 ` Dan Williams 2021-02-08 22:00 ` Dan Williams 2021-02-08 22:00 ` Dan Williams 2021-02-08 22:09 ` Kees Cook 2021-02-08 22:09 ` Kees Cook 2021-02-08 23:05 ` Ben Widawsky 2021-02-08 23:05 ` Ben Widawsky 2021-02-08 23:36 ` Dan Williams 2021-02-08 23:36 ` Dan Williams 2021-02-09 1:03 ` Dan Williams 2021-02-09 1:03 ` Dan Williams 2021-02-09 3:36 ` Ben Widawsky 2021-02-09 3:36 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 09/14] cxl/mem: Add a "RAW" send command Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:24 ` Konrad Rzeszutek Wilk 2021-02-01 18:24 ` Konrad Rzeszutek Wilk 2021-02-01 19:27 ` Ben Widawsky 2021-02-01 19:27 ` Ben Widawsky 2021-02-01 19:34 ` Konrad Rzeszutek Wilk 2021-02-01 19:34 ` Konrad Rzeszutek Wilk 2021-02-01 21:20 ` Dan Williams 2021-02-01 21:20 ` Dan Williams 2021-01-30 0:24 ` [PATCH 10/14] cxl/mem: Create concept of enabled commands Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 11/14] cxl/mem: Use CEL for enabling commands Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 12/14] cxl/mem: Add set of informational commands Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 13/14] cxl/mem: Add limited Get Log command (0401h) Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:28 ` Konrad Rzeszutek Wilk 2021-02-01 18:28 ` Konrad Rzeszutek Wilk 2021-02-02 23:51 ` Ben Widawsky 2021-02-02 23:51 ` Ben Widawsky 2021-02-02 23:57 ` Dan Williams 2021-02-02 23:57 ` Dan Williams 2021-02-03 17:16 ` Ben Widawsky 2021-02-03 17:16 ` Ben Widawsky 2021-02-03 18:14 ` Konrad Rzeszutek Wilk 2021-02-03 18:14 ` Konrad Rzeszutek Wilk 2021-02-03 20:31 ` Dan Williams 2021-02-03 20:31 ` Dan Williams 2021-02-04 18:55 ` Ben Widawsky 2021-02-04 18:55 ` Ben Widawsky 2021-02-04 21:01 ` Dan Williams 2021-02-04 21:01 ` Dan Williams 2021-01-30 0:24 ` [PATCH 14/14] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky
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