From: Dan Williams <dan.j.williams@intel.com> To: Ben Widawsky <ben.widawsky@intel.com> Cc: Christoph Hellwig <hch@infradead.org>, linux-cxl@vger.kernel.org, Linux ACPI <linux-acpi@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-nvdimm <linux-nvdimm@lists.01.org>, Linux PCI <linux-pci@vger.kernel.org>, Bjorn Helgaas <helgaas@kernel.org>, Chris Browy <cbrowy@avery-design.com>, Jon Masters <jcm@jonmasters.org>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Rafael Wysocki <rafael.j.wysocki@intel.com>, Randy Dunlap <rdunlap@infradead.org>, daniel.lll@alibaba-inc.com, "John Groves (jgroves)" <jgroves@micron.com>, "Kelley, Sean V" <sean.v.kelley@intel.com> Subject: Re: [PATCH 03/14] cxl/mem: Find device capabilities Date: Wed, 3 Feb 2021 13:23:31 -0800 [thread overview] Message-ID: <CAPcyv4hvFjs=QqmUYqPipuaLoFiZ-dr6qVhqbDupWuKTw3QDkg@mail.gmail.com> (raw) In-Reply-To: <20210203172342.fpn5vm4xj2xwh6fq@intel.com> On Wed, Feb 3, 2021 at 9:23 AM Ben Widawsky <ben.widawsky@intel.com> wrote: > > On 21-02-03 17:15:34, Christoph Hellwig wrote: > > On Tue, Feb 02, 2021 at 10:24:18AM -0800, Ben Widawsky wrote: > > > > > + /* Cap 4000h - CXL_CAP_CAP_ID_MEMDEV */ > > > > > + struct { > > > > > + void __iomem *regs; > > > > > + } mem; > > > > > > > > This style looks massively obsfucated. For one the comments look like > > > > absolute gibberish, but also what is the point of all these anonymous > > > > structures? > > > > > > They're not anonymous, and their names are for the below register functions. The > > > comments are connected spec reference 'Cap XXXXh' to definitions in cxl.h. I can > > > articulate that if it helps. > > > > But why no simply a > > > > void __iomem *mem_regs; > > > > field vs the extra struct? > > > > > The register space for CXL devices is a bit weird since it's all subdivided > > > under 1 BAR for now. To clearly distinguish over the different subregions, these > > > helpers exist. It's really easy to mess this up as the developer and I actually > > > would disagree that it makes debugging quite a bit easier. It also gets more > > > convoluted when you add the other 2 BARs which also each have their own > > > subregions. > > > > > > For example. if my mailbox function does: > > > cxl_read_status_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET); > > > > > > instead of: > > > cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET); > > > > > > It's easier to spot than: > > > readl(cxlm->regs + cxlm->status_offset + CXLDEV_MB_CAPS_OFFSET) > > > > Well, what I think would be the most obvious is: > > > > readl(cxlm->status_regs + CXLDEV_MB_CAPS_OFFSET); > > > > Right, so you wrote the buggy version. Should be. > readl(cxlm->mbox_regs + CXLDEV_MB_CAPS_OFFSET); > > Admittedly, "MB" for mailbox isn't super obvious. I think you've convinced me to > rename these register definitions > s/MB/MBOX. > > I'd prefer to keep the helpers for now as I do find them helpful, and so far > nobody else who has touched the code has complained. If you feel strongly, I > will change it. After seeing the options, I think I'd prefer to not have to worry what extra magic is happening with cxl_read_mbox_reg32() cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET); readl(cxlm->mbox_regs + CXLDEV_MB_CAPS_OFFSET); The latter is both shorter and more idiomatic. > > > > > > + /* 8.2.8.4.3 */ > > > > > > > > ???? > > > > > > > > > > I had been trying to be consistent with 'CXL2.0 - ' in front of all spec > > > reference. I obviously missed this one. > > > > FYI, I generally find section names much easier to find than section > > numbers. Especially as the numbers change very frequently, some times > > even for very minor updates to the spec. E.g. in NVMe the numbers might > > even change from NVMe 1.X to NVMe 1.Xa because an errata had to add > > a clarification as its own section. > > Why not both? > > I ran into this in fact going from version 0.7 to 1.0 of the spec. I did call > out the spec version to address this, but you're right. Section names can change > too in theory. > > /* > * CXL 2.0 8.2.8.4.3 > * Mailbox Capabilities Register > */ > > Too much? That seems like too many lines. /* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */ ...this looks ok. _______________________________________________ Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org To unsubscribe send an email to linux-nvdimm-leave@lists.01.org
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From: Dan Williams <dan.j.williams@intel.com> To: Ben Widawsky <ben.widawsky@intel.com> Cc: Christoph Hellwig <hch@infradead.org>, linux-cxl@vger.kernel.org, Linux ACPI <linux-acpi@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-nvdimm <linux-nvdimm@lists.01.org>, Linux PCI <linux-pci@vger.kernel.org>, Bjorn Helgaas <helgaas@kernel.org>, Chris Browy <cbrowy@avery-design.com>, Ira Weiny <ira.weiny@intel.com>, Jon Masters <jcm@jonmasters.org>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Rafael Wysocki <rafael.j.wysocki@intel.com>, Randy Dunlap <rdunlap@infradead.org>, Vishal Verma <vishal.l.verma@intel.com>, daniel.lll@alibaba-inc.com, "John Groves (jgroves)" <jgroves@micron.com>, "Kelley, Sean V" <sean.v.kelley@intel.com> Subject: Re: [PATCH 03/14] cxl/mem: Find device capabilities Date: Wed, 3 Feb 2021 13:23:31 -0800 [thread overview] Message-ID: <CAPcyv4hvFjs=QqmUYqPipuaLoFiZ-dr6qVhqbDupWuKTw3QDkg@mail.gmail.com> (raw) In-Reply-To: <20210203172342.fpn5vm4xj2xwh6fq@intel.com> On Wed, Feb 3, 2021 at 9:23 AM Ben Widawsky <ben.widawsky@intel.com> wrote: > > On 21-02-03 17:15:34, Christoph Hellwig wrote: > > On Tue, Feb 02, 2021 at 10:24:18AM -0800, Ben Widawsky wrote: > > > > > + /* Cap 4000h - CXL_CAP_CAP_ID_MEMDEV */ > > > > > + struct { > > > > > + void __iomem *regs; > > > > > + } mem; > > > > > > > > This style looks massively obsfucated. For one the comments look like > > > > absolute gibberish, but also what is the point of all these anonymous > > > > structures? > > > > > > They're not anonymous, and their names are for the below register functions. The > > > comments are connected spec reference 'Cap XXXXh' to definitions in cxl.h. I can > > > articulate that if it helps. > > > > But why no simply a > > > > void __iomem *mem_regs; > > > > field vs the extra struct? > > > > > The register space for CXL devices is a bit weird since it's all subdivided > > > under 1 BAR for now. To clearly distinguish over the different subregions, these > > > helpers exist. It's really easy to mess this up as the developer and I actually > > > would disagree that it makes debugging quite a bit easier. It also gets more > > > convoluted when you add the other 2 BARs which also each have their own > > > subregions. > > > > > > For example. if my mailbox function does: > > > cxl_read_status_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET); > > > > > > instead of: > > > cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET); > > > > > > It's easier to spot than: > > > readl(cxlm->regs + cxlm->status_offset + CXLDEV_MB_CAPS_OFFSET) > > > > Well, what I think would be the most obvious is: > > > > readl(cxlm->status_regs + CXLDEV_MB_CAPS_OFFSET); > > > > Right, so you wrote the buggy version. Should be. > readl(cxlm->mbox_regs + CXLDEV_MB_CAPS_OFFSET); > > Admittedly, "MB" for mailbox isn't super obvious. I think you've convinced me to > rename these register definitions > s/MB/MBOX. > > I'd prefer to keep the helpers for now as I do find them helpful, and so far > nobody else who has touched the code has complained. If you feel strongly, I > will change it. After seeing the options, I think I'd prefer to not have to worry what extra magic is happening with cxl_read_mbox_reg32() cxl_read_mbox_reg32(cxlm, CXLDEV_MB_CAPS_OFFSET); readl(cxlm->mbox_regs + CXLDEV_MB_CAPS_OFFSET); The latter is both shorter and more idiomatic. > > > > > > + /* 8.2.8.4.3 */ > > > > > > > > ???? > > > > > > > > > > I had been trying to be consistent with 'CXL2.0 - ' in front of all spec > > > reference. I obviously missed this one. > > > > FYI, I generally find section names much easier to find than section > > numbers. Especially as the numbers change very frequently, some times > > even for very minor updates to the spec. E.g. in NVMe the numbers might > > even change from NVMe 1.X to NVMe 1.Xa because an errata had to add > > a clarification as its own section. > > Why not both? > > I ran into this in fact going from version 0.7 to 1.0 of the spec. I did call > out the spec version to address this, but you're right. Section names can change > too in theory. > > /* > * CXL 2.0 8.2.8.4.3 > * Mailbox Capabilities Register > */ > > Too much? That seems like too many lines. /* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */ ...this looks ok.
next prev parent reply other threads:[~2021-02-03 21:23 UTC|newest] Thread overview: 193+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-30 0:24 [PATCH 00/14] CXL 2.0 Support Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 01/14] cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 17:21 ` Jonathan Cameron 2021-02-01 17:21 ` Jonathan Cameron 2021-02-01 17:34 ` Konrad Rzeszutek Wilk 2021-02-01 17:34 ` Konrad Rzeszutek Wilk 2021-02-02 17:58 ` Christoph Hellwig 2021-02-02 17:58 ` Christoph Hellwig 2021-02-02 18:00 ` Christoph Hellwig 2021-02-02 18:00 ` Christoph Hellwig 2021-01-30 0:24 ` [PATCH 02/14] cxl/mem: Map memory device registers Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 16:46 ` Ben Widawsky 2021-02-01 16:46 ` Ben Widawsky 2021-02-01 18:19 ` Jonathan Cameron 2021-02-01 18:19 ` Jonathan Cameron 2021-02-01 17:36 ` Konrad Rzeszutek Wilk 2021-02-01 17:36 ` Konrad Rzeszutek Wilk 2021-02-02 18:04 ` Christoph Hellwig 2021-02-02 18:04 ` Christoph Hellwig 2021-02-02 18:31 ` Ben Widawsky 2021-02-02 18:31 ` Ben Widawsky 2021-02-03 17:12 ` Christoph Hellwig 2021-02-03 17:12 ` Christoph Hellwig 2021-01-30 0:24 ` [PATCH 03/14] cxl/mem: Find device capabilities Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 16:53 ` Ben Widawsky 2021-02-01 16:53 ` Ben Widawsky 2021-02-01 21:51 ` David Rientjes 2021-02-01 21:51 ` David Rientjes 2021-02-01 21:58 ` Ben Widawsky 2021-02-01 21:58 ` Ben Widawsky 2021-02-01 22:23 ` David Rientjes 2021-02-01 22:23 ` David Rientjes 2021-02-01 22:28 ` Ben Widawsky 2021-02-01 22:28 ` Ben Widawsky 2021-02-01 22:33 ` Ben Widawsky 2021-02-01 22:33 ` Ben Widawsky 2021-02-01 22:45 ` David Rientjes 2021-02-01 22:45 ` David Rientjes 2021-02-01 22:50 ` Ben Widawsky 2021-02-01 22:50 ` Ben Widawsky 2021-02-01 23:09 ` David Rientjes 2021-02-01 23:09 ` David Rientjes 2021-02-01 23:17 ` Ben Widawsky 2021-02-01 23:17 ` Ben Widawsky 2021-02-01 23:58 ` David Rientjes 2021-02-01 23:58 ` David Rientjes 2021-02-02 0:11 ` Ben Widawsky 2021-02-02 0:11 ` Ben Widawsky 2021-02-02 0:14 ` Dan Williams 2021-02-02 0:14 ` Dan Williams 2021-02-02 1:09 ` David Rientjes 2021-02-02 1:09 ` David Rientjes 2021-02-01 22:02 ` Dan Williams 2021-02-01 22:02 ` Dan Williams 2021-02-01 17:41 ` Konrad Rzeszutek Wilk 2021-02-01 17:41 ` Konrad Rzeszutek Wilk 2021-02-01 17:50 ` Ben Widawsky 2021-02-01 17:50 ` Ben Widawsky 2021-02-01 18:08 ` Konrad Rzeszutek Wilk 2021-02-01 18:08 ` Konrad Rzeszutek Wilk 2021-02-02 18:10 ` Christoph Hellwig 2021-02-02 18:10 ` Christoph Hellwig 2021-02-02 18:24 ` Ben Widawsky 2021-02-02 18:24 ` Ben Widawsky 2021-02-03 17:15 ` Christoph Hellwig 2021-02-03 17:15 ` Christoph Hellwig 2021-02-03 17:23 ` Ben Widawsky 2021-02-03 17:23 ` Ben Widawsky 2021-02-03 21:23 ` Dan Williams [this message] 2021-02-03 21:23 ` Dan Williams 2021-02-04 7:16 ` Christoph Hellwig 2021-02-04 7:16 ` Christoph Hellwig 2021-02-04 15:29 ` Ben Widawsky 2021-02-04 15:29 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 04/14] cxl/mem: Implement polled mode mailbox Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 23:51 ` David Rientjes 2021-01-30 23:51 ` David Rientjes 2021-02-01 20:00 ` Dan Williams 2021-02-01 20:00 ` Dan Williams 2021-02-02 22:57 ` Ben Widawsky 2021-02-02 22:57 ` Ben Widawsky 2021-02-02 23:54 ` Dan Williams 2021-02-02 23:54 ` Dan Williams 2021-02-03 0:54 ` Ben Widawsky 2021-02-03 0:54 ` Ben Widawsky 2021-02-02 22:50 ` Ben Widawsky 2021-02-02 22:50 ` Ben Widawsky 2021-02-01 17:54 ` Konrad Rzeszutek Wilk 2021-02-01 17:54 ` Konrad Rzeszutek Wilk 2021-02-01 19:13 ` Ben Widawsky 2021-02-01 19:13 ` Ben Widawsky 2021-02-01 19:28 ` Dan Williams 2021-02-01 19:28 ` Dan Williams 2021-02-04 21:53 ` [EXT] " John Groves (jgroves) 2021-02-04 22:24 ` Ben Widawsky 2021-02-04 22:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 05/14] cxl/mem: Register CXL memX devices Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:31 ` Dan Williams 2021-01-30 0:31 ` Dan Williams 2021-01-30 23:52 ` David Rientjes 2021-01-30 23:52 ` David Rientjes 2021-02-01 17:10 ` Ben Widawsky 2021-02-01 17:10 ` Ben Widawsky 2021-02-01 21:53 ` David Rientjes 2021-02-01 21:53 ` David Rientjes 2021-02-01 21:55 ` Dan Williams 2021-02-01 21:55 ` Dan Williams 2021-02-02 18:13 ` Christoph Hellwig 2021-02-02 18:13 ` Christoph Hellwig 2021-01-30 0:24 ` [PATCH 06/14] cxl/mem: Add basic IOCTL interface Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-02 18:15 ` Christoph Hellwig 2021-02-02 18:15 ` Christoph Hellwig 2021-02-02 18:33 ` Ben Widawsky 2021-02-02 18:33 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 07/14] cxl/mem: Add send command Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:15 ` Konrad Rzeszutek Wilk 2021-02-01 18:15 ` Konrad Rzeszutek Wilk 2021-02-02 23:08 ` Ben Widawsky 2021-02-02 23:08 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 08/14] taint: add taint for direct hardware access Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:18 ` Konrad Rzeszutek Wilk 2021-02-01 18:18 ` Konrad Rzeszutek Wilk 2021-02-01 18:34 ` Ben Widawsky 2021-02-01 18:34 ` Ben Widawsky 2021-02-01 19:01 ` Dan Williams 2021-02-01 19:01 ` Dan Williams 2021-02-02 2:49 ` Konrad Rzeszutek Wilk 2021-02-02 2:49 ` Konrad Rzeszutek Wilk 2021-02-02 17:46 ` Dan Williams 2021-02-02 17:46 ` Dan Williams 2021-02-08 22:00 ` Dan Williams 2021-02-08 22:00 ` Dan Williams 2021-02-08 22:09 ` Kees Cook 2021-02-08 22:09 ` Kees Cook 2021-02-08 23:05 ` Ben Widawsky 2021-02-08 23:05 ` Ben Widawsky 2021-02-08 23:36 ` Dan Williams 2021-02-08 23:36 ` Dan Williams 2021-02-09 1:03 ` Dan Williams 2021-02-09 1:03 ` Dan Williams 2021-02-09 3:36 ` Ben Widawsky 2021-02-09 3:36 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 09/14] cxl/mem: Add a "RAW" send command Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:24 ` Konrad Rzeszutek Wilk 2021-02-01 18:24 ` Konrad Rzeszutek Wilk 2021-02-01 19:27 ` Ben Widawsky 2021-02-01 19:27 ` Ben Widawsky 2021-02-01 19:34 ` Konrad Rzeszutek Wilk 2021-02-01 19:34 ` Konrad Rzeszutek Wilk 2021-02-01 21:20 ` Dan Williams 2021-02-01 21:20 ` Dan Williams 2021-01-30 0:24 ` [PATCH 10/14] cxl/mem: Create concept of enabled commands Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 11/14] cxl/mem: Use CEL for enabling commands Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 12/14] cxl/mem: Add set of informational commands Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-01-30 0:24 ` [PATCH 13/14] cxl/mem: Add limited Get Log command (0401h) Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky 2021-02-01 18:28 ` Konrad Rzeszutek Wilk 2021-02-01 18:28 ` Konrad Rzeszutek Wilk 2021-02-02 23:51 ` Ben Widawsky 2021-02-02 23:51 ` Ben Widawsky 2021-02-02 23:57 ` Dan Williams 2021-02-02 23:57 ` Dan Williams 2021-02-03 17:16 ` Ben Widawsky 2021-02-03 17:16 ` Ben Widawsky 2021-02-03 18:14 ` Konrad Rzeszutek Wilk 2021-02-03 18:14 ` Konrad Rzeszutek Wilk 2021-02-03 20:31 ` Dan Williams 2021-02-03 20:31 ` Dan Williams 2021-02-04 18:55 ` Ben Widawsky 2021-02-04 18:55 ` Ben Widawsky 2021-02-04 21:01 ` Dan Williams 2021-02-04 21:01 ` Dan Williams 2021-01-30 0:24 ` [PATCH 14/14] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky 2021-01-30 0:24 ` Ben Widawsky
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