All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
	suzuki.poulose@arm.com, mike.leach@linaro.org,
	lcherian@marvell.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
Date: Fri, 12 Feb 2021 09:57:34 -0700	[thread overview]
Message-ID: <20210212165734.GA2692426@xps15> (raw)
In-Reply-To: <be83fd32-e552-ac06-6ee5-3bf22c6daab2@arm.com>

[...]

> > 
> > 
> >> +	if (nr_pages < 2)
> >> +		return NULL;
> >> +
> >> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> >> +	if (IS_ERR(buf))
> >> +		return ERR_PTR(-ENOMEM);
> >> +
> >> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> >> +	if (IS_ERR(pglist)) {
> >> +		kfree(buf);
> >> +		return ERR_PTR(-ENOMEM);
> >> +	}
> >> +
> >> +	for (i = 0; i < nr_pages; i++)
> >> +		pglist[i] = virt_to_page(pages[i]);
> >> +
> >> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> >> +	if (IS_ERR((void *)buf->trbe_base)) {
> > 
> > Why not simply make buf->trbe_base a void * instead of having to do all this
> 
> There are many arithmetic and comparison operations involving trbe_base
> element. Hence it might be better to keep it as unsigned long, also to
> keeps it consistent with other pointers i.e trbe_write, trbe_limit.

That is a fair point.  Please add a comment to explain your design choice and
make sure the sparse checker is happy with all of it.

> 
> Snippet from $cat drivers/hwtracing/coresight/coresight-trbe.c | grep "trbe_base"
> There are just two places type casting trbe_base back to (void *).
> 
> 	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> 	return buf->trbe_base + offset;
> 	WARN_ON(buf->trbe_write < buf->trbe_base);
> 	set_trbe_base_pointer(buf->trbe_base);
> 	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> 	if (IS_ERR((void *)buf->trbe_base)) {
> 		return ERR_PTR(buf->trbe_base);
> 	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> 	buf->trbe_write = buf->trbe_base;
> 	vunmap((void *)buf->trbe_base);
> 	base = get_trbe_base_pointer();
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> 		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>   
> > casting?  And IS_ERR() doesn't work with vmap().
> 
> Sure, will drop IS_ERR() here.
> 

[...]


> > 
> >> +
> >> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> >> +{
> >> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> >> +
> >> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> >> +}
> >> +static DEVICE_ATTR_RO(dbm);
> > 
> > What does "dbm" stand for?  Looking at the documentation for TRBIDR_EL1.F, I
> > don't see what "dbm" relates to.
> 
> I made it up to refer TRBIDR_EL1.F as "Dirty (and Access Flag) Bit Management".
> Could change it as "afdbm" to be more specific or if it is preferred.
> 

I don't see "afdbm" being a better solution - why not simply "flag"?


WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lcherian@marvell.com,
	mike.leach@linaro.org
Subject: Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
Date: Fri, 12 Feb 2021 09:57:34 -0700	[thread overview]
Message-ID: <20210212165734.GA2692426@xps15> (raw)
In-Reply-To: <be83fd32-e552-ac06-6ee5-3bf22c6daab2@arm.com>

[...]

> > 
> > 
> >> +	if (nr_pages < 2)
> >> +		return NULL;
> >> +
> >> +	buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
> >> +	if (IS_ERR(buf))
> >> +		return ERR_PTR(-ENOMEM);
> >> +
> >> +	pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
> >> +	if (IS_ERR(pglist)) {
> >> +		kfree(buf);
> >> +		return ERR_PTR(-ENOMEM);
> >> +	}
> >> +
> >> +	for (i = 0; i < nr_pages; i++)
> >> +		pglist[i] = virt_to_page(pages[i]);
> >> +
> >> +	buf->trbe_base = (unsigned long) vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> >> +	if (IS_ERR((void *)buf->trbe_base)) {
> > 
> > Why not simply make buf->trbe_base a void * instead of having to do all this
> 
> There are many arithmetic and comparison operations involving trbe_base
> element. Hence it might be better to keep it as unsigned long, also to
> keeps it consistent with other pointers i.e trbe_write, trbe_limit.

That is a fair point.  Please add a comment to explain your design choice and
make sure the sparse checker is happy with all of it.

> 
> Snippet from $cat drivers/hwtracing/coresight/coresight-trbe.c | grep "trbe_base"
> There are just two places type casting trbe_base back to (void *).
> 
> 	memset((void *)buf->trbe_base + head, ETE_IGNORE_PACKET, len);
> 	return buf->trbe_base + offset;
> 	WARN_ON(buf->trbe_write < buf->trbe_base);
> 	set_trbe_base_pointer(buf->trbe_base);
> 	buf->trbe_base = (unsigned long)vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
> 	if (IS_ERR((void *)buf->trbe_base)) {
> 		return ERR_PTR(buf->trbe_base);
> 	buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
> 	buf->trbe_write = buf->trbe_base;
> 	vunmap((void *)buf->trbe_base);
> 	base = get_trbe_base_pointer();
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> 	buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf);
> 	if (buf->trbe_limit == buf->trbe_base) {
> 	WARN_ON(buf->trbe_base != get_trbe_base_pointer());
> 		if (get_trbe_write_pointer() == get_trbe_base_pointer())
>   
> > casting?  And IS_ERR() doesn't work with vmap().
> 
> Sure, will drop IS_ERR() here.
> 

[...]


> > 
> >> +
> >> +static ssize_t dbm_show(struct device *dev, struct device_attribute *attr, char *buf)
> >> +{
> >> +	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
> >> +
> >> +	return sprintf(buf, "%d\n", cpudata->trbe_dbm);
> >> +}
> >> +static DEVICE_ATTR_RO(dbm);
> > 
> > What does "dbm" stand for?  Looking at the documentation for TRBIDR_EL1.F, I
> > don't see what "dbm" relates to.
> 
> I made it up to refer TRBIDR_EL1.F as "Dirty (and Access Flag) Bit Management".
> Could change it as "afdbm" to be more specific or if it is preferred.
> 

I don't see "afdbm" being a better solution - why not simply "flag"?


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-02-12 16:58 UTC|newest]

Thread overview: 181+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27  8:55 ` Anshuman Khandual
2021-01-27  8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-01 23:17   ` Mathieu Poirier
2021-02-01 23:17     ` Mathieu Poirier
2021-02-02  9:42     ` Suzuki K Poulose
2021-02-02  9:42       ` Suzuki K Poulose
2021-02-02 16:33       ` Mike Leach
2021-02-02 16:33         ` Mike Leach
2021-02-02 22:41         ` Suzuki K Poulose
2021-02-02 22:41           ` Suzuki K Poulose
2021-02-04 12:27           ` Mike Leach
2021-02-04 12:27             ` Mike Leach
2021-02-02 16:37       ` Mathieu Poirier
2021-02-02 16:37         ` Mathieu Poirier
2021-01-27  8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-01 23:44   ` Mathieu Poirier
2021-02-01 23:44     ` Mathieu Poirier
2021-02-02 11:10   ` Mike Leach
2021-02-02 11:10     ` Mike Leach
2021-02-02 14:36     ` Suzuki K Poulose
2021-02-02 14:36       ` Suzuki K Poulose
2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-02 17:40   ` Mathieu Poirier
2021-02-02 17:40     ` Mathieu Poirier
2021-02-02 18:03   ` Mathieu Poirier
2021-02-02 18:03     ` Mathieu Poirier
2021-02-15 14:08   ` Mike Leach
2021-02-15 14:08     ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-02 17:52   ` Mathieu Poirier
2021-02-02 17:52     ` Mathieu Poirier
2021-02-03 15:51     ` Suzuki K Poulose
2021-02-03 15:51       ` Suzuki K Poulose
2021-02-15 14:08   ` Mike Leach
2021-02-15 14:08     ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-02 18:56   ` Mathieu Poirier
2021-02-02 18:56     ` Mathieu Poirier
2021-02-02 22:50     ` Suzuki K Poulose
2021-02-02 22:50       ` Suzuki K Poulose
2021-02-15 13:21     ` Mike Leach
2021-02-15 13:21       ` Mike Leach
2021-02-15 14:08       ` Mike Leach
2021-02-15 14:08         ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-09 19:00   ` Rob Herring
2021-02-09 19:00     ` Rob Herring
2021-02-10 12:33     ` Suzuki K Poulose
2021-02-10 12:33       ` Suzuki K Poulose
2021-02-18 18:33       ` Rob Herring
2021-02-18 18:33         ` Rob Herring
2021-02-18 22:51         ` Suzuki K Poulose
2021-02-18 22:51           ` Suzuki K Poulose
2021-01-27  8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-03 19:05   ` Mathieu Poirier
2021-02-03 19:05     ` Mathieu Poirier
2021-02-03 23:36     ` Suzuki K Poulose
2021-02-03 23:36       ` Suzuki K Poulose
2021-02-15 16:27   ` Mike Leach
2021-02-15 16:27     ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-01-28  9:16   ` Suzuki K Poulose
2021-01-28  9:16     ` Suzuki K Poulose
2021-02-04 18:34     ` Mathieu Poirier
2021-02-04 18:34       ` Mathieu Poirier
2021-02-16 10:40       ` Anshuman Khandual
2021-02-16 10:40         ` Anshuman Khandual
2021-02-16 20:44         ` Mathieu Poirier
2021-02-16 20:44           ` Mathieu Poirier
2021-02-16 10:21     ` Anshuman Khandual
2021-02-16 10:21       ` Anshuman Khandual
2021-02-15 16:27   ` Mike Leach
2021-02-15 16:27     ` Mike Leach
2021-02-15 16:56     ` Mathieu Poirier
2021-02-15 16:56       ` Mathieu Poirier
2021-02-15 17:58       ` Mike Leach
2021-02-15 17:58         ` Mike Leach
2021-02-16 20:30         ` Mathieu Poirier
2021-02-16 20:30           ` Mathieu Poirier
2021-01-27  8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-01-28  9:31   ` Suzuki K Poulose
2021-01-28  9:31     ` Suzuki K Poulose
2021-01-28 17:18   ` Catalin Marinas
2021-01-28 17:18     ` Catalin Marinas
2021-02-15 18:06     ` Mike Leach
2021-02-15 18:06       ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-01-27  9:58   ` Marc Zyngier
2021-01-27  9:58     ` Marc Zyngier
2021-01-28  9:34     ` Suzuki K Poulose
2021-01-28  9:34       ` Suzuki K Poulose
2021-01-28  9:46       ` Marc Zyngier
2021-01-28  9:46         ` Marc Zyngier
2021-01-28  9:48         ` Suzuki K Poulose
2021-01-28  9:48           ` Suzuki K Poulose
2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-01-29 10:23   ` Suzuki K Poulose
2021-02-02  5:55     ` Anshuman Khandual
2021-02-02  5:55       ` Anshuman Khandual
2021-02-05 17:53   ` Mathieu Poirier
2021-02-05 17:53     ` Mathieu Poirier
2021-02-08  4:20     ` Anshuman Khandual
2021-02-08  4:20       ` Anshuman Khandual
2021-02-09 17:39     ` Mathieu Poirier
2021-02-09 17:39       ` Mathieu Poirier
2021-02-10  4:12       ` Anshuman Khandual
2021-02-10  4:12         ` Anshuman Khandual
2021-02-10 16:54         ` Mathieu Poirier
2021-02-10 16:54           ` Mathieu Poirier
2021-02-10 19:00   ` Mathieu Poirier
2021-02-10 19:00     ` Mathieu Poirier
2021-02-12  5:43     ` Anshuman Khandual
2021-02-12  5:43       ` Anshuman Khandual
2021-02-12 17:02       ` Mathieu Poirier
2021-02-12 17:02         ` Mathieu Poirier
2021-02-11 19:00   ` Mathieu Poirier
2021-02-11 19:00     ` Mathieu Poirier
2021-02-12  3:31     ` Anshuman Khandual
2021-02-12  3:31       ` Anshuman Khandual
2021-02-12 16:57       ` Mathieu Poirier [this message]
2021-02-12 16:57         ` Mathieu Poirier
2021-02-15  9:26         ` Anshuman Khandual
2021-02-15  9:26           ` Anshuman Khandual
2021-02-12 20:26   ` Mathieu Poirier
2021-02-12 20:26     ` Mathieu Poirier
2021-02-15  9:46     ` Anshuman Khandual
2021-02-15  9:46       ` Anshuman Khandual
2021-02-16  9:00       ` Mike Leach
2021-02-16  9:00         ` Mike Leach
2021-02-16  9:44         ` Anshuman Khandual
2021-02-16  9:44           ` Anshuman Khandual
2021-02-16 12:12           ` Mike Leach
2021-02-16 12:12             ` Mike Leach
2021-02-18  7:50         ` Suzuki K Poulose
2021-02-18  7:50           ` Suzuki K Poulose
2021-02-18 14:30           ` Mike Leach
2021-02-18 14:30             ` Mike Leach
2021-02-18 15:14             ` Suzuki K Poulose
2021-02-18 15:14               ` Suzuki K Poulose
2021-02-22 10:42               ` Mike Leach
2021-02-22 10:42                 ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-02-09 19:04   ` Rob Herring
2021-02-09 19:04     ` Rob Herring
2021-01-27  8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-01-27 12:51   ` Peter Zijlstra
2021-01-27 12:51     ` Peter Zijlstra
2021-02-16 10:59   ` Mike Leach
2021-02-16 10:59     ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27  8:55   ` Anshuman Khandual
2021-01-27 12:54   ` Peter Zijlstra
2021-01-27 12:54     ` Peter Zijlstra
2021-01-27 13:00     ` Al Grant
2021-01-27 13:00       ` Al Grant
2021-02-18  3:05       ` Anshuman Khandual
2021-02-18  3:05         ` Anshuman Khandual
2021-01-27 14:12     ` Suzuki K Poulose
2021-01-27 14:12       ` Suzuki K Poulose
2021-02-16 11:01   ` Mike Leach
2021-02-16 11:01     ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-01-27 18:50   ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-01 18:44   ` Mathieu Poirier
2021-02-18  4:23   ` Anshuman Khandual
2021-02-18  4:23     ` Anshuman Khandual

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210212165734.GA2692426@xps15 \
    --to=mathieu.poirier@linaro.org \
    --cc=anshuman.khandual@arm.com \
    --cc=coresight@lists.linaro.org \
    --cc=lcherian@marvell.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mike.leach@linaro.org \
    --cc=suzuki.poulose@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.