From: Mike Leach <mike.leach@linaro.org> To: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, Coresight ML <coresight@lists.linaro.org>, "Suzuki K. Poulose" <suzuki.poulose@arm.com>, Linu Cherian <lcherian@marvell.com>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver Date: Tue, 16 Feb 2021 12:12:32 +0000 [thread overview] Message-ID: <CAJ9a7VjBs_xNzPX3sbVZ2-2QUProqfKmFn9rPLavkq+B=EtHQA@mail.gmail.com> (raw) In-Reply-To: <7b20f8b3-4efa-530f-b058-1aae13e4e43e@arm.com> Hi Anshuman, On Tue, 16 Feb 2021 at 09:44, Anshuman Khandual <anshuman.khandual@arm.com> wrote: > > Hello Mike, > > On 2/16/21 2:30 PM, Mike Leach wrote: > > Hi Anshuman, > > > > There have been plenty of detailed comments so I will restrict mine to > > a few general issues:- > > > > 1) Currently there appears to be no sysfs support (I cannot see the > > MODE_SYSFS constants running alongside the MODE_PERF ones present in > > the other sink drivers). This is present on all other coresight > > devices, and must be provided for this device. It is useful for > > testing, and there are users out there who will have scripts to use > > it. It is not essential it makes it into this set, but should be a > > follow up set. > > Sure, will try and add it in a follow up series. > > > > > 2) Using FILL mode for TRBE means that the trace will by definition be > > lossy. Fill mode will halt collection without cleanly stopping and > > flushing the source. This will result in the sink missing the last of > > the data from the source as it stops. Even if taking the exception > > moves into a prohibited region there is still the possibility the last > > trace operations will not be seen. Further it is possible that the > > last few bytes of trace will be an incomplete packet, and indeed the > > start of the next buffer could contain incomplete packets too. > > Just wondering why TRBE and ETE would not sync with each other in order > for the ETE to possibly resend all the lost trace data, when the TRBE > runs out of buffer and wrappers around ? The ETE and TRBE are separate devices - there is no feedback between them. The ETE can also send to external sinks. Given the rate of trace generation, buffering enough trace in the ETE to resend is not realistic, and would be very complicated in terms of hardware. Therefore the solution is to stop the source (disable ETE or prohibit using TFR), flush (TSB CSYNC), then stop collection. A TSB CSYNC without stopping the ETE, or after TRBE has stopped collection will have no effect in terms of getting cleanly stopped trace into the buffer. > Is this ETE/TRBE behavior same > for all implementations in the FILL mode ? Just wondering. > Yes - there is nothing in either spec that would suggest otherwise. > > > > This operation differs from the other sinks which will only halt after > > the sources have stopped and the path has been flushed. This ensures > > that the latest trace is complete. The weakness with the older sinks > > is the lack of interrupt meaning buffers were frequently wrapped so > > that only the latest trace is available. > > Right. > > > > > By using TRBE WRAP mode, with a watermark as described in the TRBE > > spec, using the interrupts it is possible to approach lossless trace > > in a way that is not possible with earlier ETR/ETB. This is somethin > Using TRBTRG_EL1 as the above mentioned watermark ? > Using TRBTRG_EL1 precludes using the ETE Event triggers for activating and marking trace. It is preferable to use the write pointer offset from the initial base to allow a portion of the buffer to be filled after wrap. This a little more complex but more flexible in terms of ETE usage. > > that has been requested by partners since trace became available in > > linux systems. (There is still a possibility of loss due to filling > > the buffer completely and overflowing the watermark, but that can be > > flagged). > > > > While FILL mode trace is a good start, and suitable for some scenarios > > - WRAP mode needs implementing as well. > > I would like to understand this mechanism more. Besides how the perf > interface suppose to choose between FILL and WRAP mode ? via a new > event attribute ? > That is an open question. Event option is one possibility, configfs or compile time options are others. Probably have to look at the performance of wrap mode and decide if it could be used all the time or if FILL still has value. We are in the early days of ETE / TRBE development here. I do not think there is anything wrong with using FILL as a first step. as long as the limitations are well understood. Regards Mike > > > > 3) Padding: To be clear, it is not safe for the decoder to run off the > > end of one buffer, into the padding area and continue decoding, or > > continue through the padding into the next buffer. However I believe > > the buffer start / stop points are demarked by the aux_output_start / > > aux_output_end calls? > > Yes. > > > > > With upcoming perf decode updates this should enable the decoder to > > correctly be started and stopped on the buffer boundaries. The padding > > is there primarily to ensure that the decoder does not synchronize > > with the data stream until a genuine sync point is found. > > Right. > > > > > 4) TRBE needs to be a loadable module like the rest of coresight. > > Even though the driver has all the module constructs, the Kconfig was > missing a tristate value, which is being fixed for the next version. > > - Anshuman -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
WARNING: multiple messages have this Message-ID (diff)
From: Mike Leach <mike.leach@linaro.org> To: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>, "Suzuki K. Poulose" <suzuki.poulose@arm.com>, Coresight ML <coresight@lists.linaro.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, Linu Cherian <lcherian@marvell.com> Subject: Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver Date: Tue, 16 Feb 2021 12:12:32 +0000 [thread overview] Message-ID: <CAJ9a7VjBs_xNzPX3sbVZ2-2QUProqfKmFn9rPLavkq+B=EtHQA@mail.gmail.com> (raw) In-Reply-To: <7b20f8b3-4efa-530f-b058-1aae13e4e43e@arm.com> Hi Anshuman, On Tue, 16 Feb 2021 at 09:44, Anshuman Khandual <anshuman.khandual@arm.com> wrote: > > Hello Mike, > > On 2/16/21 2:30 PM, Mike Leach wrote: > > Hi Anshuman, > > > > There have been plenty of detailed comments so I will restrict mine to > > a few general issues:- > > > > 1) Currently there appears to be no sysfs support (I cannot see the > > MODE_SYSFS constants running alongside the MODE_PERF ones present in > > the other sink drivers). This is present on all other coresight > > devices, and must be provided for this device. It is useful for > > testing, and there are users out there who will have scripts to use > > it. It is not essential it makes it into this set, but should be a > > follow up set. > > Sure, will try and add it in a follow up series. > > > > > 2) Using FILL mode for TRBE means that the trace will by definition be > > lossy. Fill mode will halt collection without cleanly stopping and > > flushing the source. This will result in the sink missing the last of > > the data from the source as it stops. Even if taking the exception > > moves into a prohibited region there is still the possibility the last > > trace operations will not be seen. Further it is possible that the > > last few bytes of trace will be an incomplete packet, and indeed the > > start of the next buffer could contain incomplete packets too. > > Just wondering why TRBE and ETE would not sync with each other in order > for the ETE to possibly resend all the lost trace data, when the TRBE > runs out of buffer and wrappers around ? The ETE and TRBE are separate devices - there is no feedback between them. The ETE can also send to external sinks. Given the rate of trace generation, buffering enough trace in the ETE to resend is not realistic, and would be very complicated in terms of hardware. Therefore the solution is to stop the source (disable ETE or prohibit using TFR), flush (TSB CSYNC), then stop collection. A TSB CSYNC without stopping the ETE, or after TRBE has stopped collection will have no effect in terms of getting cleanly stopped trace into the buffer. > Is this ETE/TRBE behavior same > for all implementations in the FILL mode ? Just wondering. > Yes - there is nothing in either spec that would suggest otherwise. > > > > This operation differs from the other sinks which will only halt after > > the sources have stopped and the path has been flushed. This ensures > > that the latest trace is complete. The weakness with the older sinks > > is the lack of interrupt meaning buffers were frequently wrapped so > > that only the latest trace is available. > > Right. > > > > > By using TRBE WRAP mode, with a watermark as described in the TRBE > > spec, using the interrupts it is possible to approach lossless trace > > in a way that is not possible with earlier ETR/ETB. This is somethin > Using TRBTRG_EL1 as the above mentioned watermark ? > Using TRBTRG_EL1 precludes using the ETE Event triggers for activating and marking trace. It is preferable to use the write pointer offset from the initial base to allow a portion of the buffer to be filled after wrap. This a little more complex but more flexible in terms of ETE usage. > > that has been requested by partners since trace became available in > > linux systems. (There is still a possibility of loss due to filling > > the buffer completely and overflowing the watermark, but that can be > > flagged). > > > > While FILL mode trace is a good start, and suitable for some scenarios > > - WRAP mode needs implementing as well. > > I would like to understand this mechanism more. Besides how the perf > interface suppose to choose between FILL and WRAP mode ? via a new > event attribute ? > That is an open question. Event option is one possibility, configfs or compile time options are others. Probably have to look at the performance of wrap mode and decide if it could be used all the time or if FILL still has value. We are in the early days of ETE / TRBE development here. I do not think there is anything wrong with using FILL as a first step. as long as the limitations are well understood. Regards Mike > > > > 3) Padding: To be clear, it is not safe for the decoder to run off the > > end of one buffer, into the padding area and continue decoding, or > > continue through the padding into the next buffer. However I believe > > the buffer start / stop points are demarked by the aux_output_start / > > aux_output_end calls? > > Yes. > > > > > With upcoming perf decode updates this should enable the decoder to > > correctly be started and stopped on the buffer boundaries. The padding > > is there primarily to ensure that the decoder does not synchronize > > with the data stream until a genuine sync point is found. > > Right. > > > > > 4) TRBE needs to be a loadable module like the rest of coresight. > > Even though the driver has all the module constructs, the Kconfig was > missing a tristate value, which is being fixed for the next version. > > - Anshuman -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-16 12:13 UTC|newest] Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-01 23:17 ` Mathieu Poirier 2021-02-01 23:17 ` Mathieu Poirier 2021-02-02 9:42 ` Suzuki K Poulose 2021-02-02 9:42 ` Suzuki K Poulose 2021-02-02 16:33 ` Mike Leach 2021-02-02 16:33 ` Mike Leach 2021-02-02 22:41 ` Suzuki K Poulose 2021-02-02 22:41 ` Suzuki K Poulose 2021-02-04 12:27 ` Mike Leach 2021-02-04 12:27 ` Mike Leach 2021-02-02 16:37 ` Mathieu Poirier 2021-02-02 16:37 ` Mathieu Poirier 2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-01 23:44 ` Mathieu Poirier 2021-02-01 23:44 ` Mathieu Poirier 2021-02-02 11:10 ` Mike Leach 2021-02-02 11:10 ` Mike Leach 2021-02-02 14:36 ` Suzuki K Poulose 2021-02-02 14:36 ` Suzuki K Poulose 2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-02 17:40 ` Mathieu Poirier 2021-02-02 17:40 ` Mathieu Poirier 2021-02-02 18:03 ` Mathieu Poirier 2021-02-02 18:03 ` Mathieu Poirier 2021-02-15 14:08 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-02 17:52 ` Mathieu Poirier 2021-02-02 17:52 ` Mathieu Poirier 2021-02-03 15:51 ` Suzuki K Poulose 2021-02-03 15:51 ` Suzuki K Poulose 2021-02-15 14:08 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-02 18:56 ` Mathieu Poirier 2021-02-02 18:56 ` Mathieu Poirier 2021-02-02 22:50 ` Suzuki K Poulose 2021-02-02 22:50 ` Suzuki K Poulose 2021-02-15 13:21 ` Mike Leach 2021-02-15 13:21 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-02-15 14:08 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-09 19:00 ` Rob Herring 2021-02-09 19:00 ` Rob Herring 2021-02-10 12:33 ` Suzuki K Poulose 2021-02-10 12:33 ` Suzuki K Poulose 2021-02-18 18:33 ` Rob Herring 2021-02-18 18:33 ` Rob Herring 2021-02-18 22:51 ` Suzuki K Poulose 2021-02-18 22:51 ` Suzuki K Poulose 2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-03 19:05 ` Mathieu Poirier 2021-02-03 19:05 ` Mathieu Poirier 2021-02-03 23:36 ` Suzuki K Poulose 2021-02-03 23:36 ` Suzuki K Poulose 2021-02-15 16:27 ` Mike Leach 2021-02-15 16:27 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-28 9:16 ` Suzuki K Poulose 2021-01-28 9:16 ` Suzuki K Poulose 2021-02-04 18:34 ` Mathieu Poirier 2021-02-04 18:34 ` Mathieu Poirier 2021-02-16 10:40 ` Anshuman Khandual 2021-02-16 10:40 ` Anshuman Khandual 2021-02-16 20:44 ` Mathieu Poirier 2021-02-16 20:44 ` Mathieu Poirier 2021-02-16 10:21 ` Anshuman Khandual 2021-02-16 10:21 ` Anshuman Khandual 2021-02-15 16:27 ` Mike Leach 2021-02-15 16:27 ` Mike Leach 2021-02-15 16:56 ` Mathieu Poirier 2021-02-15 16:56 ` Mathieu Poirier 2021-02-15 17:58 ` Mike Leach 2021-02-15 17:58 ` Mike Leach 2021-02-16 20:30 ` Mathieu Poirier 2021-02-16 20:30 ` Mathieu Poirier 2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-28 9:31 ` Suzuki K Poulose 2021-01-28 9:31 ` Suzuki K Poulose 2021-01-28 17:18 ` Catalin Marinas 2021-01-28 17:18 ` Catalin Marinas 2021-02-15 18:06 ` Mike Leach 2021-02-15 18:06 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 9:58 ` Marc Zyngier 2021-01-27 9:58 ` Marc Zyngier 2021-01-28 9:34 ` Suzuki K Poulose 2021-01-28 9:34 ` Suzuki K Poulose 2021-01-28 9:46 ` Marc Zyngier 2021-01-28 9:46 ` Marc Zyngier 2021-01-28 9:48 ` Suzuki K Poulose 2021-01-28 9:48 ` Suzuki K Poulose 2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-29 10:23 ` Suzuki K Poulose 2021-02-02 5:55 ` Anshuman Khandual 2021-02-02 5:55 ` Anshuman Khandual 2021-02-05 17:53 ` Mathieu Poirier 2021-02-05 17:53 ` Mathieu Poirier 2021-02-08 4:20 ` Anshuman Khandual 2021-02-08 4:20 ` Anshuman Khandual 2021-02-09 17:39 ` Mathieu Poirier 2021-02-09 17:39 ` Mathieu Poirier 2021-02-10 4:12 ` Anshuman Khandual 2021-02-10 4:12 ` Anshuman Khandual 2021-02-10 16:54 ` Mathieu Poirier 2021-02-10 16:54 ` Mathieu Poirier 2021-02-10 19:00 ` Mathieu Poirier 2021-02-10 19:00 ` Mathieu Poirier 2021-02-12 5:43 ` Anshuman Khandual 2021-02-12 5:43 ` Anshuman Khandual 2021-02-12 17:02 ` Mathieu Poirier 2021-02-12 17:02 ` Mathieu Poirier 2021-02-11 19:00 ` Mathieu Poirier 2021-02-11 19:00 ` Mathieu Poirier 2021-02-12 3:31 ` Anshuman Khandual 2021-02-12 3:31 ` Anshuman Khandual 2021-02-12 16:57 ` Mathieu Poirier 2021-02-12 16:57 ` Mathieu Poirier 2021-02-15 9:26 ` Anshuman Khandual 2021-02-15 9:26 ` Anshuman Khandual 2021-02-12 20:26 ` Mathieu Poirier 2021-02-12 20:26 ` Mathieu Poirier 2021-02-15 9:46 ` Anshuman Khandual 2021-02-15 9:46 ` Anshuman Khandual 2021-02-16 9:00 ` Mike Leach 2021-02-16 9:00 ` Mike Leach 2021-02-16 9:44 ` Anshuman Khandual 2021-02-16 9:44 ` Anshuman Khandual 2021-02-16 12:12 ` Mike Leach [this message] 2021-02-16 12:12 ` Mike Leach 2021-02-18 7:50 ` Suzuki K Poulose 2021-02-18 7:50 ` Suzuki K Poulose 2021-02-18 14:30 ` Mike Leach 2021-02-18 14:30 ` Mike Leach 2021-02-18 15:14 ` Suzuki K Poulose 2021-02-18 15:14 ` Suzuki K Poulose 2021-02-22 10:42 ` Mike Leach 2021-02-22 10:42 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-02-09 19:04 ` Rob Herring 2021-02-09 19:04 ` Rob Herring 2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 12:51 ` Peter Zijlstra 2021-01-27 12:51 ` Peter Zijlstra 2021-02-16 10:59 ` Mike Leach 2021-02-16 10:59 ` Mike Leach 2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual 2021-01-27 8:55 ` Anshuman Khandual 2021-01-27 12:54 ` Peter Zijlstra 2021-01-27 12:54 ` Peter Zijlstra 2021-01-27 13:00 ` Al Grant 2021-01-27 13:00 ` Al Grant 2021-02-18 3:05 ` Anshuman Khandual 2021-02-18 3:05 ` Anshuman Khandual 2021-01-27 14:12 ` Suzuki K Poulose 2021-01-27 14:12 ` Suzuki K Poulose 2021-02-16 11:01 ` Mike Leach 2021-02-16 11:01 ` Mike Leach 2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier 2021-01-27 18:50 ` Mathieu Poirier 2021-02-01 18:44 ` Mathieu Poirier 2021-02-01 18:44 ` Mathieu Poirier 2021-02-18 4:23 ` Anshuman Khandual 2021-02-18 4:23 ` Anshuman Khandual
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to='CAJ9a7VjBs_xNzPX3sbVZ2-2QUProqfKmFn9rPLavkq+B=EtHQA@mail.gmail.com' \ --to=mike.leach@linaro.org \ --cc=anshuman.khandual@arm.com \ --cc=coresight@lists.linaro.org \ --cc=lcherian@marvell.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mathieu.poirier@linaro.org \ --cc=suzuki.poulose@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.