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* [PULL 00/19] riscv-to-apply queue
@ 2021-02-18  1:59 Alistair Francis
  2021-02-18  1:59 ` [PULL 01/19] target/riscv: Declare csr_ops[] with a known size Alistair Francis
                   ` (19 more replies)
  0 siblings, 20 replies; 27+ messages in thread
From: Alistair Francis @ 2021-02-18  1:59 UTC (permalink / raw)
  To: peter.maydell; +Cc: alistair23, Alistair Francis, qemu-devel

The following changes since commit 1af5629673bb5c1592d993f9fb6119a62845f576:

  Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210216' into staging (2021-02-17 14:44:18 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210217-1

for you to fetch changes up to d0867d2dad4125d2295b28d6f91fa49cf034ffd2:

  hw/riscv: virt: Map high mmio for PCIe (2021-02-17 17:47:19 -0800)

----------------------------------------------------------------
RISC-V PR for 6.0

This PR is a collection of RISC-V patches:
 - Improvements to SiFive U OTP
 - Upgrade OpenSBI to v0.9
 - Support the QMP dump-guest-memory
 - Add support for the SiFive SPI controller (sifive_u)
 - Initial RISC-V system documentation
 - A fix for the Goldfish RTC
 - MAINTAINERS updates
 - Support for high PCIe memory in the virt machine

----------------------------------------------------------------
Alistair Francis (1):
      MAINTAINERS: Add a SiFive machine section

Bin Meng (16):
      target/riscv: Declare csr_ops[] with a known size
      hw/misc: sifive_u_otp: Use error_report() when block operation fails
      roms/opensbi: Upgrade from v0.8 to v0.9
      hw/block: m25p80: Add ISSI SPI flash support
      hw/block: m25p80: Add various ISSI flash information
      hw/ssi: Add SiFive SPI controller support
      hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
      hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
      hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
      docs/system: Sort targets in alphabetical order
      docs/system: Add RISC-V documentation
      docs/system: riscv: Add documentation for sifive_u machine
      hw/riscv: Drop 'struct MemmapEntry'
      hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
      hw/riscv: virt: Limit RAM size in a 32-bit system
      hw/riscv: virt: Map high mmio for PCIe

Laurent Vivier (1):
      goldfish_rtc: re-arm the alarm after migration

Yifei Jiang (1):
      target-riscv: support QMP dump-guest-memory

 docs/system/riscv/sifive_u.rst                 | 336 +++++++++++++++++++++++
 docs/system/target-riscv.rst                   |  72 +++++
 docs/system/targets.rst                        |  20 +-
 include/hw/riscv/sifive_u.h                    |   9 +-
 include/hw/ssi/sifive_spi.h                    |  47 ++++
 target/riscv/cpu.h                             |   6 +-
 target/riscv/cpu_bits.h                        |   1 +
 hw/block/m25p80.c                              |  57 +++-
 hw/misc/sifive_u_otp.c                         |  13 +-
 hw/riscv/microchip_pfsoc.c                     |   9 +-
 hw/riscv/opentitan.c                           |   9 +-
 hw/riscv/sifive_e.c                            |   9 +-
 hw/riscv/sifive_u.c                            | 102 ++++++-
 hw/riscv/spike.c                               |   9 +-
 hw/riscv/virt.c                                |  72 +++--
 hw/rtc/goldfish_rtc.c                          |   2 +
 hw/ssi/sifive_spi.c                            | 358 +++++++++++++++++++++++++
 target/riscv/arch_dump.c                       | 202 ++++++++++++++
 target/riscv/cpu.c                             |   2 +
 MAINTAINERS                                    |   9 +
 hw/riscv/Kconfig                               |   3 +
 hw/ssi/Kconfig                                 |   4 +
 hw/ssi/meson.build                             |   1 +
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 62144 -> 78680 bytes
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 558668 -> 727464 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 70792 -> 75096 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 620424 -> 781264 bytes
 roms/opensbi                                   |   2 +-
 target/riscv/meson.build                       |   1 +
 29 files changed, 1290 insertions(+), 65 deletions(-)
 create mode 100644 docs/system/riscv/sifive_u.rst
 create mode 100644 docs/system/target-riscv.rst
 create mode 100644 include/hw/ssi/sifive_spi.h
 create mode 100644 hw/ssi/sifive_spi.c
 create mode 100644 target/riscv/arch_dump.c


^ permalink raw reply	[flat|nested] 27+ messages in thread
end of thread, other threads:[~2021-02-19 16:25 UTC | newest]

Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-18  1:59 [PULL 00/19] riscv-to-apply queue Alistair Francis
2021-02-18  1:59 ` [PULL 01/19] target/riscv: Declare csr_ops[] with a known size Alistair Francis
2021-02-18  1:59 ` [PULL 02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails Alistair Francis
2021-02-18  1:59 ` [PULL 03/19] roms/opensbi: Upgrade from v0.8 to v0.9 Alistair Francis
2021-02-18  1:59 ` [PULL 04/19] target-riscv: support QMP dump-guest-memory Alistair Francis
2021-02-18  1:59 ` [PULL 05/19] hw/block: m25p80: Add ISSI SPI flash support Alistair Francis
2021-02-18  1:59 ` [PULL 06/19] hw/block: m25p80: Add various ISSI flash information Alistair Francis
2021-02-18  1:59 ` [PULL 07/19] hw/ssi: Add SiFive SPI controller support Alistair Francis
2021-02-18  1:59 ` [PULL 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Alistair Francis
2021-02-18  1:59 ` [PULL 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Alistair Francis
2021-02-18  1:59 ` [PULL 10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Alistair Francis
2021-02-18  1:59 ` [PULL 11/19] docs/system: Sort targets in alphabetical order Alistair Francis
2021-02-18  1:59 ` [PULL 12/19] docs/system: Add RISC-V documentation Alistair Francis
2021-02-18  1:59 ` [PULL 13/19] docs/system: riscv: Add documentation for sifive_u machine Alistair Francis
2021-02-18  1:59 ` [PULL 14/19] goldfish_rtc: re-arm the alarm after migration Alistair Francis
2021-02-18  1:59 ` [PULL 15/19] MAINTAINERS: Add a SiFive machine section Alistair Francis
2021-02-18  1:59 ` [PULL 16/19] hw/riscv: Drop 'struct MemmapEntry' Alistair Francis
2021-02-18  1:59 ` [PULL 17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Alistair Francis
2021-02-18  1:59 ` [PULL 18/19] hw/riscv: virt: Limit RAM size in a 32-bit system Alistair Francis
2021-02-18  1:59 ` [PULL 19/19] hw/riscv: virt: Map high mmio for PCIe Alistair Francis
2021-02-18 13:25 ` [PULL 00/19] riscv-to-apply queue Peter Maydell
2021-02-18 14:07   ` Bin Meng
2021-02-18 14:22     ` Peter Maydell
2021-02-19 12:36       ` Bin Meng
2021-02-19 13:31       ` Philippe Mathieu-Daudé
2021-02-19 13:40         ` Peter Maydell
2021-02-19 16:12         ` Richard W.M. Jones

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