From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@intel.com>, Swati Sharma <swati2.sharma@intel.com>, dri-devel@lists.freedesktop.org Subject: [PATCH 17/19] drm/i915/dg1: Double memory bandwidth available Date: Mon, 12 Apr 2021 10:05:24 +0100 [thread overview] Message-ID: <20210412090526.30547-18-matthew.auld@intel.com> (raw) In-Reply-To: <20210412090526.30547-1-matthew.auld@intel.com> From: Clint Taylor <clinton.a.taylor@intel.com> Use MCHBAR Gear_type information to compute memory bandwidth available during MCHBAR calculations. v2 by Jani: - switch to intel_uncore_read/intel_uncore_write Tested-by: Swati Sharma <swati2.sharma@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 99cae0dc0ca2..6c02bd52ce45 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -41,6 +41,9 @@ struct intel_qgv_info { #define DG1_DRAM_T_RP_MASK (0x7F << 0) #define DG1_DRAM_T_RP_SHIFT 0 +#define ICL_GEAR_TYPE_MASK (0x01 << 16) +#define ICL_GEAR_TYPE_SHIFT 16 + static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, struct intel_qgv_point *sp, int point) @@ -55,6 +58,11 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, else dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ sp->dclk = dclk_ratio * dclk_reference; + + val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); + if ((val & ICL_GEAR_TYPE_MASK) >> ICL_GEAR_TYPE_SHIFT) + sp->dclk *= 2; + if (sp->dclk == 0) return -EINVAL; -- 2.26.3 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula <jani.nikula@intel.com>, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 17/19] drm/i915/dg1: Double memory bandwidth available Date: Mon, 12 Apr 2021 10:05:24 +0100 [thread overview] Message-ID: <20210412090526.30547-18-matthew.auld@intel.com> (raw) In-Reply-To: <20210412090526.30547-1-matthew.auld@intel.com> From: Clint Taylor <clinton.a.taylor@intel.com> Use MCHBAR Gear_type information to compute memory bandwidth available during MCHBAR calculations. v2 by Jani: - switch to intel_uncore_read/intel_uncore_write Tested-by: Swati Sharma <swati2.sharma@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 99cae0dc0ca2..6c02bd52ce45 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -41,6 +41,9 @@ struct intel_qgv_info { #define DG1_DRAM_T_RP_MASK (0x7F << 0) #define DG1_DRAM_T_RP_SHIFT 0 +#define ICL_GEAR_TYPE_MASK (0x01 << 16) +#define ICL_GEAR_TYPE_SHIFT 16 + static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, struct intel_qgv_point *sp, int point) @@ -55,6 +58,11 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv, else dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ sp->dclk = dclk_ratio * dclk_reference; + + val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); + if ((val & ICL_GEAR_TYPE_MASK) >> ICL_GEAR_TYPE_SHIFT) + sp->dclk *= 2; + if (sp->dclk == 0) return -EINVAL; -- 2.26.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-04-12 9:10 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-12 9:05 [PATCH 00/19] More DG1 enabling Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 01/19] drm/i915/gt: Skip aperture remapping selftest where there is no aperture Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 14:48 ` Daniel Vetter 2021-04-12 14:48 ` Daniel Vetter 2021-04-12 9:05 ` [PATCH 02/19] drm/i915/selftests: Only query RAPL for integrated power measurements Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 03/19] drm/i915: Create stolen memory region from local memory Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:01 ` Tvrtko Ursulin 2021-04-14 15:01 ` Tvrtko Ursulin 2021-04-16 15:04 ` Matthew Auld 2021-04-16 15:04 ` Matthew Auld 2021-04-19 14:15 ` Tvrtko Ursulin 2021-04-19 14:15 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 04/19] drm/i915/stolen: treat stolen local as normal " Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:06 ` Tvrtko Ursulin 2021-04-14 15:06 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 05/19] drm/i915/stolen: enforce the min_page_size contract Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:07 ` Tvrtko Ursulin 2021-04-14 15:07 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 06/19] drm/i915/stolen: pass the allocation flags Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:09 ` Tvrtko Ursulin 2021-04-14 15:09 ` Tvrtko Ursulin 2021-04-16 13:53 ` Matthew Auld 2021-04-16 13:53 ` Matthew Auld 2021-04-12 9:05 ` [PATCH 07/19] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 15:00 ` Daniel Vetter 2021-04-12 15:00 ` [Intel-gfx] " Daniel Vetter 2021-04-12 9:05 ` [PATCH 08/19] drm/i915: Return error value when bo not in LMEM for discrete Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:16 ` Tvrtko Ursulin 2021-04-14 15:16 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 09/19] drm/i915/lmem: Fail driver init if LMEM training failed Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 10/19] drm/i915/dg1: Fix mapping type for default state object Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 11/19] drm/i915: Update the helper to set correct mapping Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:22 ` Tvrtko Ursulin 2021-04-14 15:22 ` Tvrtko Ursulin 2021-04-14 16:20 ` Matthew Auld 2021-04-14 16:20 ` Matthew Auld 2021-04-15 8:20 ` Tvrtko Ursulin 2021-04-15 8:20 ` Tvrtko Ursulin 2021-04-15 9:23 ` Matthew Auld 2021-04-15 9:23 ` Matthew Auld 2021-04-15 11:05 ` Tvrtko Ursulin 2021-04-15 11:05 ` Tvrtko Ursulin 2021-04-19 11:30 ` Matthew Auld 2021-04-19 11:30 ` Matthew Auld 2021-04-19 14:07 ` Tvrtko Ursulin 2021-04-19 14:07 ` Tvrtko Ursulin 2021-04-19 14:37 ` Matthew Auld 2021-04-19 14:37 ` Matthew Auld 2021-04-19 15:01 ` Tvrtko Ursulin 2021-04-19 15:01 ` Tvrtko Ursulin 2021-04-21 11:42 ` Matthew Auld 2021-04-21 11:42 ` Matthew Auld 2021-04-21 15:41 ` Tvrtko Ursulin 2021-04-21 15:41 ` Tvrtko Ursulin 2021-04-21 19:13 ` Matthew Auld 2021-04-21 19:13 ` Matthew Auld 2021-04-26 8:57 ` Matthew Auld 2021-04-26 8:57 ` Matthew Auld 2021-04-26 9:21 ` Tvrtko Ursulin 2021-04-26 9:21 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 12/19] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:33 ` Tvrtko Ursulin 2021-04-14 15:33 ` Tvrtko Ursulin 2021-04-16 14:25 ` Matthew Auld 2021-04-16 14:25 ` Matthew Auld 2021-04-19 14:16 ` Tvrtko Ursulin 2021-04-19 14:16 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 13/19] drm/i915/dg1: Read OPROM via SPI controller Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-09-17 23:29 ` Lucas De Marchi 2021-04-12 9:05 ` [PATCH 14/19] drm/i915/oprom: Basic sanitization Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` [PATCH] drm/i915/oprom: fix memdup.cocci warnings kernel test robot 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` [Intel-gfx] " kernel test robot 2021-05-17 11:57 ` [Intel-gfx] [PATCH 14/19] drm/i915/oprom: Basic sanitization Jani Nikula 2021-05-17 11:57 ` Jani Nikula 2021-09-18 4:30 ` Lucas De Marchi 2021-09-20 7:41 ` Jani Nikula 2021-09-20 8:04 ` Gupta, Anshuman 2021-09-20 8:04 ` Gupta, Anshuman 2021-09-20 8:43 ` Jani Nikula 2021-09-20 8:43 ` Jani Nikula 2021-09-22 21:53 ` Lucas De Marchi 2021-04-12 9:05 ` [PATCH 15/19] drm/i915: WA for zero memory channel Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 16:57 ` Souza, Jose 2021-04-12 16:57 ` [Intel-gfx] " Souza, Jose 2021-04-12 9:05 ` [PATCH 16/19] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` Matthew Auld [this message] 2021-04-12 9:05 ` [Intel-gfx] [PATCH 17/19] drm/i915/dg1: Double memory bandwidth available Matthew Auld 2021-04-12 9:05 ` [PATCH 18/19] drm/i915/gtt: map the PD up front Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 15:17 ` Daniel Vetter 2021-04-12 15:17 ` Daniel Vetter 2021-04-12 16:01 ` Jani Nikula 2021-04-12 16:01 ` Jani Nikula 2021-04-12 16:36 ` Daniel Vetter 2021-04-12 16:36 ` Daniel Vetter 2021-04-12 16:08 ` Matthew Auld 2021-04-12 16:08 ` Matthew Auld 2021-04-12 17:00 ` Daniel Vetter 2021-04-12 17:00 ` Daniel Vetter 2021-04-13 9:28 ` Matthew Auld 2021-04-13 9:28 ` Matthew Auld 2021-04-13 10:18 ` Daniel Vetter 2021-04-13 10:18 ` Daniel Vetter 2021-04-12 9:05 ` [PATCH 19/19] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:37 ` Tvrtko Ursulin 2021-04-14 15:37 ` Tvrtko Ursulin 2021-04-12 11:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More DG1 enabling Patchwork 2021-04-12 11:12 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2021-04-12 11:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-04-12 13:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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