From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 19/19] drm/i915/gtt/dgfx: place the PD in LMEM Date: Wed, 14 Apr 2021 16:37:11 +0100 [thread overview] Message-ID: <eab41d73-598b-c95d-4bc3-ca451f013ddf@linux.intel.com> (raw) In-Reply-To: <20210412090526.30547-20-matthew.auld@intel.com> On 12/04/2021 10:05, Matthew Auld wrote: > It's a requirement that for dgfx we place all the paging structures in > device local-memory. > > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 ++++- > drivers/gpu/drm/i915/gt/intel_gtt.c | 27 +++++++++++++++++++++++++-- > drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + > 3 files changed, 30 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index f83496836f0f..11fb5df45a0f 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -712,7 +712,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt) > */ > ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12); > > - ppgtt->vm.alloc_pt_dma = alloc_pt_dma; > + if (HAS_LMEM(gt->i915)) > + ppgtt->vm.alloc_pt_dma = alloc_pt_lmem; > + else > + ppgtt->vm.alloc_pt_dma = alloc_pt_dma; > > err = gen8_init_scratch(&ppgtt->vm); > if (err) > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c > index d386b89e2758..1eeeab45445c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > @@ -7,10 +7,23 @@ > > #include <linux/fault-inject.h> > > +#include "gem/i915_gem_lmem.h" > #include "i915_trace.h" > #include "intel_gt.h" > #include "intel_gtt.h" > > +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz) > +{ > + struct drm_i915_gem_object *obj; > + > + obj = i915_gem_object_create_lmem(vm->i915, sz, 0); > + > + /* ensure all dma objects have the same reservation class */ > + if (!IS_ERR(obj)) > + obj->base.resv = &vm->resv; > + return obj; > +} > + > struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) > { > struct drm_i915_gem_object *obj; > @@ -27,9 +40,14 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) > > int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) > { > + enum i915_map_type type; > void *vaddr; > > - vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB); > + type = I915_MAP_WB; > + if (i915_gem_object_is_lmem(obj)) > + type = I915_MAP_WC; Not trusting the "always coherent" helper from earlier in the series? Regards, Tvrtko > + > + vaddr = i915_gem_object_pin_map_unlocked(obj, type); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > > @@ -39,9 +57,14 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) > > int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) > { > + enum i915_map_type type; > void *vaddr; > > - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); > + type = I915_MAP_WB; > + if (i915_gem_object_is_lmem(obj)) > + type = I915_MAP_WC; > + > + vaddr = i915_gem_object_pin_map(obj, type); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index 40e486704558..44ce27c51631 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -527,6 +527,7 @@ int setup_scratch_page(struct i915_address_space *vm); > void free_scratch(struct i915_address_space *vm); > > struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); > +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); > struct i915_page_table *alloc_pt(struct i915_address_space *vm); > struct i915_page_directory *alloc_pd(struct i915_address_space *vm); > struct i915_page_directory *__alloc_pd(int npde); > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 19/19] drm/i915/gtt/dgfx: place the PD in LMEM Date: Wed, 14 Apr 2021 16:37:11 +0100 [thread overview] Message-ID: <eab41d73-598b-c95d-4bc3-ca451f013ddf@linux.intel.com> (raw) In-Reply-To: <20210412090526.30547-20-matthew.auld@intel.com> On 12/04/2021 10:05, Matthew Auld wrote: > It's a requirement that for dgfx we place all the paging structures in > device local-memory. > > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > --- > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 ++++- > drivers/gpu/drm/i915/gt/intel_gtt.c | 27 +++++++++++++++++++++++++-- > drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + > 3 files changed, 30 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > index f83496836f0f..11fb5df45a0f 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c > @@ -712,7 +712,10 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt) > */ > ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12); > > - ppgtt->vm.alloc_pt_dma = alloc_pt_dma; > + if (HAS_LMEM(gt->i915)) > + ppgtt->vm.alloc_pt_dma = alloc_pt_lmem; > + else > + ppgtt->vm.alloc_pt_dma = alloc_pt_dma; > > err = gen8_init_scratch(&ppgtt->vm); > if (err) > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c > index d386b89e2758..1eeeab45445c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c > @@ -7,10 +7,23 @@ > > #include <linux/fault-inject.h> > > +#include "gem/i915_gem_lmem.h" > #include "i915_trace.h" > #include "intel_gt.h" > #include "intel_gtt.h" > > +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz) > +{ > + struct drm_i915_gem_object *obj; > + > + obj = i915_gem_object_create_lmem(vm->i915, sz, 0); > + > + /* ensure all dma objects have the same reservation class */ > + if (!IS_ERR(obj)) > + obj->base.resv = &vm->resv; > + return obj; > +} > + > struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) > { > struct drm_i915_gem_object *obj; > @@ -27,9 +40,14 @@ struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) > > int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) > { > + enum i915_map_type type; > void *vaddr; > > - vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB); > + type = I915_MAP_WB; > + if (i915_gem_object_is_lmem(obj)) > + type = I915_MAP_WC; Not trusting the "always coherent" helper from earlier in the series? Regards, Tvrtko > + > + vaddr = i915_gem_object_pin_map_unlocked(obj, type); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > > @@ -39,9 +57,14 @@ int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) > > int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) > { > + enum i915_map_type type; > void *vaddr; > > - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); > + type = I915_MAP_WB; > + if (i915_gem_object_is_lmem(obj)) > + type = I915_MAP_WC; > + > + vaddr = i915_gem_object_pin_map(obj, type); > if (IS_ERR(vaddr)) > return PTR_ERR(vaddr); > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h > index 40e486704558..44ce27c51631 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h > @@ -527,6 +527,7 @@ int setup_scratch_page(struct i915_address_space *vm); > void free_scratch(struct i915_address_space *vm); > > struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); > +struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz); > struct i915_page_table *alloc_pt(struct i915_address_space *vm); > struct i915_page_directory *alloc_pd(struct i915_address_space *vm); > struct i915_page_directory *__alloc_pd(int npde); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-04-14 15:37 UTC|newest] Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-12 9:05 [PATCH 00/19] More DG1 enabling Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 01/19] drm/i915/gt: Skip aperture remapping selftest where there is no aperture Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 14:48 ` Daniel Vetter 2021-04-12 14:48 ` Daniel Vetter 2021-04-12 9:05 ` [PATCH 02/19] drm/i915/selftests: Only query RAPL for integrated power measurements Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 03/19] drm/i915: Create stolen memory region from local memory Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:01 ` Tvrtko Ursulin 2021-04-14 15:01 ` Tvrtko Ursulin 2021-04-16 15:04 ` Matthew Auld 2021-04-16 15:04 ` Matthew Auld 2021-04-19 14:15 ` Tvrtko Ursulin 2021-04-19 14:15 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 04/19] drm/i915/stolen: treat stolen local as normal " Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:06 ` Tvrtko Ursulin 2021-04-14 15:06 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 05/19] drm/i915/stolen: enforce the min_page_size contract Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:07 ` Tvrtko Ursulin 2021-04-14 15:07 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 06/19] drm/i915/stolen: pass the allocation flags Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:09 ` Tvrtko Ursulin 2021-04-14 15:09 ` Tvrtko Ursulin 2021-04-16 13:53 ` Matthew Auld 2021-04-16 13:53 ` Matthew Auld 2021-04-12 9:05 ` [PATCH 07/19] drm/i915/fbdev: Use lmem physical addresses for fb_mmap() on discrete Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 15:00 ` Daniel Vetter 2021-04-12 15:00 ` [Intel-gfx] " Daniel Vetter 2021-04-12 9:05 ` [PATCH 08/19] drm/i915: Return error value when bo not in LMEM for discrete Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:16 ` Tvrtko Ursulin 2021-04-14 15:16 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 09/19] drm/i915/lmem: Fail driver init if LMEM training failed Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 10/19] drm/i915/dg1: Fix mapping type for default state object Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 11/19] drm/i915: Update the helper to set correct mapping Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:22 ` Tvrtko Ursulin 2021-04-14 15:22 ` Tvrtko Ursulin 2021-04-14 16:20 ` Matthew Auld 2021-04-14 16:20 ` Matthew Auld 2021-04-15 8:20 ` Tvrtko Ursulin 2021-04-15 8:20 ` Tvrtko Ursulin 2021-04-15 9:23 ` Matthew Auld 2021-04-15 9:23 ` Matthew Auld 2021-04-15 11:05 ` Tvrtko Ursulin 2021-04-15 11:05 ` Tvrtko Ursulin 2021-04-19 11:30 ` Matthew Auld 2021-04-19 11:30 ` Matthew Auld 2021-04-19 14:07 ` Tvrtko Ursulin 2021-04-19 14:07 ` Tvrtko Ursulin 2021-04-19 14:37 ` Matthew Auld 2021-04-19 14:37 ` Matthew Auld 2021-04-19 15:01 ` Tvrtko Ursulin 2021-04-19 15:01 ` Tvrtko Ursulin 2021-04-21 11:42 ` Matthew Auld 2021-04-21 11:42 ` Matthew Auld 2021-04-21 15:41 ` Tvrtko Ursulin 2021-04-21 15:41 ` Tvrtko Ursulin 2021-04-21 19:13 ` Matthew Auld 2021-04-21 19:13 ` Matthew Auld 2021-04-26 8:57 ` Matthew Auld 2021-04-26 8:57 ` Matthew Auld 2021-04-26 9:21 ` Tvrtko Ursulin 2021-04-26 9:21 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 12/19] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:33 ` Tvrtko Ursulin 2021-04-14 15:33 ` Tvrtko Ursulin 2021-04-16 14:25 ` Matthew Auld 2021-04-16 14:25 ` Matthew Auld 2021-04-19 14:16 ` Tvrtko Ursulin 2021-04-19 14:16 ` Tvrtko Ursulin 2021-04-12 9:05 ` [PATCH 13/19] drm/i915/dg1: Read OPROM via SPI controller Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-09-17 23:29 ` Lucas De Marchi 2021-04-12 9:05 ` [PATCH 14/19] drm/i915/oprom: Basic sanitization Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` [PATCH] drm/i915/oprom: fix memdup.cocci warnings kernel test robot 2021-04-12 22:36 ` kernel test robot 2021-04-12 22:36 ` [Intel-gfx] " kernel test robot 2021-05-17 11:57 ` [Intel-gfx] [PATCH 14/19] drm/i915/oprom: Basic sanitization Jani Nikula 2021-05-17 11:57 ` Jani Nikula 2021-09-18 4:30 ` Lucas De Marchi 2021-09-20 7:41 ` Jani Nikula 2021-09-20 8:04 ` Gupta, Anshuman 2021-09-20 8:04 ` Gupta, Anshuman 2021-09-20 8:43 ` Jani Nikula 2021-09-20 8:43 ` Jani Nikula 2021-09-22 21:53 ` Lucas De Marchi 2021-04-12 9:05 ` [PATCH 15/19] drm/i915: WA for zero memory channel Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 16:57 ` Souza, Jose 2021-04-12 16:57 ` [Intel-gfx] " Souza, Jose 2021-04-12 9:05 ` [PATCH 16/19] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 17/19] drm/i915/dg1: Double memory bandwidth available Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 9:05 ` [PATCH 18/19] drm/i915/gtt: map the PD up front Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-12 15:17 ` Daniel Vetter 2021-04-12 15:17 ` Daniel Vetter 2021-04-12 16:01 ` Jani Nikula 2021-04-12 16:01 ` Jani Nikula 2021-04-12 16:36 ` Daniel Vetter 2021-04-12 16:36 ` Daniel Vetter 2021-04-12 16:08 ` Matthew Auld 2021-04-12 16:08 ` Matthew Auld 2021-04-12 17:00 ` Daniel Vetter 2021-04-12 17:00 ` Daniel Vetter 2021-04-13 9:28 ` Matthew Auld 2021-04-13 9:28 ` Matthew Auld 2021-04-13 10:18 ` Daniel Vetter 2021-04-13 10:18 ` Daniel Vetter 2021-04-12 9:05 ` [PATCH 19/19] drm/i915/gtt/dgfx: place the PD in LMEM Matthew Auld 2021-04-12 9:05 ` [Intel-gfx] " Matthew Auld 2021-04-14 15:37 ` Tvrtko Ursulin [this message] 2021-04-14 15:37 ` Tvrtko Ursulin 2021-04-12 11:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More DG1 enabling Patchwork 2021-04-12 11:12 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2021-04-12 11:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-04-12 13:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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