* [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform
@ 2021-04-23 16:27 Dave Gerlach
2021-04-23 16:27 ` [PATCH 01/17] arm: mach-k3: Add basic support for AM642 SoC definition Dave Gerlach
` (18 more replies)
0 siblings, 19 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Hi,
This series adds initial support for the latest new SoC, AM642,
from Texas Instruments.
Additional detail can be found in the patch descriptions, also
see AM64X Technical Reference Manual (SPRUIM2, Revised Jan 2021)
for further details: https://www.ti.com/lit/pdf/spruim2
Regards,
Dave
Dave Gerlach (14):
arm: mach-k3: Add basic support for AM642 SoC definition
arm: mach-k3: am642: Unlock all applicable control MMR registers
arm: mach-k3: am642: Store boot info from ROM
arm: mach-k3: am642: Load SYSFW binary and config from boot media
arm: mach-k3: am642: Use mmc start and stop callbacks
mmc: sdhci_am654: Add Support for TI's AM642 SoC
mailbox: k3-sec-proxy: Extend valid thread IDs
board: ti: am64x: Add board support for am64x evm
dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
arm: dts: ti: Add Support for AM642 SoC
arm: dts: k3-am642: Add initial support for EVM
arm: dts: k3-am642: Add r5 specific dt support
configs: am64x_evm_r5: Add Initial support
configs: am64x_evm_a53: Add Initial support
Keerthy (2):
arm: mach-k3: am642: Add support for boot device detection
armv8: mach-k3: am642: Add custom MMU support
Suman Anna (1):
arm: mach-k3: am642: Shut down R5 core after ATF startup on A53
arch/arm/dts/Makefile | 2 +
arch/arm/dts/k3-am64-main.dtsi | 405 ++++++++++++++++++
arch/arm/dts/k3-am64-mcu.dtsi | 76 ++++
arch/arm/dts/k3-am64.dtsi | 103 +++++
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 58 +++
arch/arm/dts/k3-am642-evm.dts | 246 +++++++++++
arch/arm/dts/k3-am642-r5-evm.dts | 169 ++++++++
arch/arm/dts/k3-am642.dtsi | 65 +++
arch/arm/mach-k3/Kconfig | 15 +-
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am642_init.c | 283 ++++++++++++
arch/arm/mach-k3/arm64-mmu.c | 41 ++
arch/arm/mach-k3/include/mach/am64_hardware.h | 52 +++
arch/arm/mach-k3/include/mach/am64_spl.h | 44 ++
arch/arm/mach-k3/include/mach/hardware.h | 4 +
arch/arm/mach-k3/include/mach/spl.h | 4 +
board/ti/am64x/Kconfig | 53 +++
board/ti/am64x/Makefile | 8 +
board/ti/am64x/evm.c | 48 +++
configs/am64x_evm_a53_defconfig | 96 +++++
configs/am64x_evm_r5_defconfig | 91 ++++
drivers/mailbox/k3-sec-proxy.c | 10 +-
drivers/mmc/am654_sdhci.c | 18 +
include/configs/am64x_evm.h | 105 +++++
include/dt-bindings/pinctrl/k3.h | 5 +-
25 files changed, 1988 insertions(+), 14 deletions(-)
create mode 100644 arch/arm/dts/k3-am64-main.dtsi
create mode 100644 arch/arm/dts/k3-am64-mcu.dtsi
create mode 100644 arch/arm/dts/k3-am64.dtsi
create mode 100644 arch/arm/dts/k3-am642-evm-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-am642-evm.dts
create mode 100644 arch/arm/dts/k3-am642-r5-evm.dts
create mode 100644 arch/arm/dts/k3-am642.dtsi
create mode 100644 arch/arm/mach-k3/am642_init.c
create mode 100644 arch/arm/mach-k3/include/mach/am64_hardware.h
create mode 100644 arch/arm/mach-k3/include/mach/am64_spl.h
create mode 100644 board/ti/am64x/Kconfig
create mode 100644 board/ti/am64x/Makefile
create mode 100644 board/ti/am64x/evm.c
create mode 100644 configs/am64x_evm_a53_defconfig
create mode 100644 configs/am64x_evm_r5_defconfig
create mode 100644 include/configs/am64x_evm.h
--
2.28.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 01/17] arm: mach-k3: Add basic support for AM642 SoC definition
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 02/17] arm: mach-k3: am642: Add support for boot device detection Dave Gerlach
` (17 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/Kconfig | 14 ++++++++++----
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am642_init.c | 28 ++++++++++++++++++++++++++++
3 files changed, 39 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-k3/am642_init.c
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index c7d186149ba5..35edc6d8eeb8 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -10,6 +10,9 @@ config SOC_K3_AM6
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
+config SOC_K3_AM642
+ bool "TI's K3 based AM642 SoC Family Support"
+
endchoice
config SYS_SOC
@@ -19,16 +22,18 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000 if SOC_K3_AM6
default 0x100000 if SOC_K3_J721E
+ default 0x1c0000 if SOC_K3_AM642
help
- Describes the total size of the MCU MSRAM. This doesn't
- specify the total size of SPL as ROM can use some part
- of this RAM. Once ROM gives control to SPL then this
- complete size can be usable.
+ Describes the total size of the MCU or OCMC MSRAM present on
+ the SoC in use. This doesn't specify the total size of SPL as
+ ROM can use some part of this RAM. Once ROM gives control to
+ SPL then this complete size can be usable.
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
default 0xc0000 if SOC_K3_J721E
+ default 0x180000 if SOC_K3_AM642
help
Describes the maximum size of the image that ROM can download
from any boot media.
@@ -51,6 +56,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffbfc if SOC_K3_J721E
+ default 0x701bebfc if SOC_K3_AM642
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 7572f56925cd..890d1498d0c8 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
new file mode 100644
index 000000000000..e73450da41da
--- /dev/null
+++ b/arch/arm/mach-k3/am642_init.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM642: SoC specific initialization
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ * Dave Gerlach <d-gerlach@ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include "common.h"
+
+#if defined(CONFIG_SPL_BUILD)
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_CPU_V7R)
+ setup_k3_mpu_regions();
+#endif
+
+ /* Init DM early */
+ spl_early_init();
+
+ preloader_console_init();
+}
+#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 02/17] arm: mach-k3: am642: Add support for boot device detection
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
2021-04-23 16:27 ` [PATCH 01/17] arm: mach-k3: Add basic support for AM642 SoC definition Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 03/17] arm: mach-k3: am642: Unlock all applicable control MMR registers Dave Gerlach
` (16 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
From: Keerthy <j-keerthy@ti.com>
AM642 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/am642_init.c | 98 +++++++++++++++++++
arch/arm/mach-k3/include/mach/am64_hardware.h | 48 +++++++++
arch/arm/mach-k3/include/mach/am64_spl.h | 44 +++++++++
arch/arm/mach-k3/include/mach/hardware.h | 4 +
arch/arm/mach-k3/include/mach/spl.h | 4 +
5 files changed, 198 insertions(+)
create mode 100644 arch/arm/mach-k3/include/mach/am64_hardware.h
create mode 100644 arch/arm/mach-k3/include/mach/am64_spl.h
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index e73450da41da..e63275ccc68f 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <spl.h>
#include <asm/io.h>
+#include <asm/arch/hardware.h>
#include "common.h"
#if defined(CONFIG_SPL_BUILD)
@@ -25,4 +26,101 @@ void board_init_f(ulong dummy)
preloader_console_init();
}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_EMMCBOOT;
+
+ case BOOT_DEVICE_MMC2:
+ return MMCSD_MODE_FS;
+
+ default:
+ return MMCSD_MODE_RAW;
+ }
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+ u32 bkup_bootmode =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+ u32 bkup_bootmode_cfg =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+
+ case BACKUP_BOOT_DEVICE_USB:
+ return BOOT_DEVICE_USB;
+
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+ };
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat)
+{
+ u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg =
+ (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ fallthrough;
+ case BOOT_DEVICE_QSPI:
+ fallthrough;
+ case BOOT_DEVICE_XSPI:
+ fallthrough;
+ case BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ fallthrough;
+ case BOOT_DEVICE_ETHERNET_RMII:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BOOT_DEVICE_EMMC:
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_MMC:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_NOBOOT:
+ return BOOT_DEVICE_RAM;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootindex == K3_PRIMARY_BOOTMODE)
+ return __get_primary_bootmedia(devstat);
+ else
+ return __get_backup_bootmedia(devstat);
+}
#endif
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
new file mode 100644
index 000000000000..8136585bde6f
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM64 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM64_HARDWARE_H
+#define __ASM_ARCH_AM64_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE 0x43000000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
+
+/* After the cfg mask and shifts have been applied */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
+
+/*
+ * The CTRL_MMR memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR lock/kick-mechanism shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0 0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
+#define CTRLMMR_LOCK_KICK1 0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h
new file mode 100644
index 000000000000..a3de4e70fc3f
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+#ifndef _ASM_ARCH_AM64_SPL_H_
+#define _ASM_ARCH_AM64_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_ETHERNET_RGMII 0x04
+#define BOOT_DEVICE_ETHERNET_RMII 0x05
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+
+#define BOOT_DEVICE_USB 0x0A
+#define BOOT_DEVICE_GPMC_NOR 0x0C
+#define BOOT_DEVICE_PCIE 0x0D
+#define BOOT_DEVICE_XSPI 0x0E
+
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+#define BOOT_DEVICE_MMC2 0x08
+#define BOOT_DEVICE_MMC1 0x09
+/* INVALID */
+#define BOOT_DEVICE_MMC2_2 0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+#define BACKUP_BOOT_DEVICE_I2C 0x07
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 02b3df0e1b78..8725e7d51a5b 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -14,6 +14,10 @@
#include "j721e_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_hardware.h"
+#endif
+
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
#define JTAG_ID_VARIANT_SHIFT 28
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index a26c8ecdd5bd..ef1c3fb8cae6 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -13,4 +13,8 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_spl.h"
#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_spl.h"
+#endif
#endif /* _ASM_ARCH_SPL_H_ */
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 03/17] arm: mach-k3: am642: Unlock all applicable control MMR registers
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
2021-04-23 16:27 ` [PATCH 01/17] arm: mach-k3: Add basic support for AM642 SoC definition Dave Gerlach
2021-04-23 16:27 ` [PATCH 02/17] arm: mach-k3: am642: Add support for boot device detection Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 04/17] arm: mach-k3: am642: Store boot info from ROM Dave Gerlach
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MAIN domain.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/am642_init.c | 16 ++++++++++++++++
arch/arm/mach-k3/include/mach/am64_hardware.h | 10 ++++++----
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index e63275ccc68f..5ab2904c5e0c 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -15,12 +15,28 @@
#if defined(CONFIG_SPL_BUILD)
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all PADCFG_MMR1 module registers */
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 3);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+}
+
void board_init_f(ulong dummy)
{
#if defined(CONFIG_CPU_V7R)
setup_k3_mpu_regions();
#endif
+ ctrl_mmr_unlock();
+
/* Init DM early */
spl_early_init();
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index 8136585bde6f..ec5387025b98 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -12,6 +12,8 @@
#define CTRL_MMR0_BASE 0x43000000
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define PADCFG_MMR1_BASE 0xf0000
+
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
@@ -29,14 +31,14 @@
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
/*
- * The CTRL_MMR memory space is divided into several equally-spaced
- * partitions, so defining the partition size allows us to determine
- * register addresses common to those partitions.
+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several
+ * equally-spaced partitions, so defining the partition size allows us to
+ * determine register addresses common to those partitions.
*/
#define CTRL_MMR0_PARTITION_SIZE 0x4000
/*
- * CTRL_MMR lock/kick-mechanism shared register definitions.
+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
*/
#define CTRLMMR_LOCK_KICK0 0x01008
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 04/17] arm: mach-k3: am642: Store boot info from ROM
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (2 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 03/17] arm: mach-k3: am642: Unlock all applicable control MMR registers Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 05/17] arm: mach-k3: am642: Load SYSFW binary and config from boot media Dave Gerlach
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
For AM642, ROM supports loading system firmware directly
from boot image. ROM passes information about the number of
images that are loaded to bootloader at a specific address
that is temporary. Add support for storing this information
somewhere permanent before it gets corrupted.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/am642_init.c | 21 +++++++++++++++++++
arch/arm/mach-k3/include/mach/am64_hardware.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 5ab2904c5e0c..7ebe5b56cd1f 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -29,12 +29,33 @@ static void ctrl_mmr_unlock(void)
mmr_unlock(CTRL_MMR0_BASE, 6);
}
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(.data);
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
void board_init_f(ulong dummy)
{
#if defined(CONFIG_CPU_V7R)
setup_k3_mpu_regions();
#endif
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_info_from_rom();
+
ctrl_mmr_unlock();
/* Init DM early */
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
index ec5387025b98..c440685e608f 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -47,4 +47,6 @@
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
+
#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 05/17] arm: mach-k3: am642: Load SYSFW binary and config from boot media
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (3 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 04/17] arm: mach-k3: am642: Store boot info from ROM Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 06/17] arm: mach-k3: am642: Use mmc start and stop callbacks Dave Gerlach
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the AM642 early initialization sequence. Also
make use of existing logic to detect if ROM has already loaded sysfw
and avoided attempting to reload and instead just prepare to use already
running firmware.
While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW
to print diagnostic messages.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/am642_init.c | 37 +++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 7ebe5b56cd1f..db2a8d4d6013 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -11,7 +11,14 @@
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include <asm/arch/sys_proto.h>
#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
#if defined(CONFIG_SPL_BUILD)
@@ -46,6 +53,11 @@ static void store_boot_info_from_rom(void)
void board_init_f(ulong dummy)
{
+#if defined(CONFIG_K3_LOAD_SYSFW)
+ struct udevice *dev;
+ int ret;
+#endif
+
#if defined(CONFIG_CPU_V7R)
setup_k3_mpu_regions();
#endif
@@ -62,6 +74,31 @@ void board_init_f(ulong dummy)
spl_early_init();
preloader_console_init();
+
+#if defined(CONFIG_K3_LOAD_SYSFW)
+ /*
+ * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the system
+ * firmware (SYSFW) image for various purposes and SYSFW depends on us
+ * to initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+ * Load, start up, and configure system controller firmware.
+ * This will determine whether or not ROM has already loaded
+ * system firmware and if so, will only perform needed config
+ * and not attempt to load firmware again.
+ */
+ k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), NULL, NULL);
+#endif
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
}
u32 spl_boot_mode(const u32 boot_device)
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 06/17] arm: mach-k3: am642: Use mmc start and stop callbacks
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (4 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 05/17] arm: mach-k3: am642: Load SYSFW binary and config from boot media Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 07/17] arm: mach-k3: am642: Shut down R5 core after ATF startup on A53 Dave Gerlach
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
To avoid any glitches on MMC clock line, make use of pm per and post
callbacks when loading sysfw.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/am642_init.c | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index db2a8d4d6013..adae9fbbb8cc 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -19,6 +19,7 @@
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
+#include <mmc.h>
#if defined(CONFIG_SPL_BUILD)
@@ -51,6 +52,36 @@ static void store_boot_info_from_rom(void)
sizeof(struct rom_extended_boot_data));
}
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
+void k3_mmc_stop_clock(void)
+{
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc->saved_clock = mmc->clock;
+ mmc_set_clock(mmc, 0, true);
+ }
+}
+
+void k3_mmc_restart_clock(void)
+{
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc_set_clock(mmc, mmc->saved_clock, false);
+ }
+}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
+#endif
+
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
@@ -94,7 +125,8 @@ void board_init_f(ulong dummy)
* system firmware and if so, will only perform needed config
* and not attempt to load firmware again.
*/
- k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), NULL, NULL);
+ k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
+ k3_mmc_restart_clock);
#endif
/* Output System Firmware version info */
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 07/17] arm: mach-k3: am642: Shut down R5 core after ATF startup on A53
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (5 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 06/17] arm: mach-k3: am642: Use mmc start and stop callbacks Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 08/17] armv8: mach-k3: am642: Add custom MMU support Dave Gerlach
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
From: Suman Anna <s-anna@ti.com>
The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs
the R5 SPL that performs the initialization of the System Controller
processor and starting the Arm Trusted Firmware (ATF) on the Arm
Cortex A53 cluster. The Core0 serves as this boot processor and is
parked in WFE after all the initialization. Core1 does not directly
participate in the boot flow, and is simply parked in a WFI.
Power down these R5 cores (and the associated RTI timer resources
that were indirectly powered up) after starting up ATF on A53 by
using the appropriate SYSFW API in release_resources_for_core_shutdown().
This allows these Main R5F cores to be further controlled from the
A53 to run regular applications.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/am642_init.c | 51 +++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index adae9fbbb8cc..8931aaabf2f9 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -230,3 +230,54 @@ u32 spl_boot_device(void)
return __get_backup_bootmedia(devstat);
}
#endif
+
+#if defined(CONFIG_SYS_K3_SPL_ATF)
+
+#define AM64X_DEV_RTI8 127
+#define AM64X_DEV_RTI9 128
+#define AM64X_DEV_R5FSS0_CORE0 121
+#define AM64X_DEV_R5FSS0_CORE1 122
+
+void release_resources_for_core_shutdown(void)
+{
+ struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+ struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+ struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+ int ret;
+ u32 i;
+
+ const u32 put_device_ids[] = {
+ AM64X_DEV_RTI9,
+ AM64X_DEV_RTI8,
+ };
+
+ /* Iterate through list of devices to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+ u32 id = put_device_ids[i];
+
+ ret = dev_ops->put_device(ti_sci, id);
+ if (ret)
+ panic("Failed to put device %u (%d)\n", id, ret);
+ }
+
+ const u32 put_core_ids[] = {
+ AM64X_DEV_R5FSS0_CORE1,
+ AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
+ };
+
+ /* Iterate through list of cores to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+ u32 id = put_core_ids[i];
+
+ /*
+ * Queue up the core shutdown request. Note that this call
+ * needs to be followed up by an actual invocation of an WFE
+ * or WFI CPU instruction.
+ */
+ ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+ if (ret)
+ panic("Failed sending core %u shutdown message (%d)\n",
+ id, ret);
+ }
+}
+#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 08/17] armv8: mach-k3: am642: Add custom MMU support
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (6 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 07/17] arm: mach-k3: am642: Shut down R5 core after ATF startup on A53 Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 09/17] mmc: sdhci_am654: Add Support for TI's AM642 SoC Dave Gerlach
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
From: Keerthy <j-keerthy@ti.com>
Change the memory attributes for the DDR regions used by the remote
processors on AM65x so that the cores can see and execute the proper code.
A separate table based on the previous K3 SoCs is introduced since the
number of remote processors and their DDR usage is different between the
SoC families.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/arm64-mmu.c | 41 ++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index a0da3df59388..94242e1e5cc3 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -180,3 +180,44 @@ struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_TARGET_J7200_A72_EVM */
#endif /* CONFIG_SOC_K3_J721E */
+
+#ifdef CONFIG_SOC_K3_AM642
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = am64_mem_map;
+#endif /* CONFIG_SOC_K3_AM642 */
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 09/17] mmc: sdhci_am654: Add Support for TI's AM642 SoC
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (7 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 08/17] armv8: mach-k3: am642: Add custom MMU support Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 10/17] mailbox: k3-sec-proxy: Extend valid thread IDs Dave Gerlach
` (9 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Add support for the controller present on the AM642 SoC.
There are instances:
sdhci0: 8bit bus width, max 400 MBps
sdhci1: 4bit bus width, max 100 MBps
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
drivers/mmc/am654_sdhci.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 11dcde134c5f..a86d96aacd2b 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -470,6 +470,16 @@ const struct am654_driver_data j721e_4bit_drv_data = {
.flags = IOMUX_PRESENT,
};
+static const struct am654_driver_data sdhci_am64_8bit_drvdata = {
+ .ops = &am654_sdhci_ops,
+ .flags = DLL_PRESENT | DLL_CALIB,
+};
+
+static const struct am654_driver_data sdhci_am64_4bit_drvdata = {
+ .ops = &j721e_4bit_sdhci_ops,
+ .flags = IOMUX_PRESENT,
+};
+
const struct soc_attr am654_sdhci_soc_attr[] = {
{ .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
{/* sentinel */}
@@ -651,6 +661,14 @@ static const struct udevice_id am654_sdhci_ids[] = {
.compatible = "ti,j721e-sdhci-4bit",
.data = (ulong)&j721e_4bit_drv_data,
},
+ {
+ .compatible = "ti,am64-sdhci-8bit",
+ .data = (ulong)&sdhci_am64_8bit_drvdata,
+ },
+ {
+ .compatible = "ti,am64-sdhci-4bit",
+ .data = (ulong)&sdhci_am64_4bit_drvdata,
+ },
{ }
};
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 10/17] mailbox: k3-sec-proxy: Extend valid thread IDs
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (8 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 09/17] mmc: sdhci_am654: Add Support for TI's AM642 SoC Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 11/17] board: ti: am64x: Add board support for am64x evm Dave Gerlach
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
AM64x uses a different thread mapping that existing K3 SoCs, so update
the valid thread ID list to include those used for AM64x.
Also remove the comment identifying the purpose of each thread ID. The
purpose of the thread ID is specified when describing the threads in the
device tree and the same ID can mean different things on different SoCs,
so the comment is not useful.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
drivers/mailbox/k3-sec-proxy.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index ff21a08388a9..88f320515aec 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -409,15 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev)
return 0;
}
-/*
- * Thread ID #4: ROM request
- * Thread ID #5: ROM response, SYSFW notify
- * Thread ID #6: SYSFW request response
- * Thread ID #7: SYSFW request high priority
- * Thread ID #8: SYSFW request low priority
- * Thread ID #9: SYSFW notify response
- */
-static const u32 am6x_valid_threads[] = { 4, 5, 6, 7, 8, 9, 11, 13 };
+static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 };
static const struct k3_sec_proxy_desc am654_desc = {
.thread_count = 90,
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 11/17] board: ti: am64x: Add board support for am64x evm
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (9 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 10/17] mailbox: k3-sec-proxy: Extend valid thread IDs Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 12/17] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64 Dave Gerlach
` (7 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Add board specific initialization for am64x based boards.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/mach-k3/Kconfig | 1 +
board/ti/am64x/Kconfig | 53 ++++++++++++++++++
board/ti/am64x/Makefile | 8 +++
board/ti/am64x/evm.c | 48 +++++++++++++++++
include/configs/am64x_evm.h | 105 ++++++++++++++++++++++++++++++++++++
5 files changed, 215 insertions(+)
create mode 100644 board/ti/am64x/Kconfig
create mode 100644 board/ti/am64x/Makefile
create mode 100644 board/ti/am64x/evm.c
create mode 100644 include/configs/am64x_evm.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 35edc6d8eeb8..bfbce44bfa59 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -148,5 +148,6 @@ config SYS_K3_SPL_ATF
after SPL from R5.
source "board/ti/am65x/Kconfig"
+source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
endif
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
new file mode 100644
index 000000000000..a49e22266983
--- /dev/null
+++ b/board/ti/am64x/Kconfig
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+
+choice
+ prompt "K3 AM64 based boards"
+ optional
+
+config TARGET_AM642_A53_EVM
+ bool "TI K3 based AM642 EVM running on A53"
+ select ARM64
+ select SOC_K3_AM642
+ imply BOARD
+ imply SPL_BOARD
+
+config TARGET_AM642_R5_EVM
+ bool "TI K3 based AM642 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select SOC_K3_AM642
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_AM642_A53_EVM
+
+config SYS_BOARD
+ default "am64x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am64x_evm"
+
+endif
+
+if TARGET_AM642_R5_EVM
+
+config SYS_BOARD
+ default "am64x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am64x_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/am64x/Makefile b/board/ti/am64x/Makefile
new file mode 100644
index 000000000000..71bdca7d9592
--- /dev/null
+++ b/board/ti/am64x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+# Keerthy <j-keerthy@ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
new file mode 100644
index 000000000000..147fe5488a63
--- /dev/null
+++ b/board/ti/am64x/evm.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM642 EVM
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+#if defined(CONFIG_TARGET_AM642_A53_EVM)
+ if (!strcmp(name, "k3-am642-evm"))
+ return 0;
+#endif
+
+ return -1;
+}
+#endif
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
new file mode 100644
index 000000000000..4f710181b31b
--- /dev/null
+++ b/include/configs/am64x_evm.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 AM642 SoC family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#ifndef __CONFIG_AM642_EVM_H
+#define __CONFIG_AM642_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
+#endif
+
+#ifndef CONFIG_CPU_V7R
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE 0x5000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+ CONFIG_SPL_BSS_MAX_SIZE)
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
+
+#define PARTS_DEFAULT \
+ /* Linux partitions */ \
+ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS \
+ "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "findfdt=" \
+ "setenv name_fdt ${default_device_tree};" \
+ "setenv fdtfile ${name_fdt}\0" \
+ "name_kern=Image\0" \
+ "console=ttyS2,115200n8\0" \
+ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \
+ "${mtdparts}\0" \
+ "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \
+ "boot=mmc\0" \
+ "mmcdev=1\0" \
+ "bootpart=1:2\0" \
+ "bootdir=/boot\0" \
+ "rd_spec=-\0" \
+ "init_mmc=run args_all args_mmc\0" \
+ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
+ "get_overlay_mmc=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
+ "fdt apply ${dtboaddr};" \
+ "done;\0" \
+ "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
+ "${bootdir}/${name_kern}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
+ "partitions=" PARTS_DEFAULT
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
+ EXTRA_ENV_AM642_BOARD_SETTINGS \
+ EXTRA_ENV_AM642_BOARD_SETTINGS_MMC
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#endif /* __CONFIG_AM642_EVM_H */
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 12/17] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (10 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 11/17] board: ti: am64x: Add board support for am64x evm Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 13/17] arm: dts: ti: Add Support for AM642 SoC Dave Gerlach
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Add pinctrl macros for AM64 SoC. These macro definitions are similar to
that of previous platforms, but adding new definitions to avoid any
naming confusions in the soc dts files.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
include/dt-bindings/pinctrl/k3.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index ce0cd38f56e4..52df47298e03 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -2,7 +2,7 @@
/*
* This header provides constants for TI K3-AM65 pinctrl bindings.
*
- * Copyright (C) 2018 Texas Instruments
+ * Copyright (C) 2018-2021 Texas Instruments
*/
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
@@ -38,4 +38,7 @@
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 13/17] arm: dts: ti: Add Support for AM642 SoC
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (11 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 12/17] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64 Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 14/17] arm: dts: k3-am642: Add initial support for EVM Dave Gerlach
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/dts/k3-am64-main.dtsi | 405 +++++++++++++++++++++++++++++++++
arch/arm/dts/k3-am64-mcu.dtsi | 76 +++++++
arch/arm/dts/k3-am64.dtsi | 103 +++++++++
arch/arm/dts/k3-am642.dtsi | 65 ++++++
4 files changed, 649 insertions(+)
create mode 100644 arch/arm/dts/k3-am64-main.dtsi
create mode 100644 arch/arm/dts/k3-am64-mcu.dtsi
create mode 100644 arch/arm/dts/k3-am64.dtsi
create mode 100644 arch/arm/dts/k3-am642.dtsi
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
new file mode 100644
index 000000000000..5f85950daef7
--- /dev/null
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram at 70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x70000000 0x200000>;
+
+ atf-sram at 0 {
+ reg = <0x0 0x1a000>;
+ };
+ };
+
+ gic500: interrupt-controller at 1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01840000 0x00 0xC0000>; /* GICR */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller at 1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ dmss: dmss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ ti,sci-dev-id = <25>;
+
+ secure_proxy_main: mailbox at 4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_012";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ inta_main_dmss: interrupt-controller at 48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <4 68 36>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller at 485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller at 485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>, /* SAUL_TX_1_CHAN */
+ <0x27>, /* ICSSG_0_TX_CHAN */
+ <0x28>; /* ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>, /* RING_SAUL_TX_1_CHAN */
+ <0x14>, /* RING_ICSSG_0_TX_CHAN */
+ <0x15>; /* RING_ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>, /* SAUL_RX_3_CHAN */
+ <0x35>, /* ICSSG_0_RX_CHAN */
+ <0x37>; /* ICSSG_1_RX_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
+ <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
+ <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
+ };
+ };
+
+ dmsc: dmsc at 44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ main_pmx0: pinctrl at f4000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0xf4000 0x00 0x2d0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_conf: syscon at 43000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x43000000 0x20000>;
+
+ chipid at 14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00000014 0x4>;
+ };
+ };
+
+ main_uart0: serial at 2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial at 2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial at 2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial at 2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 154 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial at 2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 155 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial at 2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial at 2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>;
+ clock-names = "fclk";
+ };
+
+ main_i2c0: i2c at 20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c1: i2c at 20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c2: i2c at 20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c3: i2c at 20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ };
+
+ main_spi0: spi at 20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
+ dma-names = "tx0", "rx0";
+ };
+
+ main_spi1: spi at 20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ };
+
+ main_spi2: spi at 20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ };
+
+ main_spi3: spi at 20130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20130000 0x00 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 144 0>;
+ };
+
+ main_spi4: spi at 20140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20140000 0x00 0x400>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 145 0>;
+ };
+
+ sdhci0: mmc at fa10000 {
+ compatible = "ti,am64-sdhci-8bit";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,otap-del-sel-hs400 = <0x4>;
+ };
+
+ sdhci1: mmc at fa00000 {
+ compatible = "ti,am64-sdhci-4bit";
+ reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
+ clock-names = "clk_ahb", "clk_xin";
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,clkbuf-sel = <0x7>;
+ };
+};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
new file mode 100644
index 000000000000..1d2be485a669
--- /dev/null
+++ b/arch/arm/dts/k3-am64-mcu.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM64 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_uart0: serial at 4a00000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart1: serial at 4a10000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a10000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 160 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_i2c0: i2c at 4900000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04900000 0x00 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ };
+
+ mcu_i2c1: i2c at 4910000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04910000 0x00 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 2>;
+ clock-names = "fck";
+ };
+
+ mcu_spi0: spi at 4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ };
+
+ mcu_spi1: spi at 4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ };
+};
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
new file mode 100644
index 000000000000..0ae8c844c482
--- /dev/null
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 AM642 SoC";
+ compatible = "ti,am642";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &mcu_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ };
+
+ chosen { };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus at f4000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+ <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
+ <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
+ <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
+ <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
+ <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
+
+ cbass_mcu: bus at 4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am64-main.dtsi"
+#include "k3-am64-mcu.dtsi"
diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi
new file mode 100644
index 000000000000..e2b397c88401
--- /dev/null
+++ b/arch/arm/dts/k3-am642.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC family in Dual core configuration
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am64.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 14/17] arm: dts: k3-am642: Add initial support for EVM
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (12 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 13/17] arm: dts: ti: Add Support for AM642 SoC Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 15/17] arm: dts: k3-am642: Add r5 specific dt support Dave Gerlach
` (4 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
The AM642 EValuation Module (EVM) is a board that provides access to
various peripherals available on the AM642 SoC, such as PCIe, USB 2.0,
CPSW Ethernet, ADC, and more.
Add basic support.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am642-evm.dts | 246 ++++++++++++++++++++++++++++++++++
2 files changed, 247 insertions(+)
create mode 100644 arch/arm/dts/k3-am642-evm.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c6710826a0ae..70ba1414fb01 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1002,6 +1002,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
new file mode 100644
index 000000000000..1f1787750fef
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "k3-am642.dtsi"
+
+/ {
+ compatible = "ti,am642-evm", "ti,am642";
+ model = "Texas Instruments AM642 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee at 9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixed-regulator-sd {
+ /* TPS2051BD */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vddb: fixedregulator-vddb {
+ compatible = "regulator-fixed";
+ regulator-name = "vddb_3v3_display";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "am64-evm:red:heartbeat";
+ gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "off";
+ };
+ };
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+ >;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+/* main_uart1 is reserved for firmware usage */
+&main_uart1 {
+ status = "reserved";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&mcu_uart0 {
+ status = "disabled";
+};
+
+&mcu_uart1 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio at 22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
+ "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
+ "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
+ "MMC1_SD_EN", "FSI_FET_SEL",
+ "MCAN0_STB_3V3", "MCAN1_STB_3V3",
+ "CPSW_FET_SEL", "CPSW_FET2_SEL",
+ "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
+ "GPIO_OLED_RESETn", "VPP_LDO_EN",
+ "TEST_LED1", "TP92", "TP90", "TP88",
+ "TP87", "TP86", "TP89", "TP91";
+ };
+
+ /* osd9616p0899-10 */
+ display at 3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ reg = <0x3c>;
+ reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&vddb>;
+ solomon,height = <16>;
+ solomon,width = <96>;
+ solomon,com-seq;
+ solomon,com-invdir;
+ solomon,page-offset = <0>;
+ solomon,prechargep1 = <2>;
+ solomon,prechargep2 = <13>;
+ };
+};
+
+&mcu_i2c0 {
+ status = "disabled";
+};
+
+&mcu_i2c1 {
+ status = "disabled";
+};
+
+&mcu_spi0 {
+ status = "disabled";
+};
+
+&mcu_spi1 {
+ status = "disabled";
+};
+
+&sdhci0 {
+ /* emmc */
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 15/17] arm: dts: k3-am642: Add r5 specific dt support
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (13 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 14/17] arm: dts: k3-am642: Add initial support for EVM Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 16/17] configs: am64x_evm_r5: Add Initial support Dave Gerlach
` (3 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Add initial support for dt that runs on r5.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 58 +++++++++
arch/arm/dts/k3-am642-r5-evm.dts | 169 ++++++++++++++++++++++++++
3 files changed, 229 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-am642-evm-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-am642-r5-evm.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 70ba1414fb01..b500e4059383 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1002,7 +1002,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
-dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb
+dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
+ k3-am642-r5-evm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
new file mode 100644
index 000000000000..a8d5c4d21ad4
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+ timer1: timer at 2400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x2400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&dmss {
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&sdhci0 {
+ u-boot,dm-spl;
+};
+
+&sdhci1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
new file mode 100644
index 000000000000..8f4db0d2a4a0
--- /dev/null
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am642.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ a53_0: a53 at 0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1000000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee at 9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ clk_200mhz: dummy-clock-200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
+ mbox-names = "tx", "rx";
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_uart0_pins_default: main-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_mmc0_pins_default: main-mmc0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
+ >;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+};
+
+&main_uart1 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&sdhci0 {
+ /delete-property/ power-domains;
+ clocks = <&clk_200mhz>;
+ clock-names = "clk_xin";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ pinctrl-0 = <&main_mmc0_pins_default>;
+};
+
+&sdhci1 {
+ /delete-property/ power-domains;
+ clocks = <&clk_200mhz>;
+ clock-names = "clk_xin";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+};
+
+#include "k3-am642-evm-u-boot.dtsi"
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 16/17] configs: am64x_evm_r5: Add Initial support
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (14 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 15/17] arm: dts: k3-am642: Add r5 specific dt support Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-04-23 16:27 ` [PATCH 17/17] configs: am64x_evm_a53: " Dave Gerlach
` (2 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Add initial R5 defconfig support for AM64x SoCs.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
configs/am64x_evm_r5_defconfig | 91 ++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 configs/am64x_evm_r5_defconfig
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
new file mode 100644
index 000000000000..0fa4ae90b59b
--- /dev/null
+++ b/configs/am64x_evm_r5_defconfig
@@ -0,0 +1,91 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SOC_K3_AM642=y
+CONFIG_TARGET_AM642_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x70020000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 17/17] configs: am64x_evm_a53: Add Initial support
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (15 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 16/17] configs: am64x_evm_r5: Add Initial support Dave Gerlach
@ 2021-04-23 16:27 ` Dave Gerlach
2021-05-06 17:54 ` Vignesh Raghavendra
2021-05-06 8:02 ` [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Lokesh Vutla
2021-05-12 13:58 ` Lokesh Vutla
18 siblings, 1 reply; 23+ messages in thread
From: Dave Gerlach @ 2021-04-23 16:27 UTC (permalink / raw)
To: u-boot
Add initial A53 defconfig support for AM64x SoCs.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
configs/am64x_evm_a53_defconfig | 96 +++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 configs/am64x_evm_a53_defconfig
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
new file mode 100644
index 000000000000..5aa4ad3022fc
--- /dev/null
+++ b/configs/am64x_evm_a53_defconfig
@@ -0,0 +1,96 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM642=y
+CONFIG_TARGET_AM642_A53_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_TIME=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
--
2.28.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (16 preceding siblings ...)
2021-04-23 16:27 ` [PATCH 17/17] configs: am64x_evm_a53: " Dave Gerlach
@ 2021-05-06 8:02 ` Lokesh Vutla
2021-05-06 12:22 ` Lokesh Vutla
2021-05-12 13:58 ` Lokesh Vutla
18 siblings, 1 reply; 23+ messages in thread
From: Lokesh Vutla @ 2021-05-06 8:02 UTC (permalink / raw)
To: u-boot
On 23/04/21 9:57 pm, Dave Gerlach wrote:
> Hi,
>
> This series adds initial support for the latest new SoC, AM642,
> from Texas Instruments.
>
> Additional detail can be found in the patch descriptions, also
> see AM64X Technical Reference Manual (SPRUIM2, Revised Jan 2021)
> for further details: https://www.ti.com/lit/pdf/spruim2
>
> Regards,
> Dave
>
> Dave Gerlach (14):
> arm: mach-k3: Add basic support for AM642 SoC definition
> arm: mach-k3: am642: Unlock all applicable control MMR registers
> arm: mach-k3: am642: Store boot info from ROM
> arm: mach-k3: am642: Load SYSFW binary and config from boot media
> arm: mach-k3: am642: Use mmc start and stop callbacks
> mmc: sdhci_am654: Add Support for TI's AM642 SoC
> mailbox: k3-sec-proxy: Extend valid thread IDs
> board: ti: am64x: Add board support for am64x evm
> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
> arm: dts: ti: Add Support for AM642 SoC
> arm: dts: k3-am642: Add initial support for EVM
> arm: dts: k3-am642: Add r5 specific dt support
> configs: am64x_evm_r5: Add Initial support
> configs: am64x_evm_a53: Add Initial support
You need to add MAINTAINERS file under board/ti/am64x. Else few testes are failing.
https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/7397
Thanks and regards,
Lokesh
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform
2021-05-06 8:02 ` [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Lokesh Vutla
@ 2021-05-06 12:22 ` Lokesh Vutla
0 siblings, 0 replies; 23+ messages in thread
From: Lokesh Vutla @ 2021-05-06 12:22 UTC (permalink / raw)
To: u-boot
On 06/05/21 1:32 pm, Lokesh Vutla wrote:
>
>
> On 23/04/21 9:57 pm, Dave Gerlach wrote:
>> Hi,
>>
>> This series adds initial support for the latest new SoC, AM642,
>> from Texas Instruments.
>>
>> Additional detail can be found in the patch descriptions, also
>> see AM64X Technical Reference Manual (SPRUIM2, Revised Jan 2021)
>> for further details: https://www.ti.com/lit/pdf/spruim2
>>
>> Regards,
>> Dave
>>
>> Dave Gerlach (14):
>> arm: mach-k3: Add basic support for AM642 SoC definition
>> arm: mach-k3: am642: Unlock all applicable control MMR registers
>> arm: mach-k3: am642: Store boot info from ROM
>> arm: mach-k3: am642: Load SYSFW binary and config from boot media
>> arm: mach-k3: am642: Use mmc start and stop callbacks
>> mmc: sdhci_am654: Add Support for TI's AM642 SoC
>> mailbox: k3-sec-proxy: Extend valid thread IDs
>> board: ti: am64x: Add board support for am64x evm
>> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
>> arm: dts: ti: Add Support for AM642 SoC
>> arm: dts: k3-am642: Add initial support for EVM
>> arm: dts: k3-am642: Add r5 specific dt support
>> configs: am64x_evm_r5: Add Initial support
>> configs: am64x_evm_a53: Add Initial support
>
> You need to add MAINTAINERS file under board/ti/am64x. Else few testes are failing.
>
> https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/7397
I have updated locally and pushed the change:
https://source.denx.de/u-boot/custodians/u-boot-ti/-/commit/140fde6a6d7835095be2e5aa4316fe03e3bc28e9
https://source.denx.de/u-boot/custodians/u-boot-ti/-/commit/465bee1469a30a675bc7ff34229536dcc5af14f8
Please see if it looks good.
Thanks and regards,
Lokesh
>
> Thanks and regards,
> Lokesh
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 17/17] configs: am64x_evm_a53: Add Initial support
2021-04-23 16:27 ` [PATCH 17/17] configs: am64x_evm_a53: " Dave Gerlach
@ 2021-05-06 17:54 ` Vignesh Raghavendra
2021-05-07 11:23 ` Vignesh Raghavendra
0 siblings, 1 reply; 23+ messages in thread
From: Vignesh Raghavendra @ 2021-05-06 17:54 UTC (permalink / raw)
To: u-boot
On 4/23/21 9:57 PM, Dave Gerlach wrote:
> Add initial A53 defconfig support for AM64x SoCs.
>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
> ---
> configs/am64x_evm_a53_defconfig | 96 +++++++++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
> create mode 100644 configs/am64x_evm_a53_defconfig
>
> diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
> new file mode 100644
> index 000000000000..5aa4ad3022fc
> --- /dev/null
> +++ b/configs/am64x_evm_a53_defconfig
> @@ -0,0 +1,96 @@
[...]
> +CONFIG_MMC_SDHCI_ADMA=y
> +CONFIG_SPL_MMC_SDHCI_ADMA=y
> +CONFIG_MMC_SDHCI_AM654=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_MODE=0
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PHY_TI=y
CONFIG does not exist.. Please replace with:
CONFIG_PHY_TI_DP83867=y
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 17/17] configs: am64x_evm_a53: Add Initial support
2021-05-06 17:54 ` Vignesh Raghavendra
@ 2021-05-07 11:23 ` Vignesh Raghavendra
0 siblings, 0 replies; 23+ messages in thread
From: Vignesh Raghavendra @ 2021-05-07 11:23 UTC (permalink / raw)
To: u-boot
On 5/6/21 11:24 PM, Vignesh Raghavendra wrote:
>
>
> On 4/23/21 9:57 PM, Dave Gerlach wrote:
>> Add initial A53 defconfig support for AM64x SoCs.
>>
>> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
>> ---
>> configs/am64x_evm_a53_defconfig | 96 +++++++++++++++++++++++++++++++++
>> 1 file changed, 96 insertions(+)
>> create mode 100644 configs/am64x_evm_a53_defconfig
>>
>> diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
>> new file mode 100644
>> index 000000000000..5aa4ad3022fc
>> --- /dev/null
>> +++ b/configs/am64x_evm_a53_defconfig
>> @@ -0,0 +1,96 @@
> [...]
>> +CONFIG_MMC_SDHCI_ADMA=y
>> +CONFIG_SPL_MMC_SDHCI_ADMA=y
>> +CONFIG_MMC_SDHCI_AM654=y
>> +CONFIG_DM_SPI_FLASH=y
>> +CONFIG_SF_DEFAULT_MODE=0
>> +CONFIG_SPI_FLASH_SPANSION=y
>> +CONFIG_SPI_FLASH_STMICRO=y
>> +CONFIG_PHY_TI=y
>
> CONFIG does not exist.. Please replace with:
>
Sorry, I meant the meaning has changed for CONFIG_PHY_TI.
It now just allows to register any of the TI PHYs and is selected by
CONFIG_PHY_TI_DP83867 implicitly.
>
> CONFIG_PHY_TI_DP83867=y
>
Also drop
+CONFIG_PHY_FIXED=y
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
` (17 preceding siblings ...)
2021-05-06 8:02 ` [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Lokesh Vutla
@ 2021-05-12 13:58 ` Lokesh Vutla
18 siblings, 0 replies; 23+ messages in thread
From: Lokesh Vutla @ 2021-05-12 13:58 UTC (permalink / raw)
To: u-boot
On 23/04/21 9:57 pm, Dave Gerlach wrote:
> Hi,
>
> This series adds initial support for the latest new SoC, AM642,
> from Texas Instruments.
>
> Additional detail can be found in the patch descriptions, also
> see AM64X Technical Reference Manual (SPRUIM2, Revised Jan 2021)
> for further details: https://www.ti.com/lit/pdf/spruim2
Fixed the MAINTAINERS file and Timer clock frequency and applied to u-boot-ti/for-rc
Thanks and regards,
Lokesh
>
> Regards,
> Dave
>
> Dave Gerlach (14):
> arm: mach-k3: Add basic support for AM642 SoC definition
> arm: mach-k3: am642: Unlock all applicable control MMR registers
> arm: mach-k3: am642: Store boot info from ROM
> arm: mach-k3: am642: Load SYSFW binary and config from boot media
> arm: mach-k3: am642: Use mmc start and stop callbacks
> mmc: sdhci_am654: Add Support for TI's AM642 SoC
> mailbox: k3-sec-proxy: Extend valid thread IDs
> board: ti: am64x: Add board support for am64x evm
> dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64
> arm: dts: ti: Add Support for AM642 SoC
> arm: dts: k3-am642: Add initial support for EVM
> arm: dts: k3-am642: Add r5 specific dt support
> configs: am64x_evm_r5: Add Initial support
> configs: am64x_evm_a53: Add Initial support
>
> Keerthy (2):
> arm: mach-k3: am642: Add support for boot device detection
> armv8: mach-k3: am642: Add custom MMU support
>
> Suman Anna (1):
> arm: mach-k3: am642: Shut down R5 core after ATF startup on A53
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/k3-am64-main.dtsi | 405 ++++++++++++++++++
> arch/arm/dts/k3-am64-mcu.dtsi | 76 ++++
> arch/arm/dts/k3-am64.dtsi | 103 +++++
> arch/arm/dts/k3-am642-evm-u-boot.dtsi | 58 +++
> arch/arm/dts/k3-am642-evm.dts | 246 +++++++++++
> arch/arm/dts/k3-am642-r5-evm.dts | 169 ++++++++
> arch/arm/dts/k3-am642.dtsi | 65 +++
> arch/arm/mach-k3/Kconfig | 15 +-
> arch/arm/mach-k3/Makefile | 1 +
> arch/arm/mach-k3/am642_init.c | 283 ++++++++++++
> arch/arm/mach-k3/arm64-mmu.c | 41 ++
> arch/arm/mach-k3/include/mach/am64_hardware.h | 52 +++
> arch/arm/mach-k3/include/mach/am64_spl.h | 44 ++
> arch/arm/mach-k3/include/mach/hardware.h | 4 +
> arch/arm/mach-k3/include/mach/spl.h | 4 +
> board/ti/am64x/Kconfig | 53 +++
> board/ti/am64x/Makefile | 8 +
> board/ti/am64x/evm.c | 48 +++
> configs/am64x_evm_a53_defconfig | 96 +++++
> configs/am64x_evm_r5_defconfig | 91 ++++
> drivers/mailbox/k3-sec-proxy.c | 10 +-
> drivers/mmc/am654_sdhci.c | 18 +
> include/configs/am64x_evm.h | 105 +++++
> include/dt-bindings/pinctrl/k3.h | 5 +-
> 25 files changed, 1988 insertions(+), 14 deletions(-)
> create mode 100644 arch/arm/dts/k3-am64-main.dtsi
> create mode 100644 arch/arm/dts/k3-am64-mcu.dtsi
> create mode 100644 arch/arm/dts/k3-am64.dtsi
> create mode 100644 arch/arm/dts/k3-am642-evm-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-am642-evm.dts
> create mode 100644 arch/arm/dts/k3-am642-r5-evm.dts
> create mode 100644 arch/arm/dts/k3-am642.dtsi
> create mode 100644 arch/arm/mach-k3/am642_init.c
> create mode 100644 arch/arm/mach-k3/include/mach/am64_hardware.h
> create mode 100644 arch/arm/mach-k3/include/mach/am64_spl.h
> create mode 100644 board/ti/am64x/Kconfig
> create mode 100644 board/ti/am64x/Makefile
> create mode 100644 board/ti/am64x/evm.c
> create mode 100644 configs/am64x_evm_a53_defconfig
> create mode 100644 configs/am64x_evm_r5_defconfig
> create mode 100644 include/configs/am64x_evm.h
>
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2021-05-12 13:58 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-23 16:27 [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Dave Gerlach
2021-04-23 16:27 ` [PATCH 01/17] arm: mach-k3: Add basic support for AM642 SoC definition Dave Gerlach
2021-04-23 16:27 ` [PATCH 02/17] arm: mach-k3: am642: Add support for boot device detection Dave Gerlach
2021-04-23 16:27 ` [PATCH 03/17] arm: mach-k3: am642: Unlock all applicable control MMR registers Dave Gerlach
2021-04-23 16:27 ` [PATCH 04/17] arm: mach-k3: am642: Store boot info from ROM Dave Gerlach
2021-04-23 16:27 ` [PATCH 05/17] arm: mach-k3: am642: Load SYSFW binary and config from boot media Dave Gerlach
2021-04-23 16:27 ` [PATCH 06/17] arm: mach-k3: am642: Use mmc start and stop callbacks Dave Gerlach
2021-04-23 16:27 ` [PATCH 07/17] arm: mach-k3: am642: Shut down R5 core after ATF startup on A53 Dave Gerlach
2021-04-23 16:27 ` [PATCH 08/17] armv8: mach-k3: am642: Add custom MMU support Dave Gerlach
2021-04-23 16:27 ` [PATCH 09/17] mmc: sdhci_am654: Add Support for TI's AM642 SoC Dave Gerlach
2021-04-23 16:27 ` [PATCH 10/17] mailbox: k3-sec-proxy: Extend valid thread IDs Dave Gerlach
2021-04-23 16:27 ` [PATCH 11/17] board: ti: am64x: Add board support for am64x evm Dave Gerlach
2021-04-23 16:27 ` [PATCH 12/17] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64 Dave Gerlach
2021-04-23 16:27 ` [PATCH 13/17] arm: dts: ti: Add Support for AM642 SoC Dave Gerlach
2021-04-23 16:27 ` [PATCH 14/17] arm: dts: k3-am642: Add initial support for EVM Dave Gerlach
2021-04-23 16:27 ` [PATCH 15/17] arm: dts: k3-am642: Add r5 specific dt support Dave Gerlach
2021-04-23 16:27 ` [PATCH 16/17] configs: am64x_evm_r5: Add Initial support Dave Gerlach
2021-04-23 16:27 ` [PATCH 17/17] configs: am64x_evm_a53: " Dave Gerlach
2021-05-06 17:54 ` Vignesh Raghavendra
2021-05-07 11:23 ` Vignesh Raghavendra
2021-05-06 8:02 ` [PATCH 00/17] arm: mach-k3: Initial Support for Texas Instruments AM642 Platform Lokesh Vutla
2021-05-06 12:22 ` Lokesh Vutla
2021-05-12 13:58 ` Lokesh Vutla
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