* [PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
v8-resend:
Resending to trigger recheck due to minor codestyle issues.
v8:
Hi folks,
Finally we were able to assign v0.1 draft for Pointer Masking extension for RISC-V: https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc
This is supposed to be the first series of patches with initial support for PM. It obviously misses support for hypervisor mode, vector load/stores and some other features, while using temporary csr numbers(they're to be assigned by the committee a bit later).
With this patch series we were able to run a bunch of tests with HWASAN checks enabled.
I hope I've managed to addressed @Alistair's previous comments in this version.
Thanks!
v7:
Hi folks,
Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY.
This series contains fixed @Alistair suggestion on enabling J-ext.
As for @Richard comments:
- Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first?
- These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular.
If this patch series would be accepted, I think my further attention would be to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned previously
Thanks!
Alexey Baturo (5):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
the h-mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
[RISCV_PM] Allow experimental J-ext to be turned on
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 32 ++++
target/riscv/cpu.h | 34 ++++
target/riscv/cpu_bits.h | 66 +++++++
target/riscv/csr.c | 236 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/translate.c | 42 +++++
9 files changed, 419 insertions(+)
--
2.20.1
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
2021-04-28 4:18 ` Alexey Baturo
@ 2021-04-28 4:18 ` Alexey Baturo
-1 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba..0ea9fc65c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -72,6 +72,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -291,6 +292,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv, Alistair Francis
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a33d387ba..0ea9fc65c8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -72,6 +72,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -291,6 +292,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_counters;
bool ext_ifencei;
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
2021-04-28 4:18 ` Alexey Baturo
@ 2021-04-28 4:18 ` Alexey Baturo
-1 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
resend:
minor codestyle fix
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 12 ++
target/riscv/cpu_bits.h | 66 +++++++++++
target/riscv/csr.c | 240 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 323 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..c04911ec05 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -473,6 +473,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_j) {
+#ifndef CONFIG_USER_ONLY
+ env->mmte |= PM_EXT_INITIAL;
+#endif
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ea9fc65c8..19aa3b4769 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -238,6 +238,18 @@ struct CPURISCVState {
/* True if in debugger mode. */
bool debugger;
+
+ /*
+ * CSRs for PM
+ * TODO: move these csr to appropriate groups
+ */
+ target_ulong mmte;
+ target_ulong mpmmask;
+ target_ulong mpmbase;
+ target_ulong spmmask;
+ target_ulong spmbase;
+ target_ulong upmmask;
+ target_ulong upmbase;
#endif
float_status fp_status;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index caf4599207..f8e7cdb99b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -354,6 +354,21 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Custom user register */
+#define CSR_UMTE 0x8c0
+#define CSR_UPMMASK 0x8c1
+#define CSR_UPMBASE 0x8c2
+
+/* Custom machine register */
+#define CSR_MMTE 0x7c0
+#define CSR_MPMMASK 0x7c1
+#define CSR_MPMBASE 0x7c2
+
+/* Custom supervisor register */
+#define CSR_SMTE 0x9c0
+#define CSR_SPMMASK 0x9c1
+#define CSR_SPMBASE 0x9c2
+
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
@@ -592,4 +607,55 @@
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* general mte CSR bits*/
+#define PM_ENABLE 0x00000001ULL
+#define PM_CURRENT 0x00000002ULL
+#define PM_XS_MASK 0x00000003ULL
+
+/* PM XS bits values */
+#define PM_EXT_DISABLE 0x00000000ULL
+#define PM_EXT_INITIAL 0x00000001ULL
+#define PM_EXT_CLEAN 0x00000002ULL
+#define PM_EXT_DIRTY 0x00000003ULL
+
+/* offsets for every pair of control bits per each priv level */
+#define XS_OFFSET 0ULL
+#define U_OFFSET 2ULL
+#define S_OFFSET 4ULL
+#define M_OFFSET 6ULL
+
+#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
+
+/* mmte CSR bits */
+#define MMTE_PM_XS_BITS PM_XS_BITS
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
+ MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
+
+/* smte CSR bits */
+#define SMTE_PM_XS_BITS PM_XS_BITS
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
+ SMTE_PM_XS_BITS)
+
+/* umte CSR bits */
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..bef65c5ae1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -184,6 +184,39 @@ static int hmode32(CPURISCVState *env, int csrno)
}
+static int umode(CPURISCVState *env, int csrno)
+{
+ return -!riscv_has_ext(env, RVU);
+}
+
+/* Checks if PointerMasking registers could be accessed */
+static int pointer_masking(CPURISCVState *env, int csrno)
+{
+ /* Check if j-ext is present */
+ int j_check = -!riscv_has_ext(env, RVJ);
+ int mode_check = 0;
+ int csr_priv = get_field(csrno, 0x300);
+ /* check if particular mode is present */
+ switch (csr_priv) {
+ case PRV_M:
+ mode_check = any(env, csrno);
+ break;
+ case PRV_S:
+ mode_check = smode(env, csrno);
+ break;
+ case PRV_U:
+ mode_check = umode(env, csrno);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ /* raise fault if no j-ext or particular mode are present */
+ if (j_check < 0) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ return mode_check;
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1263,6 +1296,200 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+/*
+ * Functions to access Pointer Masking feature registers
+ * We have to check if current priv lvl could modify
+ * csr in given mode
+ */
+static int check_pm_current_disabled(CPURISCVState *env, int csrno)
+{
+ int csr_priv = get_field(csrno, 0x300);
+ /*
+ * If priv lvls differ that means we're accessing csr from higher priv lvl,
+ * so allow the access
+ */
+ if (env->priv != csr_priv) {
+ return 0;
+ }
+ int cur_bit_pos;
+ switch (env->priv) {
+ case PRV_M:
+ /* m-mode is always allowed to modify registers, so allow */
+ return 0;
+ case PRV_S:
+ cur_bit_pos = S_PM_CURRENT;
+ break;
+ case PRV_U:
+ cur_bit_pos = U_PM_CURRENT;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ int pm_current = get_field(env->mmte, cur_bit_pos);
+ /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
+ return !pm_current;
+}
+
+static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mmte & MMTE_MASK;
+ return 0;
+}
+
+static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong wpri_val = val & MMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ env->mmte = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mmte & SMTE_MASK;
+ return 0;
+}
+
+static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong wpri_val = val & SMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mmte & UMTE_MASK;
+ return 0;
+}
+
+static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong wpri_val = val & UMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mpmmask;
+ return 0;
+}
+
+static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mpmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->spmmask;
+ return 0;
+}
+
+static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->upmmask;
+ return 0;
+}
+
+static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mpmbase;
+ return 0;
+}
+
+static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mpmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->spmbase;
+ return 0;
+}
+
+static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->upmbase;
+ return 0;
+}
+
+static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
#endif
/*
@@ -1494,6 +1721,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
+ /* User Pointer Masking */
+ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
+ [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
+ [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
+ /* Machine Pointer Masking */
+ [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
+ [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
+ [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
+ /* Supervisor Pointer Masking */
+ [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
+ [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
+ [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
+
/* Performance Counters */
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
resend:
minor codestyle fix
target/riscv/cpu.c | 5 +
target/riscv/cpu.h | 12 ++
target/riscv/cpu_bits.h | 66 +++++++++++
target/riscv/csr.c | 240 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 323 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..c04911ec05 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -473,6 +473,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_j) {
+#ifndef CONFIG_USER_ONLY
+ env->mmte |= PM_EXT_INITIAL;
+#endif
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ea9fc65c8..19aa3b4769 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -238,6 +238,18 @@ struct CPURISCVState {
/* True if in debugger mode. */
bool debugger;
+
+ /*
+ * CSRs for PM
+ * TODO: move these csr to appropriate groups
+ */
+ target_ulong mmte;
+ target_ulong mpmmask;
+ target_ulong mpmbase;
+ target_ulong spmmask;
+ target_ulong spmbase;
+ target_ulong upmmask;
+ target_ulong upmbase;
#endif
float_status fp_status;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index caf4599207..f8e7cdb99b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -354,6 +354,21 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Custom user register */
+#define CSR_UMTE 0x8c0
+#define CSR_UPMMASK 0x8c1
+#define CSR_UPMBASE 0x8c2
+
+/* Custom machine register */
+#define CSR_MMTE 0x7c0
+#define CSR_MPMMASK 0x7c1
+#define CSR_MPMBASE 0x7c2
+
+/* Custom supervisor register */
+#define CSR_SMTE 0x9c0
+#define CSR_SPMMASK 0x9c1
+#define CSR_SPMBASE 0x9c2
+
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
@@ -592,4 +607,55 @@
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* general mte CSR bits*/
+#define PM_ENABLE 0x00000001ULL
+#define PM_CURRENT 0x00000002ULL
+#define PM_XS_MASK 0x00000003ULL
+
+/* PM XS bits values */
+#define PM_EXT_DISABLE 0x00000000ULL
+#define PM_EXT_INITIAL 0x00000001ULL
+#define PM_EXT_CLEAN 0x00000002ULL
+#define PM_EXT_DIRTY 0x00000003ULL
+
+/* offsets for every pair of control bits per each priv level */
+#define XS_OFFSET 0ULL
+#define U_OFFSET 2ULL
+#define S_OFFSET 4ULL
+#define M_OFFSET 6ULL
+
+#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
+
+/* mmte CSR bits */
+#define MMTE_PM_XS_BITS PM_XS_BITS
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
+ MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
+
+/* smte CSR bits */
+#define SMTE_PM_XS_BITS PM_XS_BITS
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
+ SMTE_PM_XS_BITS)
+
+/* umte CSR bits */
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..bef65c5ae1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -184,6 +184,39 @@ static int hmode32(CPURISCVState *env, int csrno)
}
+static int umode(CPURISCVState *env, int csrno)
+{
+ return -!riscv_has_ext(env, RVU);
+}
+
+/* Checks if PointerMasking registers could be accessed */
+static int pointer_masking(CPURISCVState *env, int csrno)
+{
+ /* Check if j-ext is present */
+ int j_check = -!riscv_has_ext(env, RVJ);
+ int mode_check = 0;
+ int csr_priv = get_field(csrno, 0x300);
+ /* check if particular mode is present */
+ switch (csr_priv) {
+ case PRV_M:
+ mode_check = any(env, csrno);
+ break;
+ case PRV_S:
+ mode_check = smode(env, csrno);
+ break;
+ case PRV_U:
+ mode_check = umode(env, csrno);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ /* raise fault if no j-ext or particular mode are present */
+ if (j_check < 0) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ return mode_check;
+}
+
static int pmp(CPURISCVState *env, int csrno)
{
return -!riscv_feature(env, RISCV_FEATURE_PMP);
@@ -1263,6 +1296,200 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+/*
+ * Functions to access Pointer Masking feature registers
+ * We have to check if current priv lvl could modify
+ * csr in given mode
+ */
+static int check_pm_current_disabled(CPURISCVState *env, int csrno)
+{
+ int csr_priv = get_field(csrno, 0x300);
+ /*
+ * If priv lvls differ that means we're accessing csr from higher priv lvl,
+ * so allow the access
+ */
+ if (env->priv != csr_priv) {
+ return 0;
+ }
+ int cur_bit_pos;
+ switch (env->priv) {
+ case PRV_M:
+ /* m-mode is always allowed to modify registers, so allow */
+ return 0;
+ case PRV_S:
+ cur_bit_pos = S_PM_CURRENT;
+ break;
+ case PRV_U:
+ cur_bit_pos = U_PM_CURRENT;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ int pm_current = get_field(env->mmte, cur_bit_pos);
+ /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
+ return !pm_current;
+}
+
+static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mmte & MMTE_MASK;
+ return 0;
+}
+
+static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong wpri_val = val & MMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ env->mmte = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mmte & SMTE_MASK;
+ return 0;
+}
+
+static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong wpri_val = val & SMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mmte & UMTE_MASK;
+ return 0;
+}
+
+static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ target_ulong wpri_val = val & UMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mpmmask;
+ return 0;
+}
+
+static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mpmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->spmmask;
+ return 0;
+}
+
+static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->upmmask;
+ return 0;
+}
+
+static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mpmbase;
+ return 0;
+}
+
+static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mpmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->spmbase;
+ return 0;
+}
+
+static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->upmbase;
+ return 0;
+}
+
+static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
#endif
/*
@@ -1494,6 +1721,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
+ /* User Pointer Masking */
+ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
+ [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
+ [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
+ /* Machine Pointer Masking */
+ [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
+ [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
+ [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
+ /* Supervisor Pointer Masking */
+ [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
+ [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
+ [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
+
/* Performance Counters */
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode
2021-04-28 4:18 ` Alexey Baturo
(?)
@ 2021-05-12 5:54 ` Alistair Francis
-1 siblings, 0 replies; 18+ messages in thread
From: Alistair Francis @ 2021-05-12 5:54 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, Dave Smith,
Palmer Dabbelt
On Wed, Apr 28, 2021 at 2:19 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> resend:
> minor codestyle fix
>
> target/riscv/cpu.c | 5 +
> target/riscv/cpu.h | 12 ++
> target/riscv/cpu_bits.h | 66 +++++++++++
> target/riscv/csr.c | 240 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 323 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7d6ed80f6b..c04911ec05 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -473,6 +473,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> if (cpu->cfg.ext_h) {
> target_misa |= RVH;
> }
> + if (cpu->cfg.ext_j) {
> +#ifndef CONFIG_USER_ONLY
> + env->mmte |= PM_EXT_INITIAL;
> +#endif
> + }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0ea9fc65c8..19aa3b4769 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -238,6 +238,18 @@ struct CPURISCVState {
>
> /* True if in debugger mode. */
> bool debugger;
> +
> + /*
> + * CSRs for PM
> + * TODO: move these csr to appropriate groups
> + */
> + target_ulong mmte;
> + target_ulong mpmmask;
> + target_ulong mpmbase;
> + target_ulong spmmask;
> + target_ulong spmbase;
> + target_ulong upmmask;
> + target_ulong upmbase;
> #endif
>
> float_status fp_status;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index caf4599207..f8e7cdb99b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -354,6 +354,21 @@
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
>
> +/* Custom user register */
> +#define CSR_UMTE 0x8c0
> +#define CSR_UPMMASK 0x8c1
> +#define CSR_UPMBASE 0x8c2
> +
> +/* Custom machine register */
> +#define CSR_MMTE 0x7c0
> +#define CSR_MPMMASK 0x7c1
> +#define CSR_MPMBASE 0x7c2
> +
> +/* Custom supervisor register */
> +#define CSR_SMTE 0x9c0
> +#define CSR_SPMMASK 0x9c1
> +#define CSR_SPMBASE 0x9c2
I don't like that the addresses aren't specified anywhere. Do you know
when they will be decided?
> +
> /* Legacy Machine Protection and Translation (priv v1.9.1) */
> #define CSR_MBASE 0x380
> #define CSR_MBOUND 0x381
> @@ -592,4 +607,55 @@
> #define MIE_UTIE (1 << IRQ_U_TIMER)
> #define MIE_SSIE (1 << IRQ_S_SOFT)
> #define MIE_USIE (1 << IRQ_U_SOFT)
> +
> +/* general mte CSR bits*/
> +#define PM_ENABLE 0x00000001ULL
> +#define PM_CURRENT 0x00000002ULL
> +#define PM_XS_MASK 0x00000003ULL
> +
> +/* PM XS bits values */
> +#define PM_EXT_DISABLE 0x00000000ULL
> +#define PM_EXT_INITIAL 0x00000001ULL
> +#define PM_EXT_CLEAN 0x00000002ULL
> +#define PM_EXT_DIRTY 0x00000003ULL
> +
> +/* offsets for every pair of control bits per each priv level */
> +#define XS_OFFSET 0ULL
> +#define U_OFFSET 2ULL
> +#define S_OFFSET 4ULL
> +#define M_OFFSET 6ULL
> +
> +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
> +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
> +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
> +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
> +
> +/* mmte CSR bits */
> +#define MMTE_PM_XS_BITS PM_XS_BITS
> +#define MMTE_U_PM_ENABLE U_PM_ENABLE
> +#define MMTE_U_PM_CURRENT U_PM_CURRENT
> +#define MMTE_S_PM_ENABLE S_PM_ENABLE
> +#define MMTE_S_PM_CURRENT S_PM_CURRENT
> +#define MMTE_M_PM_ENABLE M_PM_ENABLE
> +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
> + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
> + MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
> +
> +/* smte CSR bits */
> +#define SMTE_PM_XS_BITS PM_XS_BITS
> +#define SMTE_U_PM_ENABLE U_PM_ENABLE
> +#define SMTE_U_PM_CURRENT U_PM_CURRENT
> +#define SMTE_S_PM_ENABLE S_PM_ENABLE
> +#define SMTE_S_PM_CURRENT S_PM_CURRENT
> +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
> + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
> + SMTE_PM_XS_BITS)
> +
> +/* umte CSR bits */
> +#define UMTE_U_PM_ENABLE U_PM_ENABLE
> +#define UMTE_U_PM_CURRENT U_PM_CURRENT
> +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
> +
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d2585395bf..bef65c5ae1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -184,6 +184,39 @@ static int hmode32(CPURISCVState *env, int csrno)
>
> }
>
> +static int umode(CPURISCVState *env, int csrno)
> +{
> + return -!riscv_has_ext(env, RVU);
> +}
> +
> +/* Checks if PointerMasking registers could be accessed */
> +static int pointer_masking(CPURISCVState *env, int csrno)
> +{
> + /* Check if j-ext is present */
> + int j_check = -!riscv_has_ext(env, RVJ);
> + int mode_check = 0;
> + int csr_priv = get_field(csrno, 0x300);
> + /* check if particular mode is present */
> + switch (csr_priv) {
> + case PRV_M:
> + mode_check = any(env, csrno);
> + break;
> + case PRV_S:
> + mode_check = smode(env, csrno);
> + break;
> + case PRV_U:
> + mode_check = umode(env, csrno);
> + break;
> + default:
Can't we just use the generic check based on the CSR address?
Then this will be a simple `riscv_has_ext(env, RVJ)` check.
Alistair
> + g_assert_not_reached();
> + }
> + /* raise fault if no j-ext or particular mode are present */
> + if (j_check < 0) {
> + return -RISCV_EXCP_ILLEGAL_INST;
> + }
> + return mode_check;
> +}
> +
> static int pmp(CPURISCVState *env, int csrno)
> {
> return -!riscv_feature(env, RISCV_FEATURE_PMP);
> @@ -1263,6 +1296,200 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
> return 0;
> }
>
> +/*
> + * Functions to access Pointer Masking feature registers
> + * We have to check if current priv lvl could modify
> + * csr in given mode
> + */
> +static int check_pm_current_disabled(CPURISCVState *env, int csrno)
> +{
> + int csr_priv = get_field(csrno, 0x300);
> + /*
> + * If priv lvls differ that means we're accessing csr from higher priv lvl,
> + * so allow the access
> + */
> + if (env->priv != csr_priv) {
> + return 0;
> + }
> + int cur_bit_pos;
> + switch (env->priv) {
> + case PRV_M:
> + /* m-mode is always allowed to modify registers, so allow */
> + return 0;
> + case PRV_S:
> + cur_bit_pos = S_PM_CURRENT;
> + break;
> + case PRV_U:
> + cur_bit_pos = U_PM_CURRENT;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + int pm_current = get_field(env->mmte, cur_bit_pos);
> + /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
> + return !pm_current;
> +}
> +
> +static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mmte & MMTE_MASK;
> + return 0;
> +}
> +
> +static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + target_ulong wpri_val = val & MMTE_MASK;
> + if (val != wpri_val) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
> + val, wpri_val);
> + }
> + env->mmte = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mmte & SMTE_MASK;
> + return 0;
> +}
> +
> +static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + target_ulong wpri_val = val & SMTE_MASK;
> + if (val != wpri_val) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
> + val, wpri_val);
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
> + write_mmte(env, csrno, new_val);
> + return 0;
> +}
> +
> +static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mmte & UMTE_MASK;
> + return 0;
> +}
> +
> +static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + target_ulong wpri_val = val & UMTE_MASK;
> + if (val != wpri_val) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
> + val, wpri_val);
> + }
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
> + write_mmte(env, csrno, new_val);
> + return 0;
> +}
> +
> +static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mpmmask;
> + return 0;
> +}
> +
> +static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->mpmmask = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->spmmask;
> + return 0;
> +}
> +
> +static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->spmmask = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->upmmask;
> + return 0;
> +}
> +
> +static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->upmmask = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mpmbase;
> + return 0;
> +}
> +
> +static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->mpmbase = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->spmbase;
> + return 0;
> +}
> +
> +static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->spmbase = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> +static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->upmbase;
> + return 0;
> +}
> +
> +static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (check_pm_current_disabled(env, csrno)) {
> + return 0;
> + }
> + env->upmbase = val;
> + env->mstatus |= MSTATUS_XS | MSTATUS_SD;
> + env->mmte |= PM_EXT_DIRTY;
> + return 0;
> +}
> +
> #endif
>
> /*
> @@ -1494,6 +1721,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
> [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
>
> + /* User Pointer Masking */
> + [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
> + [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
> + [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
> + /* Machine Pointer Masking */
> + [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
> + [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
> + [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
> + /* Supervisor Pointer Masking */
> + [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
> + [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
> + [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
> +
> /* Performance Counters */
> [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
> [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
2021-04-28 4:18 ` Alexey Baturo
@ 2021-04-28 4:18 ` Alexey Baturo
-1 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c04911ec05..0682410f5d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ if (riscv_has_ext(env, RVJ)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ switch (env->priv) {
+ case PRV_U:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+ env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+ env->upmmask);
+ break;
+ case PRV_S:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+ env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+ env->spmmask);
+ break;
+ case PRV_M:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+ env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+ env->mpmmask);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv, Alistair Francis
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c04911ec05..0682410f5d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -287,6 +287,31 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ if (riscv_has_ext(env, RVJ)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ switch (env->priv) {
+ case PRV_U:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
+ env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
+ env->upmmask);
+ break;
+ case PRV_S:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
+ env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
+ env->spmmask);
+ break;
+ case PRV_M:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
+ env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
+ env->mpmmask);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
2021-04-28 4:18 ` Alexey Baturo
@ 2021-04-28 4:18 ` Alexey Baturo
-1 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
target/riscv/translate.c | 10 ++++++++++
5 files changed, 19 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..5559e347ba 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l2 = gen_new_label();
gen_get_gpr(src1, a->rs1);
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
gen_get_gpr(src2, a->rs2);
@@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
gen_get_gpr(src1, a->rs1);
gen_get_gpr(src2, a->rs2);
+ gen_pm_adjust_address(ctx, src1, src1);
(*func)(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(a->rd, src2);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 4f832637fa..935342f66d 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 3dfec8211d..04b3c3eb3d 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
@@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..bee7f6be46 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
gen_set_gpr(a->rd, t1);
@@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
gen_get_gpr(dat, a->rs2);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2f9f5ccc62..2e815a5912 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -89,6 +89,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
+/*
+ * Temp stub: generates address adjustment for PointerMasking
+ */
+static void gen_pm_adjust_address(DisasContext *s,
+ TCGv_i64 dst,
+ TCGv_i64 src)
+{
+ tcg_gen_mov_i64(dst, src);
+}
+
/*
* A narrow n-bit operation, where n < FLEN, checks that input operands
* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv, Alistair Francis
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
target/riscv/translate.c | 10 ++++++++++
5 files changed, 19 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..5559e347ba 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -26,6 +26,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -46,6 +47,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l2 = gen_new_label();
gen_get_gpr(src1, a->rs1);
+ gen_pm_adjust_address(ctx, src1, src1);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
gen_get_gpr(src2, a->rs2);
@@ -91,6 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
gen_get_gpr(src1, a->rs1);
gen_get_gpr(src2, a->rs2);
+ gen_pm_adjust_address(ctx, src1, src1);
(*func)(src2, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(a->rd, src2);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 4f832637fa..935342f66d 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -25,6 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -40,6 +41,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index 3dfec8211d..04b3c3eb3d 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,6 +30,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
@@ -47,6 +48,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..bee7f6be46 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -141,6 +141,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
TCGv t1 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
gen_set_gpr(a->rd, t1);
@@ -180,6 +181,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
TCGv dat = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
+ gen_pm_adjust_address(ctx, t0, t0);
gen_get_gpr(dat, a->rs2);
tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2f9f5ccc62..2e815a5912 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -89,6 +89,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
+/*
+ * Temp stub: generates address adjustment for PointerMasking
+ */
+static void gen_pm_adjust_address(DisasContext *s,
+ TCGv_i64 dst,
+ TCGv_i64 src)
+{
+ tcg_gen_mov_i64(dst, src);
+}
+
/*
* A narrow n-bit operation, where n < FLEN, checks that input operands
* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
2021-04-28 4:18 ` Alexey Baturo
@ 2021-04-28 4:18 ` Alexey Baturo
-1 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair.Francis,
kupokupokupopo, palmer
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 20 ++++++++++++++++++++
target/riscv/translate.c | 36 ++++++++++++++++++++++++++++++++++--
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 19aa3b4769..2edfc59712 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -407,6 +407,8 @@ FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+/* If PointerMasking should be applied */
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -464,6 +466,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+ if (riscv_has_ext(env, RVJ)) {
+ int priv = cpu_mmu_index(env, false);
+ bool pm_enabled = false;
+ switch (priv) {
+ case PRV_U:
+ pm_enabled = env->mmte & U_PM_ENABLE;
+ break;
+ case PRV_S:
+ pm_enabled = env->mmte & S_PM_ENABLE;
+ break;
+ case PRV_M:
+ pm_enabled = env->mmte & M_PM_ENABLE;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2e815a5912..37706d56d5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
#include "exec/gen-icount.h"
@@ -64,6 +67,10 @@ typedef struct DisasContext {
uint16_t vlen;
uint16_t mlen;
bool vl_eq_vlmax;
+ /* PointerMasking extension */
+ bool pm_enabled;
+ TCGv pm_mask;
+ TCGv pm_base;
CPUState *cs;
} DisasContext;
@@ -90,13 +97,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
}
/*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
*/
static void gen_pm_adjust_address(DisasContext *s,
TCGv_i64 dst,
TCGv_i64 src)
{
- tcg_gen_mov_i64(dst, src);
+ if (!s->pm_enabled) {
+ /* Load unmodified address */
+ tcg_gen_mov_i64(dst, src);
+ } else {
+ tcg_gen_andc_i64(dst, src, s->pm_mask);
+ tcg_gen_or_i64(dst, dst, s->pm_base);
+ }
}
/*
@@ -657,6 +670,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
+ ctx->pm_mask = pm_mask[priv];
+ ctx->pm_base = pm_base[priv];
ctx->cs = cs;
}
@@ -777,4 +794,19 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
+#ifndef CONFIG_USER_ONLY
+ /* Assign PM CSRs to tcg globals */
+ pm_mask[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+ pm_base[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+ pm_mask[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+ pm_base[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+ pm_mask[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+ pm_base[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
+#endif
}
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 20 ++++++++++++++++++++
target/riscv/translate.c | 36 ++++++++++++++++++++++++++++++++++--
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 19aa3b4769..2edfc59712 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -407,6 +407,8 @@ FIELD(TB_FLAGS, SEW, 5, 3)
FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
+/* If PointerMasking should be applied */
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -464,6 +466,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+ if (riscv_has_ext(env, RVJ)) {
+ int priv = cpu_mmu_index(env, false);
+ bool pm_enabled = false;
+ switch (priv) {
+ case PRV_U:
+ pm_enabled = env->mmte & U_PM_ENABLE;
+ break;
+ case PRV_S:
+ pm_enabled = env->mmte & S_PM_ENABLE;
+ break;
+ case PRV_M:
+ pm_enabled = env->mmte & M_PM_ENABLE;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2e815a5912..37706d56d5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
#include "exec/gen-icount.h"
@@ -64,6 +67,10 @@ typedef struct DisasContext {
uint16_t vlen;
uint16_t mlen;
bool vl_eq_vlmax;
+ /* PointerMasking extension */
+ bool pm_enabled;
+ TCGv pm_mask;
+ TCGv pm_base;
CPUState *cs;
} DisasContext;
@@ -90,13 +97,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
}
/*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
*/
static void gen_pm_adjust_address(DisasContext *s,
TCGv_i64 dst,
TCGv_i64 src)
{
- tcg_gen_mov_i64(dst, src);
+ if (!s->pm_enabled) {
+ /* Load unmodified address */
+ tcg_gen_mov_i64(dst, src);
+ } else {
+ tcg_gen_andc_i64(dst, src, s->pm_mask);
+ tcg_gen_or_i64(dst, dst, s->pm_base);
+ }
}
/*
@@ -657,6 +670,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
+ ctx->pm_mask = pm_mask[priv];
+ ctx->pm_base = pm_base[priv];
ctx->cs = cs;
}
@@ -777,4 +794,19 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
+#ifndef CONFIG_USER_ONLY
+ /* Assign PM CSRs to tcg globals */
+ pm_mask[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+ pm_base[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+ pm_mask[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+ pm_base[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+ pm_mask[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+ pm_base[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
+#endif
}
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
2021-04-28 4:18 ` Alexey Baturo
(?)
@ 2021-05-12 5:59 ` Alistair Francis
-1 siblings, 0 replies; 18+ messages in thread
From: Alistair Francis @ 2021-05-12 5:59 UTC (permalink / raw)
To: Alexey Baturo
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Richard Henderson, qemu-devel@nongnu.org Developers,
space.monkey.delivers, Alistair Francis, Dave Smith,
Palmer Dabbelt
On Wed, Apr 28, 2021 at 2:23 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
>
> Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 20 ++++++++++++++++++++
> target/riscv/translate.c | 36 ++++++++++++++++++++++++++++++++++--
> 2 files changed, 54 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 19aa3b4769..2edfc59712 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -407,6 +407,8 @@ FIELD(TB_FLAGS, SEW, 5, 3)
> FIELD(TB_FLAGS, VILL, 8, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> FIELD(TB_FLAGS, HLSX, 9, 1)
> +/* If PointerMasking should be applied */
> +FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
>
> bool riscv_cpu_is_32bit(CPURISCVState *env);
>
> @@ -464,6 +466,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
> }
> }
> + if (riscv_has_ext(env, RVJ)) {
> + int priv = cpu_mmu_index(env, false);
You will want to and this with TB_FLAGS_PRIV_MMU_MASK
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> + bool pm_enabled = false;
> + switch (priv) {
> + case PRV_U:
> + pm_enabled = env->mmte & U_PM_ENABLE;
> + break;
> + case PRV_S:
> + pm_enabled = env->mmte & S_PM_ENABLE;
> + break;
> + case PRV_M:
> + pm_enabled = env->mmte & M_PM_ENABLE;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
> + }
> #endif
>
> *pflags = flags;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 2e815a5912..37706d56d5 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
> static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> +/* globals for PM CSRs */
> +static TCGv pm_mask[4];
> +static TCGv pm_base[4];
>
> #include "exec/gen-icount.h"
>
> @@ -64,6 +67,10 @@ typedef struct DisasContext {
> uint16_t vlen;
> uint16_t mlen;
> bool vl_eq_vlmax;
> + /* PointerMasking extension */
> + bool pm_enabled;
> + TCGv pm_mask;
> + TCGv pm_base;
> CPUState *cs;
> } DisasContext;
>
> @@ -90,13 +97,19 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> }
>
> /*
> - * Temp stub: generates address adjustment for PointerMasking
> + * Generates address adjustment for PointerMasking
> */
> static void gen_pm_adjust_address(DisasContext *s,
> TCGv_i64 dst,
> TCGv_i64 src)
> {
> - tcg_gen_mov_i64(dst, src);
> + if (!s->pm_enabled) {
> + /* Load unmodified address */
> + tcg_gen_mov_i64(dst, src);
> + } else {
> + tcg_gen_andc_i64(dst, src, s->pm_mask);
> + tcg_gen_or_i64(dst, dst, s->pm_base);
> + }
> }
>
> /*
> @@ -657,6 +670,10 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
> ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> + ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> + int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
> + ctx->pm_mask = pm_mask[priv];
> + ctx->pm_base = pm_base[priv];
> ctx->cs = cs;
> }
>
> @@ -777,4 +794,19 @@ void riscv_translate_init(void)
> "load_res");
> load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
> "load_val");
> +#ifndef CONFIG_USER_ONLY
> + /* Assign PM CSRs to tcg globals */
> + pm_mask[PRV_U] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
> + pm_base[PRV_U] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
> + pm_mask[PRV_S] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
> + pm_base[PRV_S] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
> + pm_mask[PRV_M] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
> + pm_base[PRV_M] =
> + tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
> +#endif
> }
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
2021-04-28 4:18 ` Alexey Baturo
@ 2021-04-28 4:18 ` Alexey Baturo
-1 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, qemu-riscv, sagark, kbastian, richard.henderson,
qemu-devel, space.monkey.delivers, Alistair Francis,
kupokupokupopo, palmer
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0682410f5d..fecc64d7ba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -502,6 +502,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
env->mmte |= PM_EXT_INITIAL;
#endif
+ target_misa |= RVJ;
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -574,6 +575,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
@ 2021-04-28 4:18 ` Alexey Baturo
0 siblings, 0 replies; 18+ messages in thread
From: Alexey Baturo @ 2021-04-28 4:18 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, space.monkey.delivers,
kupokupokupopo, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv, Alistair Francis
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0682410f5d..fecc64d7ba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -502,6 +502,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
env->mmte |= PM_EXT_INITIAL;
#endif
+ target_misa |= RVJ;
}
if (cpu->cfg.ext_v) {
target_misa |= RVV;
@@ -574,6 +575,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
--
2.20.1
^ permalink raw reply related [flat|nested] 18+ messages in thread