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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Rob Herring <robh+dt@kernel.org>,
	Magnus Damm <magnus.damm@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-serial@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>
Subject: [PATCH 12/16] clk: renesas: Define RZ/G2L CPG Clock Definitions
Date: Fri, 14 May 2021 20:22:14 +0100	[thread overview]
Message-ID: <20210514192218.13022-13-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20210514192218.13022-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 include/dt-bindings/clock/r9a07g044l-cpg.h | 89 ++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 include/dt-bindings/clock/r9a07g044l-cpg.h

diff --git a/include/dt-bindings/clock/r9a07g044l-cpg.h b/include/dt-bindings/clock/r9a07g044l-cpg.h
new file mode 100644
index 000000000000..2bc13f4e575b
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g044l-cpg.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G044 CPG Core Clocks */
+#define R9A07G044_CLK_I			0
+#define R9A07G044_CLK_I2		1
+#define R9A07G044_CLK_G			2
+#define R9A07G044_CLK_S0		3
+#define R9A07G044_CLK_S1		4
+#define R9A07G044_CLK_SPI0		5
+#define R9A07G044_CLK_SPI1		6
+#define R9A07G044_CLK_SD0		7
+#define R9A07G044_CLK_SD1		8
+#define R9A07G044_CLK_M0		9
+#define R9A07G044_CLK_M1		10
+#define R9A07G044_CLK_M2		11
+#define R9A07G044_CLK_M3		12
+#define R9A07G044_CLK_M4		13
+#define R9A07G044_CLK_HP		14
+#define R9A07G044_CLK_TSU		15
+#define R9A07G044_CLK_ZT		16
+#define R9A07G044_CLK_P0		17
+#define R9A07G044_CLK_P1		18
+#define R9A07G044_CLK_P2		19
+#define R9A07G044_CLK_AT		20
+#define R9A07G044_OSCCLK		21
+
+/* R9A07G044 Module Clocks */
+#define R9A07G044_CLK_GIC600		0
+#define R9A07G044_CLK_IA55		1
+#define R9A07G044_CLK_SYC		2
+#define R9A07G044_CLK_DMAC		3
+#define R9A07G044_CLK_SYSC		4
+#define R9A07G044_CLK_MTU		5
+#define R9A07G044_CLK_GPT		6
+#define R9A07G044_CLK_ETH0		7
+#define R9A07G044_CLK_ETH1		8
+#define R9A07G044_CLK_I2C0		9
+#define R9A07G044_CLK_I2C1		10
+#define R9A07G044_CLK_I2C2		11
+#define R9A07G044_CLK_I2C3		12
+#define R9A07G044_CLK_SCIF0		13
+#define R9A07G044_CLK_SCIF1		14
+#define R9A07G044_CLK_SCIF2		15
+#define R9A07G044_CLK_SCIF3		16
+#define R9A07G044_CLK_SCIF4		17
+#define R9A07G044_CLK_SCI0		18
+#define R9A07G044_CLK_SCI1		19
+#define R9A07G044_CLK_GPIO		20
+#define R9A07G044_CLK_SDHI0		21
+#define R9A07G044_CLK_SDHI1		22
+#define R9A07G044_CLK_USB0		23
+#define R9A07G044_CLK_USB1		24
+#define R9A07G044_CLK_CANFD		25
+#define R9A07G044_CLK_SSI0		26
+#define R9A07G044_CLK_SSI1		27
+#define R9A07G044_CLK_SSI2		28
+#define R9A07G044_CLK_SSI3		29
+#define R9A07G044_CLK_MHU		30
+#define R9A07G044_CLK_OSTM0		31
+#define R9A07G044_CLK_OSTM1		32
+#define R9A07G044_CLK_OSTM2		33
+#define R9A07G044_CLK_WDT0		34
+#define R9A07G044_CLK_WDT1		35
+#define R9A07G044_CLK_WDT2		36
+#define R9A07G044_CLK_WDT_PON		37
+#define R9A07G044_CLK_GPU		38
+#define R9A07G044_CLK_ISU		39
+#define R9A07G044_CLK_H264		40
+#define R9A07G044_CLK_CRU		41
+#define R9A07G044_CLK_MIPI_DSI		42
+#define R9A07G044_CLK_LCDC		43
+#define R9A07G044_CLK_SRC		44
+#define R9A07G044_CLK_RSPI0		45
+#define R9A07G044_CLK_RSPI1		46
+#define R9A07G044_CLK_RSPI2		47
+#define R9A07G044_CLK_ADC		48
+#define R9A07G044_CLK_TSU_PCLK		49
+#define R9A07G044_CLK_SPI		50
+#define R9A07G044_CLK_MIPI_DSI_V	51
+#define R9A07G044_CLK_MIPI_DSI_PIN	52
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
-- 
2.17.1


WARNING: multiple messages have this Message-ID
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Rob Herring <robh+dt@kernel.org>,
	Magnus Damm <magnus.damm@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-serial@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>
Subject: [PATCH 12/16] clk: renesas: Define RZ/G2L CPG Clock Definitions
Date: Fri, 14 May 2021 20:22:14 +0100	[thread overview]
Message-ID: <20210514192218.13022-13-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20210514192218.13022-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 include/dt-bindings/clock/r9a07g044l-cpg.h | 89 ++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 include/dt-bindings/clock/r9a07g044l-cpg.h

diff --git a/include/dt-bindings/clock/r9a07g044l-cpg.h b/include/dt-bindings/clock/r9a07g044l-cpg.h
new file mode 100644
index 000000000000..2bc13f4e575b
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g044l-cpg.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G044 CPG Core Clocks */
+#define R9A07G044_CLK_I			0
+#define R9A07G044_CLK_I2		1
+#define R9A07G044_CLK_G			2
+#define R9A07G044_CLK_S0		3
+#define R9A07G044_CLK_S1		4
+#define R9A07G044_CLK_SPI0		5
+#define R9A07G044_CLK_SPI1		6
+#define R9A07G044_CLK_SD0		7
+#define R9A07G044_CLK_SD1		8
+#define R9A07G044_CLK_M0		9
+#define R9A07G044_CLK_M1		10
+#define R9A07G044_CLK_M2		11
+#define R9A07G044_CLK_M3		12
+#define R9A07G044_CLK_M4		13
+#define R9A07G044_CLK_HP		14
+#define R9A07G044_CLK_TSU		15
+#define R9A07G044_CLK_ZT		16
+#define R9A07G044_CLK_P0		17
+#define R9A07G044_CLK_P1		18
+#define R9A07G044_CLK_P2		19
+#define R9A07G044_CLK_AT		20
+#define R9A07G044_OSCCLK		21
+
+/* R9A07G044 Module Clocks */
+#define R9A07G044_CLK_GIC600		0
+#define R9A07G044_CLK_IA55		1
+#define R9A07G044_CLK_SYC		2
+#define R9A07G044_CLK_DMAC		3
+#define R9A07G044_CLK_SYSC		4
+#define R9A07G044_CLK_MTU		5
+#define R9A07G044_CLK_GPT		6
+#define R9A07G044_CLK_ETH0		7
+#define R9A07G044_CLK_ETH1		8
+#define R9A07G044_CLK_I2C0		9
+#define R9A07G044_CLK_I2C1		10
+#define R9A07G044_CLK_I2C2		11
+#define R9A07G044_CLK_I2C3		12
+#define R9A07G044_CLK_SCIF0		13
+#define R9A07G044_CLK_SCIF1		14
+#define R9A07G044_CLK_SCIF2		15
+#define R9A07G044_CLK_SCIF3		16
+#define R9A07G044_CLK_SCIF4		17
+#define R9A07G044_CLK_SCI0		18
+#define R9A07G044_CLK_SCI1		19
+#define R9A07G044_CLK_GPIO		20
+#define R9A07G044_CLK_SDHI0		21
+#define R9A07G044_CLK_SDHI1		22
+#define R9A07G044_CLK_USB0		23
+#define R9A07G044_CLK_USB1		24
+#define R9A07G044_CLK_CANFD		25
+#define R9A07G044_CLK_SSI0		26
+#define R9A07G044_CLK_SSI1		27
+#define R9A07G044_CLK_SSI2		28
+#define R9A07G044_CLK_SSI3		29
+#define R9A07G044_CLK_MHU		30
+#define R9A07G044_CLK_OSTM0		31
+#define R9A07G044_CLK_OSTM1		32
+#define R9A07G044_CLK_OSTM2		33
+#define R9A07G044_CLK_WDT0		34
+#define R9A07G044_CLK_WDT1		35
+#define R9A07G044_CLK_WDT2		36
+#define R9A07G044_CLK_WDT_PON		37
+#define R9A07G044_CLK_GPU		38
+#define R9A07G044_CLK_ISU		39
+#define R9A07G044_CLK_H264		40
+#define R9A07G044_CLK_CRU		41
+#define R9A07G044_CLK_MIPI_DSI		42
+#define R9A07G044_CLK_LCDC		43
+#define R9A07G044_CLK_SRC		44
+#define R9A07G044_CLK_RSPI0		45
+#define R9A07G044_CLK_RSPI1		46
+#define R9A07G044_CLK_RSPI2		47
+#define R9A07G044_CLK_ADC		48
+#define R9A07G044_CLK_TSU_PCLK		49
+#define R9A07G044_CLK_SPI		50
+#define R9A07G044_CLK_MIPI_DSI_V	51
+#define R9A07G044_CLK_MIPI_DSI_PIN	52
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
-- 
2.17.1


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  parent reply	other threads:[~2021-05-14 19:24 UTC|newest]

Thread overview: 108+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-14 19:22 [PATCH 00/16] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad Prabhakar
2021-05-14 19:22 ` Lad Prabhakar
2021-05-14 19:22 ` [PATCH 01/16] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-18  1:31   ` Rob Herring
2021-05-18  1:31     ` Rob Herring
2021-05-21 13:22   ` Geert Uytterhoeven
2021-05-21 13:22     ` Geert Uytterhoeven
2021-05-21 16:54     ` Lad, Prabhakar
2021-05-21 16:54       ` Lad, Prabhakar
2021-05-27 11:29       ` Geert Uytterhoeven
2021-05-27 11:29         ` Geert Uytterhoeven
2021-05-27 11:47         ` Lad, Prabhakar
2021-05-27 11:47           ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Lad Prabhakar
2021-05-14 19:22   ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L, LC} " Lad Prabhakar
2021-05-18  1:31   ` Rob Herring
2021-05-18  1:31     ` Rob Herring
2021-05-21 13:23   ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} " Geert Uytterhoeven
2021-05-21 13:23     ` Geert Uytterhoeven
2021-05-21 17:09     ` Lad, Prabhakar
2021-05-21 17:09       ` Lad, Prabhakar
2021-05-27 11:28       ` Geert Uytterhoeven
2021-05-27 11:28         ` Geert Uytterhoeven
2021-05-27 11:49         ` Lad, Prabhakar
2021-05-27 11:49           ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 03/16] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-18  1:32   ` Rob Herring
2021-05-18  1:32     ` Rob Herring
2021-05-21 13:24   ` Geert Uytterhoeven
2021-05-21 13:24     ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's Lad Prabhakar
2021-05-14 19:22   ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} for the new RZ/G2{L, LC} SoC's Lad Prabhakar
2021-05-21 13:25   ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's Geert Uytterhoeven
2021-05-21 13:25     ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Geert Uytterhoeven
2021-05-21 17:21     ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} " Lad, Prabhakar
2021-05-21 17:21       ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Lad, Prabhakar
2021-05-27 11:47       ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} " Geert Uytterhoeven
2021-05-27 11:47         ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 05/16] arm64: defconfig: Enable ARCH_R9A07G044{L,LC} Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-14 19:22 ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Lad Prabhakar
2021-05-14 19:22   ` [PATCH 06/16] dt-bindings: arm: renesas, prr: Add new compatible string for RZ/G{L, LC, UL} Lad Prabhakar
2021-05-18  1:33   ` Rob Herring
2021-05-18  1:33     ` Rob Herring
2021-05-21 13:25   ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Geert Uytterhoeven
2021-05-21 13:25     ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 07/16] soc: renesas: Add support to read LSI DEVID register Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-14 19:22 ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L,LC} SoC's Lad Prabhakar
2021-05-14 19:22   ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L, LC} SoC's Lad Prabhakar
2021-05-14 19:22 ` [PATCH 09/16] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings Lad Prabhakar
2021-05-14 19:22   ` [PATCH 09/16] dt-bindings: serial: renesas, scif: " Lad Prabhakar
2021-05-18  1:33   ` Rob Herring
2021-05-18  1:33     ` Rob Herring
2021-05-21 13:26   ` [PATCH 09/16] dt-bindings: serial: renesas,scif: " Geert Uytterhoeven
2021-05-21 13:26     ` Geert Uytterhoeven
2021-05-21 15:15     ` Geert Uytterhoeven
2021-05-21 15:15       ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 10/16] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-21 13:26   ` Geert Uytterhoeven
2021-05-21 13:26     ` Geert Uytterhoeven
2021-05-14 19:22 ` [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-18  1:35   ` Rob Herring
2021-05-18  1:35     ` Rob Herring
2021-05-21 15:04   ` Geert Uytterhoeven
2021-05-21 15:04     ` Geert Uytterhoeven
2021-05-21 18:42     ` Lad, Prabhakar
2021-05-21 18:42       ` Lad, Prabhakar
2021-05-27 11:51       ` Geert Uytterhoeven
2021-05-27 11:51         ` Geert Uytterhoeven
2021-05-14 19:22 ` Lad Prabhakar [this message]
2021-05-14 19:22   ` [PATCH 12/16] clk: renesas: Define RZ/G2L CPG Clock Definitions Lad Prabhakar
2021-05-21 15:03   ` Geert Uytterhoeven
2021-05-21 15:03     ` Geert Uytterhoeven
2021-05-21 15:19   ` Geert Uytterhoeven
2021-05-21 15:19     ` Geert Uytterhoeven
2021-05-21 18:37     ` Lad, Prabhakar
2021-05-21 18:37       ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-21 15:02   ` Geert Uytterhoeven
2021-05-21 15:02     ` Geert Uytterhoeven
2021-05-27 12:04   ` Geert Uytterhoeven
2021-05-27 12:04     ` Geert Uytterhoeven
2021-05-28  7:51     ` Lad, Prabhakar
2021-05-28  7:51       ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 14/16] clk: renesas: Add support for R9A07G044L SoC Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-14 19:22 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar
2021-05-14 19:22   ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L, LC} SoC's Lad Prabhakar
2021-05-21 15:35   ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Geert Uytterhoeven
2021-05-21 15:35     ` Geert Uytterhoeven
2021-05-21 18:36     ` Lad, Prabhakar
2021-05-21 18:36       ` Lad, Prabhakar
2021-05-27 11:17   ` Geert Uytterhoeven
2021-05-27 11:17     ` Geert Uytterhoeven
2021-05-27 11:51     ` Lad, Prabhakar
2021-05-27 11:51       ` Lad, Prabhakar
2021-05-14 19:22 ` [PATCH 16/16] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar
2021-05-14 19:22   ` Lad Prabhakar
2021-05-21 15:40   ` Geert Uytterhoeven
2021-05-21 15:40     ` Geert Uytterhoeven
2021-05-21 18:21     ` Lad, Prabhakar
2021-05-21 18:21       ` Lad, Prabhakar

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