From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Date: Fri, 28 May 2021 08:51:21 +0100 [thread overview] Message-ID: <CA+V-a8vHQLCL+V0f7bKZOKhtgo9_Rsqy_YjBOa_gCvgZMmBLnA@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdXd==dM2QJN5gg0ka_7-HDQbeKZK66nmyASFJAnsVsSQA@mail.gmail.com> Hi Geert, On Thu, May 27, 2021 at 1:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Fri, May 14, 2021 at 9:24 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add CPG core wrapper for RZ/G2L family. > > > > Based on a patch in the BSP by Binh Nguyen > > <binh.nguyen.jz@renesas.com>. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- /dev/null > > +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c > > > +static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) > > +{ > > + struct mstp_clock *clock = to_mod_clock(hw); > > + struct cpg_mssr_priv *priv = clock->priv; > > + unsigned int reg = MSSR_OFF(clock->bit) * 4; > > The "* 4" here makes it difficult to review the module clock tables. > > E.g. > > DEF_MOD("gic", R9A07G044_CLK_GIC600, > R9A07G044_CLK_P1, > MSSR(5, BIT(0), (BIT(0) | BIT(1)))), > > The "5" means the CLK_ON_GIC600 register is at offset CLK_ON_R(5 * 4) > = 0x514. Removing the "* 4" means you could use > "MSSR(0x14, BIT(0), (BIT(0) | BIT(1))" instead. > > Unless it has unpleasant side effects, I'd even consider putting > the full CLK_ON offset there, i.e. > "MSSR(0x514, BIT(0), (BIT(0) | BIT(1))" and change the macros like: > > #define CLK_ON_R(reg) (reg) > #define CLK_MON_R(reg) (0x680 - 0x500 + (reg)) > OK will do that. > > --- /dev/null > > +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h > > > +#define CLK_ON_R(reg) (0x500 + reg) > > +#define CLK_MON_R(reg) (0x680 + reg) > > +#define CLK_RST_R(reg) (0x800 + reg) > > +#define CLK_MRST_R(reg) (0x980 + reg) > > The last three don't seem to be documented? > I have asked Chris to send the document across. Cheers, Prabhakar
WARNING: multiple messages have this Message-ID (diff)
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Date: Fri, 28 May 2021 08:51:21 +0100 [thread overview] Message-ID: <CA+V-a8vHQLCL+V0f7bKZOKhtgo9_Rsqy_YjBOa_gCvgZMmBLnA@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdXd==dM2QJN5gg0ka_7-HDQbeKZK66nmyASFJAnsVsSQA@mail.gmail.com> Hi Geert, On Thu, May 27, 2021 at 1:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Fri, May 14, 2021 at 9:24 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add CPG core wrapper for RZ/G2L family. > > > > Based on a patch in the BSP by Binh Nguyen > > <binh.nguyen.jz@renesas.com>. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- /dev/null > > +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c > > > +static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) > > +{ > > + struct mstp_clock *clock = to_mod_clock(hw); > > + struct cpg_mssr_priv *priv = clock->priv; > > + unsigned int reg = MSSR_OFF(clock->bit) * 4; > > The "* 4" here makes it difficult to review the module clock tables. > > E.g. > > DEF_MOD("gic", R9A07G044_CLK_GIC600, > R9A07G044_CLK_P1, > MSSR(5, BIT(0), (BIT(0) | BIT(1)))), > > The "5" means the CLK_ON_GIC600 register is at offset CLK_ON_R(5 * 4) > = 0x514. Removing the "* 4" means you could use > "MSSR(0x14, BIT(0), (BIT(0) | BIT(1))" instead. > > Unless it has unpleasant side effects, I'd even consider putting > the full CLK_ON offset there, i.e. > "MSSR(0x514, BIT(0), (BIT(0) | BIT(1))" and change the macros like: > > #define CLK_ON_R(reg) (reg) > #define CLK_MON_R(reg) (0x680 - 0x500 + (reg)) > OK will do that. > > --- /dev/null > > +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.h > > > +#define CLK_ON_R(reg) (0x500 + reg) > > +#define CLK_MON_R(reg) (0x680 + reg) > > +#define CLK_RST_R(reg) (0x800 + reg) > > +#define CLK_MRST_R(reg) (0x980 + reg) > > The last three don't seem to be documented? > I have asked Chris to send the document across. Cheers, Prabhakar _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-28 7:51 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-14 19:22 [PATCH 00/16] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 01/16] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-18 1:31 ` Rob Herring 2021-05-18 1:31 ` Rob Herring 2021-05-21 13:22 ` Geert Uytterhoeven 2021-05-21 13:22 ` Geert Uytterhoeven 2021-05-21 16:54 ` Lad, Prabhakar 2021-05-21 16:54 ` Lad, Prabhakar 2021-05-27 11:29 ` Geert Uytterhoeven 2021-05-27 11:29 ` Geert Uytterhoeven 2021-05-27 11:47 ` Lad, Prabhakar 2021-05-27 11:47 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Lad Prabhakar 2021-05-14 19:22 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L, LC} " Lad Prabhakar 2021-05-18 1:31 ` Rob Herring 2021-05-18 1:31 ` Rob Herring 2021-05-21 13:23 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} " Geert Uytterhoeven 2021-05-21 13:23 ` Geert Uytterhoeven 2021-05-21 17:09 ` Lad, Prabhakar 2021-05-21 17:09 ` Lad, Prabhakar 2021-05-27 11:28 ` Geert Uytterhoeven 2021-05-27 11:28 ` Geert Uytterhoeven 2021-05-27 11:49 ` Lad, Prabhakar 2021-05-27 11:49 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 03/16] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-18 1:32 ` Rob Herring 2021-05-18 1:32 ` Rob Herring 2021-05-21 13:24 ` Geert Uytterhoeven 2021-05-21 13:24 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} for the new RZ/G2{L, LC} SoC's Lad Prabhakar 2021-05-21 13:25 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's Geert Uytterhoeven 2021-05-21 13:25 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Geert Uytterhoeven 2021-05-21 17:21 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} " Lad, Prabhakar 2021-05-21 17:21 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Lad, Prabhakar 2021-05-27 11:47 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} " Geert Uytterhoeven 2021-05-27 11:47 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 05/16] arm64: defconfig: Enable ARCH_R9A07G044{L,LC} Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Lad Prabhakar 2021-05-14 19:22 ` [PATCH 06/16] dt-bindings: arm: renesas, prr: Add new compatible string for RZ/G{L, LC, UL} Lad Prabhakar 2021-05-18 1:33 ` Rob Herring 2021-05-18 1:33 ` Rob Herring 2021-05-21 13:25 ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Geert Uytterhoeven 2021-05-21 13:25 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 07/16] soc: renesas: Add support to read LSI DEVID register Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L,LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L, LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 09/16] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings Lad Prabhakar 2021-05-14 19:22 ` [PATCH 09/16] dt-bindings: serial: renesas, scif: " Lad Prabhakar 2021-05-18 1:33 ` Rob Herring 2021-05-18 1:33 ` Rob Herring 2021-05-21 13:26 ` [PATCH 09/16] dt-bindings: serial: renesas,scif: " Geert Uytterhoeven 2021-05-21 13:26 ` Geert Uytterhoeven 2021-05-21 15:15 ` Geert Uytterhoeven 2021-05-21 15:15 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 10/16] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 13:26 ` Geert Uytterhoeven 2021-05-21 13:26 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-18 1:35 ` Rob Herring 2021-05-18 1:35 ` Rob Herring 2021-05-21 15:04 ` Geert Uytterhoeven 2021-05-21 15:04 ` Geert Uytterhoeven 2021-05-21 18:42 ` Lad, Prabhakar 2021-05-21 18:42 ` Lad, Prabhakar 2021-05-27 11:51 ` Geert Uytterhoeven 2021-05-27 11:51 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 12/16] clk: renesas: Define RZ/G2L CPG Clock Definitions Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 15:03 ` Geert Uytterhoeven 2021-05-21 15:03 ` Geert Uytterhoeven 2021-05-21 15:19 ` Geert Uytterhoeven 2021-05-21 15:19 ` Geert Uytterhoeven 2021-05-21 18:37 ` Lad, Prabhakar 2021-05-21 18:37 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 15:02 ` Geert Uytterhoeven 2021-05-21 15:02 ` Geert Uytterhoeven 2021-05-27 12:04 ` Geert Uytterhoeven 2021-05-27 12:04 ` Geert Uytterhoeven 2021-05-28 7:51 ` Lad, Prabhakar [this message] 2021-05-28 7:51 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 14/16] clk: renesas: Add support for R9A07G044L SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L, LC} SoC's Lad Prabhakar 2021-05-21 15:35 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Geert Uytterhoeven 2021-05-21 15:35 ` Geert Uytterhoeven 2021-05-21 18:36 ` Lad, Prabhakar 2021-05-21 18:36 ` Lad, Prabhakar 2021-05-27 11:17 ` Geert Uytterhoeven 2021-05-27 11:17 ` Geert Uytterhoeven 2021-05-27 11:51 ` Lad, Prabhakar 2021-05-27 11:51 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 16/16] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 15:40 ` Geert Uytterhoeven 2021-05-21 15:40 ` Geert Uytterhoeven 2021-05-21 18:21 ` Lad, Prabhakar 2021-05-21 18:21 ` Lad, Prabhakar
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