* [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
@ 2021-05-18 21:34 ` Anusha Srivatsa
2021-05-19 5:40 ` Lucas De Marchi
2021-05-18 21:34 ` [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC Anusha Srivatsa
` (7 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Anusha Srivatsa @ 2021-05-18 21:34 UTC (permalink / raw)
To: intel-gfx
No functional change.
v2: Chchpatch fixes.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 170 +++++++++---------
.../drm/i915/display/intel_display_debugfs.c | 14 +-
.../drm/i915/display/intel_display_power.c | 52 +++---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
6 files changed, 125 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 26a922d34263..a22339ebdffd 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -312,7 +312,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
*/
void intel_csr_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->csr.dmc_payload;
+ u32 *payload = dev_priv->dmc.dmc_payload;
u32 i, fw_size;
if (!HAS_CSR(dev_priv)) {
@@ -321,13 +321,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!dev_priv->csr.dmc_payload) {
+ if (!dev_priv->dmc.dmc_payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->csr.dmc_fw_size;
+ fw_size = dev_priv->dmc.dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
@@ -338,12 +338,12 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
preempt_enable();
- for (i = 0; i < dev_priv->csr.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
- dev_priv->csr.mmiodata[i]);
+ for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
+ intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
+ dev_priv->dmc.mmiodata[i]);
}
- dev_priv->csr.dc_state = 0;
+ dev_priv->dmc.dc_state = 0;
gen9_set_dc_state_debugmask(dev_priv);
}
@@ -392,7 +392,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
return dmc_offset;
}
-static u32 parse_csr_fw_dmc(struct intel_csr *csr,
+static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
@@ -401,8 +401,8 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
- ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -464,10 +464,10 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
mmioaddr[i]);
return 0;
}
- csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
- csr->mmiodata[i] = mmiodata[i];
+ dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc->mmiodata[i] = mmiodata[i];
}
- csr->mmio_count = mmio_count;
+ dmc->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -476,20 +476,20 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
if (rem_size < payload_size)
goto error_truncated;
- if (payload_size > csr->max_fw_size) {
+ if (payload_size > dmc->max_fw_size) {
DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
- csr->dmc_fw_size = dmc_header->fw_size;
+ dmc->dmc_fw_size = dmc_header->fw_size;
- csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!csr->dmc_payload) {
+ dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc->dmc_payload) {
DRM_ERROR("Memory allocation failed for dmc payload\n");
return 0;
}
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(csr->dmc_payload, payload, payload_size);
+ memcpy(dmc->dmc_payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -499,7 +499,7 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
}
static u32
-parse_csr_fw_package(struct intel_csr *csr,
+parse_csr_fw_package(struct intel_dmc *dmc,
const struct intel_package_header *package_header,
const struct stepping_info *si,
size_t rem_size)
@@ -558,7 +558,7 @@ parse_csr_fw_package(struct intel_csr *csr,
}
/* Return number of bytes parsed or 0 on error */
-static u32 parse_csr_fw_css(struct intel_csr *csr,
+static u32 parse_csr_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
@@ -575,18 +575,18 @@ static u32 parse_csr_fw_css(struct intel_csr *csr,
return 0;
}
- if (csr->required_version &&
- css_header->version != csr->required_version) {
+ if (dmc->required_version &&
+ css_header->version != dmc->required_version) {
DRM_INFO("Refusing to load DMC firmware v%u.%u,"
" please use v%u.%u\n",
CSR_VERSION_MAJOR(css_header->version),
CSR_VERSION_MINOR(css_header->version),
- CSR_VERSION_MAJOR(csr->required_version),
- CSR_VERSION_MINOR(csr->required_version));
+ CSR_VERSION_MAJOR(dmc->required_version),
+ CSR_VERSION_MINOR(dmc->required_version));
return 0;
}
- csr->version = css_header->version;
+ dmc->version = css_header->version;
return sizeof(struct intel_css_header);
}
@@ -597,7 +597,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
- struct intel_csr *csr = &dev_priv->csr;
+ struct intel_dmc *dmc = &dev_priv->dmc;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
u32 readcount = 0;
u32 r;
@@ -607,7 +607,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract CSS Header information */
css_header = (struct intel_css_header *)fw->data;
- r = parse_csr_fw_css(csr, css_header, fw->size);
+ r = parse_csr_fw_css(dmc, css_header, fw->size);
if (!r)
return;
@@ -615,7 +615,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract Package Header information */
package_header = (struct intel_package_header *)&fw->data[readcount];
- r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
+ r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount);
if (!r)
return;
@@ -623,20 +623,20 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract dmc_header information */
dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
- parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
+ parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount);
}
static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
{
- drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
- dev_priv->csr.wakeref =
+ drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
+ dev_priv->dmc.wakeref =
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&dev_priv->csr.wakeref);
+ fetch_and_zero(&dev_priv->dmc.wakeref);
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
}
@@ -644,28 +644,28 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
static void csr_load_work_fn(struct work_struct *work)
{
struct drm_i915_private *dev_priv;
- struct intel_csr *csr;
+ struct intel_dmc *dmc;
const struct firmware *fw = NULL;
- dev_priv = container_of(work, typeof(*dev_priv), csr.work);
- csr = &dev_priv->csr;
+ dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
+ dmc = &dev_priv->dmc;
- request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
+ request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
parse_csr_fw(dev_priv, fw);
- if (dev_priv->csr.dmc_payload) {
+ if (dev_priv->dmc.dmc_payload) {
intel_csr_load_program(dev_priv);
intel_csr_runtime_pm_put(dev_priv);
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
- dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
- CSR_VERSION_MINOR(csr->version));
+ dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version),
+ CSR_VERSION_MINOR(dmc->version));
} else {
drm_notice(&dev_priv->drm,
"Failed to load DMC firmware %s."
" Disabling runtime power management.\n",
- csr->fw_path);
+ dmc->fw_path);
drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
INTEL_UC_FIRMWARE_URL);
}
@@ -682,9 +682,9 @@ static void csr_load_work_fn(struct work_struct *work)
*/
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
{
- struct intel_csr *csr = &dev_priv->csr;
+ struct intel_dmc *dmc = &dev_priv->dmc;
- INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
+ INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
if (!HAS_CSR(dev_priv))
return;
@@ -700,70 +700,70 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
intel_csr_runtime_pm_get(dev_priv);
if (IS_ALDERLAKE_S(dev_priv)) {
- csr->fw_path = ADLS_CSR_PATH;
- csr->required_version = ADLS_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = ADLS_CSR_PATH;
+ dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (IS_DG1(dev_priv)) {
- csr->fw_path = DG1_CSR_PATH;
- csr->required_version = DG1_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = DG1_CSR_PATH;
+ dmc->required_version = DG1_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (IS_ROCKETLAKE(dev_priv)) {
- csr->fw_path = RKL_CSR_PATH;
- csr->required_version = RKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = RKL_CSR_PATH;
+ dmc->required_version = RKL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- csr->fw_path = TGL_CSR_PATH;
- csr->required_version = TGL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = TGL_CSR_PATH;
+ dmc->required_version = TGL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) == 11) {
- csr->fw_path = ICL_CSR_PATH;
- csr->required_version = ICL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = ICL_CSR_PATH;
+ dmc->required_version = ICL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
} else if (IS_CANNONLAKE(dev_priv)) {
- csr->fw_path = CNL_CSR_PATH;
- csr->required_version = CNL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = CNL_CSR_PATH;
+ dmc->required_version = CNL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
} else if (IS_GEMINILAKE(dev_priv)) {
- csr->fw_path = GLK_CSR_PATH;
- csr->required_version = GLK_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
+ dmc->fw_path = GLK_CSR_PATH;
+ dmc->required_version = GLK_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
} else if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
- csr->fw_path = KBL_CSR_PATH;
- csr->required_version = KBL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = KBL_CSR_PATH;
+ dmc->required_version = KBL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
} else if (IS_SKYLAKE(dev_priv)) {
- csr->fw_path = SKL_CSR_PATH;
- csr->required_version = SKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = SKL_CSR_PATH;
+ dmc->required_version = SKL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
} else if (IS_BROXTON(dev_priv)) {
- csr->fw_path = BXT_CSR_PATH;
- csr->required_version = BXT_CSR_VERSION_REQUIRED;
- csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
+ dmc->fw_path = BXT_CSR_PATH;
+ dmc->required_version = BXT_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
}
if (dev_priv->params.dmc_firmware_path) {
if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
- csr->fw_path = NULL;
+ dmc->fw_path = NULL;
drm_info(&dev_priv->drm,
- "Disabling CSR firmware and runtime PM\n");
+ "Disabling DMC firmware and runtime PM\n");
return;
}
- csr->fw_path = dev_priv->params.dmc_firmware_path;
+ dmc->fw_path = dev_priv->params.dmc_firmware_path;
/* Bypass version check for firmware override. */
- csr->required_version = 0;
+ dmc->required_version = 0;
}
- if (csr->fw_path == NULL) {
+ if (!dmc->fw_path) {
drm_dbg_kms(&dev_priv->drm,
- "No known CSR firmware for platform, disabling runtime PM\n");
+ "No known DMC firmware for platform, disabling runtime PM\n");
return;
}
- drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
- schedule_work(&dev_priv->csr.work);
+ drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
+ schedule_work(&dev_priv->dmc.work);
}
/**
@@ -779,10 +779,10 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
if (!HAS_CSR(dev_priv))
return;
- flush_work(&dev_priv->csr.work);
+ flush_work(&dev_priv->dmc.work);
/* Drop the reference held in case DMC isn't loaded. */
- if (!dev_priv->csr.dmc_payload)
+ if (!dev_priv->dmc.dmc_payload)
intel_csr_runtime_pm_put(dev_priv);
}
@@ -802,7 +802,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
* Reacquire the reference to keep RPM disabled in case DMC isn't
* loaded.
*/
- if (!dev_priv->csr.dmc_payload)
+ if (!dev_priv->dmc.dmc_payload)
intel_csr_runtime_pm_get(dev_priv);
}
@@ -819,7 +819,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
return;
intel_csr_ucode_suspend(dev_priv);
- drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- kfree(dev_priv->csr.dmc_payload);
+ kfree(dev_priv->dmc.dmc_payload);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d77a0ab5cacf..a875f3c9b358 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -532,24 +532,24 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
- struct intel_csr *csr;
+ struct intel_dmc *dmc;
i915_reg_t dc5_reg, dc6_reg = {};
if (!HAS_CSR(dev_priv))
return -ENODEV;
- csr = &dev_priv->csr;
+ dmc = &dev_priv->dmc;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
- seq_printf(m, "path: %s\n", csr->fw_path);
+ seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload));
+ seq_printf(m, "path: %s\n", dmc->fw_path);
- if (!csr->dmc_payload)
+ if (!dmc->dmc_payload)
goto out;
- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
- CSR_VERSION_MINOR(csr->version));
+ seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version),
+ CSR_VERSION_MINOR(dmc->version));
if (DISPLAY_VER(dev_priv) >= 12) {
if (IS_DGFX(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 54c6d65011ee..0a05d0f90f28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -829,8 +829,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"Resetting DC state tracking from %02x to %02x\n",
- dev_priv->csr.dc_state, val);
- dev_priv->csr.dc_state = val;
+ dev_priv->dmc.dc_state, val);
+ dev_priv->dmc.dc_state = val;
}
/**
@@ -865,8 +865,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm,
- state & ~dev_priv->csr.allowed_dc_mask))
- state &= dev_priv->csr.allowed_dc_mask;
+ state & ~dev_priv->dmc.allowed_dc_mask))
+ state &= dev_priv->dmc.allowed_dc_mask;
val = intel_de_read(dev_priv, DC_STATE_EN);
mask = gen9_dc_mask(dev_priv);
@@ -874,16 +874,16 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
val & mask, state);
/* Check if DMC is ignoring our DC state requests */
- if ((val & mask) != dev_priv->csr.dc_state)
+ if ((val & mask) != dev_priv->dmc.dc_state)
drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
- dev_priv->csr.dc_state, val & mask);
+ dev_priv->dmc.dc_state, val & mask);
val &= ~mask;
val |= state;
gen9_write_dc_state(dev_priv, val);
- dev_priv->csr.dc_state = val & mask;
+ dev_priv->dmc.dc_state = val & mask;
}
static u32
@@ -902,7 +902,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->csr.allowed_dc_mask & target_dc_state)
+ if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -1016,7 +1016,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->csr.target_dc_state)
+ if (state == dev_priv->dmc.target_dc_state)
goto unlock;
dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
@@ -1028,7 +1028,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (!dc_off_enabled)
power_well->desc->ops->enable(dev_priv, power_well);
- dev_priv->csr.target_dc_state = state;
+ dev_priv->dmc.target_dc_state = state;
if (!dc_off_enabled)
power_well->desc->ops->disable(dev_priv, power_well);
@@ -1181,7 +1181,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = {};
- if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
+ if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
return;
}
@@ -1220,10 +1220,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (!dev_priv->csr.dmc_payload)
+ if (!dev_priv->dmc.dmc_payload)
return;
- switch (dev_priv->csr.target_dc_state) {
+ switch (dev_priv->dmc.target_dc_state) {
case DC_STATE_EN_DC3CO:
tgl_enable_dc3co(dev_priv);
break;
@@ -5090,10 +5090,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->csr.allowed_dc_mask =
+ dev_priv->dmc.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->csr.target_dc_state =
+ dev_priv->dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
@@ -5573,7 +5573,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
}
@@ -5640,7 +5640,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
}
@@ -5706,7 +5706,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
}
@@ -5863,7 +5863,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
/* Wa_14011508470 */
@@ -6222,9 +6222,9 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
- i915->csr.dmc_payload) {
+ i915->dmc.dmc_payload) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -6414,19 +6414,19 @@ void intel_display_power_resume(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
- if (i915->csr.dmc_payload) {
- if (i915->csr.allowed_dc_mask &
+ if (i915->dmc.dmc_payload) {
+ if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->csr.allowed_dc_mask &
+ else if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
- if (i915->csr.dmc_payload &&
- (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ if (i915->dmc.dmc_payload &&
+ (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index acaf3d459821..0905386b2270 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -669,7 +669,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (crtc_state->enable_psr2_sel_fetch)
return;
- if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9aee6a045590..3c9f6bbb5dd7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -328,7 +328,7 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_csr {
+struct intel_dmc {
struct work_struct work;
const char *fw_path;
u32 required_version;
@@ -824,7 +824,7 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- struct intel_csr csr;
+ struct intel_dmc dmc;
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 99ca242ec13b..03d1221de13b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -789,13 +789,13 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
if (HAS_CSR(m->i915)) {
- struct intel_csr *csr = &m->i915->csr;
+ struct intel_dmc *dmc = &m->i915->dmc;
err_printf(m, "DMC loaded: %s\n",
- yesno(csr->dmc_payload != NULL));
+ yesno(dmc->dmc_payload));
err_printf(m, "DMC fw version: %d.%d\n",
- CSR_VERSION_MAJOR(csr->version),
- CSR_VERSION_MINOR(csr->version));
+ CSR_VERSION_MAJOR(dmc->version),
+ CSR_VERSION_MINOR(dmc->version));
}
err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc
2021-05-18 21:34 ` [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc Anusha Srivatsa
@ 2021-05-19 5:40 ` Lucas De Marchi
0 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2021-05-19 5:40 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Tue, May 18, 2021 at 02:34:40PM -0700, Anusha Srivatsa wrote:
>No functional change.
>
>v2: Chchpatch fixes.
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
`git show -U0 --word-diff=color` really helps here. Not sure if I would
split the patch per struct/functions/macro like was done, but I'm ok
with it.
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_csr.c | 170 +++++++++---------
> .../drm/i915/display/intel_display_debugfs.c | 14 +-
> .../drm/i915/display/intel_display_power.c | 52 +++---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
> 6 files changed, 125 insertions(+), 125 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>index 26a922d34263..a22339ebdffd 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
>@@ -312,7 +312,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> */
> void intel_csr_load_program(struct drm_i915_private *dev_priv)
> {
>- u32 *payload = dev_priv->csr.dmc_payload;
>+ u32 *payload = dev_priv->dmc.dmc_payload;
> u32 i, fw_size;
>
> if (!HAS_CSR(dev_priv)) {
>@@ -321,13 +321,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
> return;
> }
>
>- if (!dev_priv->csr.dmc_payload) {
>+ if (!dev_priv->dmc.dmc_payload) {
> drm_err(&dev_priv->drm,
> "Tried to program CSR with empty payload\n");
> return;
> }
>
>- fw_size = dev_priv->csr.dmc_fw_size;
>+ fw_size = dev_priv->dmc.dmc_fw_size;
> assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
> preempt_disable();
>@@ -338,12 +338,12 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
>
> preempt_enable();
>
>- for (i = 0; i < dev_priv->csr.mmio_count; i++) {
>- intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
>- dev_priv->csr.mmiodata[i]);
>+ for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
>+ intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
>+ dev_priv->dmc.mmiodata[i]);
> }
>
>- dev_priv->csr.dc_state = 0;
>+ dev_priv->dmc.dc_state = 0;
>
> gen9_set_dc_state_debugmask(dev_priv);
> }
>@@ -392,7 +392,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
> return dmc_offset;
> }
>
>-static u32 parse_csr_fw_dmc(struct intel_csr *csr,
>+static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
> const struct intel_dmc_header_base *dmc_header,
> size_t rem_size)
> {
>@@ -401,8 +401,8 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> u32 mmio_count, mmio_count_max;
> u8 *payload;
>
>- BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
>- ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
>+ BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
>+ ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
>
> /*
> * Check if we can access common fields, we will checkc again below
>@@ -464,10 +464,10 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> mmioaddr[i]);
> return 0;
> }
>- csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
>- csr->mmiodata[i] = mmiodata[i];
>+ dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
>+ dmc->mmiodata[i] = mmiodata[i];
> }
>- csr->mmio_count = mmio_count;
>+ dmc->mmio_count = mmio_count;
>
> rem_size -= header_len_bytes;
>
>@@ -476,20 +476,20 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> if (rem_size < payload_size)
> goto error_truncated;
>
>- if (payload_size > csr->max_fw_size) {
>+ if (payload_size > dmc->max_fw_size) {
> DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
> return 0;
> }
>- csr->dmc_fw_size = dmc_header->fw_size;
>+ dmc->dmc_fw_size = dmc_header->fw_size;
>
>- csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
>- if (!csr->dmc_payload) {
>+ dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
>+ if (!dmc->dmc_payload) {
> DRM_ERROR("Memory allocation failed for dmc payload\n");
> return 0;
> }
>
> payload = (u8 *)(dmc_header) + header_len_bytes;
>- memcpy(csr->dmc_payload, payload, payload_size);
>+ memcpy(dmc->dmc_payload, payload, payload_size);
>
> return header_len_bytes + payload_size;
>
>@@ -499,7 +499,7 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> }
>
> static u32
>-parse_csr_fw_package(struct intel_csr *csr,
>+parse_csr_fw_package(struct intel_dmc *dmc,
> const struct intel_package_header *package_header,
> const struct stepping_info *si,
> size_t rem_size)
>@@ -558,7 +558,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> }
>
> /* Return number of bytes parsed or 0 on error */
>-static u32 parse_csr_fw_css(struct intel_csr *csr,
>+static u32 parse_csr_fw_css(struct intel_dmc *dmc,
> struct intel_css_header *css_header,
> size_t rem_size)
> {
>@@ -575,18 +575,18 @@ static u32 parse_csr_fw_css(struct intel_csr *csr,
> return 0;
> }
>
>- if (csr->required_version &&
>- css_header->version != csr->required_version) {
>+ if (dmc->required_version &&
>+ css_header->version != dmc->required_version) {
> DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> " please use v%u.%u\n",
> CSR_VERSION_MAJOR(css_header->version),
> CSR_VERSION_MINOR(css_header->version),
>- CSR_VERSION_MAJOR(csr->required_version),
>- CSR_VERSION_MINOR(csr->required_version));
>+ CSR_VERSION_MAJOR(dmc->required_version),
>+ CSR_VERSION_MINOR(dmc->required_version));
> return 0;
> }
>
>- csr->version = css_header->version;
>+ dmc->version = css_header->version;
>
> return sizeof(struct intel_css_header);
> }
>@@ -597,7 +597,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
> struct intel_css_header *css_header;
> struct intel_package_header *package_header;
> struct intel_dmc_header_base *dmc_header;
>- struct intel_csr *csr = &dev_priv->csr;
>+ struct intel_dmc *dmc = &dev_priv->dmc;
> const struct stepping_info *si = intel_get_stepping_info(dev_priv);
> u32 readcount = 0;
> u32 r;
>@@ -607,7 +607,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract CSS Header information */
> css_header = (struct intel_css_header *)fw->data;
>- r = parse_csr_fw_css(csr, css_header, fw->size);
>+ r = parse_csr_fw_css(dmc, css_header, fw->size);
> if (!r)
> return;
>
>@@ -615,7 +615,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract Package Header information */
> package_header = (struct intel_package_header *)&fw->data[readcount];
>- r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
>+ r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount);
> if (!r)
> return;
>
>@@ -623,20 +623,20 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract dmc_header information */
> dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
>- parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
>+ parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount);
> }
>
> static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
> {
>- drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
>- dev_priv->csr.wakeref =
>+ drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
>+ dev_priv->dmc.wakeref =
> intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> }
>
> static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
> {
> intel_wakeref_t wakeref __maybe_unused =
>- fetch_and_zero(&dev_priv->csr.wakeref);
>+ fetch_and_zero(&dev_priv->dmc.wakeref);
>
> intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
> }
>@@ -644,28 +644,28 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
> static void csr_load_work_fn(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv;
>- struct intel_csr *csr;
>+ struct intel_dmc *dmc;
> const struct firmware *fw = NULL;
>
>- dev_priv = container_of(work, typeof(*dev_priv), csr.work);
>- csr = &dev_priv->csr;
>+ dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
>+ dmc = &dev_priv->dmc;
>
>- request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
>+ request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
> parse_csr_fw(dev_priv, fw);
>
>- if (dev_priv->csr.dmc_payload) {
>+ if (dev_priv->dmc.dmc_payload) {
> intel_csr_load_program(dev_priv);
> intel_csr_runtime_pm_put(dev_priv);
>
> drm_info(&dev_priv->drm,
> "Finished loading DMC firmware %s (v%u.%u)\n",
>- dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
>- CSR_VERSION_MINOR(csr->version));
>+ dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version),
>+ CSR_VERSION_MINOR(dmc->version));
> } else {
> drm_notice(&dev_priv->drm,
> "Failed to load DMC firmware %s."
> " Disabling runtime power management.\n",
>- csr->fw_path);
>+ dmc->fw_path);
> drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
> INTEL_UC_FIRMWARE_URL);
> }
>@@ -682,9 +682,9 @@ static void csr_load_work_fn(struct work_struct *work)
> */
> void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> {
>- struct intel_csr *csr = &dev_priv->csr;
>+ struct intel_dmc *dmc = &dev_priv->dmc;
>
>- INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
>+ INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
>
> if (!HAS_CSR(dev_priv))
> return;
>@@ -700,70 +700,70 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> intel_csr_runtime_pm_get(dev_priv);
>
> if (IS_ALDERLAKE_S(dev_priv)) {
>- csr->fw_path = ADLS_CSR_PATH;
>- csr->required_version = ADLS_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = ADLS_CSR_PATH;
>+ dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> } else if (IS_DG1(dev_priv)) {
>- csr->fw_path = DG1_CSR_PATH;
>- csr->required_version = DG1_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = DG1_CSR_PATH;
>+ dmc->required_version = DG1_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> } else if (IS_ROCKETLAKE(dev_priv)) {
>- csr->fw_path = RKL_CSR_PATH;
>- csr->required_version = RKL_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = RKL_CSR_PATH;
>+ dmc->required_version = RKL_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
>- csr->fw_path = TGL_CSR_PATH;
>- csr->required_version = TGL_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = TGL_CSR_PATH;
>+ dmc->required_version = TGL_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> } else if (DISPLAY_VER(dev_priv) == 11) {
>- csr->fw_path = ICL_CSR_PATH;
>- csr->required_version = ICL_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = ICL_CSR_PATH;
>+ dmc->required_version = ICL_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
> } else if (IS_CANNONLAKE(dev_priv)) {
>- csr->fw_path = CNL_CSR_PATH;
>- csr->required_version = CNL_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = CNL_CSR_PATH;
>+ dmc->required_version = CNL_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
> } else if (IS_GEMINILAKE(dev_priv)) {
>- csr->fw_path = GLK_CSR_PATH;
>- csr->required_version = GLK_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = GLK_CSR_PATH;
>+ dmc->required_version = GLK_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
> } else if (IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv)) {
>- csr->fw_path = KBL_CSR_PATH;
>- csr->required_version = KBL_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = KBL_CSR_PATH;
>+ dmc->required_version = KBL_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
> } else if (IS_SKYLAKE(dev_priv)) {
>- csr->fw_path = SKL_CSR_PATH;
>- csr->required_version = SKL_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = SKL_CSR_PATH;
>+ dmc->required_version = SKL_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
> } else if (IS_BROXTON(dev_priv)) {
>- csr->fw_path = BXT_CSR_PATH;
>- csr->required_version = BXT_CSR_VERSION_REQUIRED;
>- csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = BXT_CSR_PATH;
>+ dmc->required_version = BXT_CSR_VERSION_REQUIRED;
>+ dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
> }
>
> if (dev_priv->params.dmc_firmware_path) {
> if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
>- csr->fw_path = NULL;
>+ dmc->fw_path = NULL;
> drm_info(&dev_priv->drm,
>- "Disabling CSR firmware and runtime PM\n");
>+ "Disabling DMC firmware and runtime PM\n");
> return;
> }
>
>- csr->fw_path = dev_priv->params.dmc_firmware_path;
>+ dmc->fw_path = dev_priv->params.dmc_firmware_path;
> /* Bypass version check for firmware override. */
>- csr->required_version = 0;
>+ dmc->required_version = 0;
> }
>
>- if (csr->fw_path == NULL) {
>+ if (!dmc->fw_path) {
> drm_dbg_kms(&dev_priv->drm,
>- "No known CSR firmware for platform, disabling runtime PM\n");
>+ "No known DMC firmware for platform, disabling runtime PM\n");
> return;
> }
>
>- drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
>- schedule_work(&dev_priv->csr.work);
>+ drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
>+ schedule_work(&dev_priv->dmc.work);
> }
>
> /**
>@@ -779,10 +779,10 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
> if (!HAS_CSR(dev_priv))
> return;
>
>- flush_work(&dev_priv->csr.work);
>+ flush_work(&dev_priv->dmc.work);
>
> /* Drop the reference held in case DMC isn't loaded. */
>- if (!dev_priv->csr.dmc_payload)
>+ if (!dev_priv->dmc.dmc_payload)
> intel_csr_runtime_pm_put(dev_priv);
> }
>
>@@ -802,7 +802,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
> * Reacquire the reference to keep RPM disabled in case DMC isn't
> * loaded.
> */
>- if (!dev_priv->csr.dmc_payload)
>+ if (!dev_priv->dmc.dmc_payload)
> intel_csr_runtime_pm_get(dev_priv);
> }
>
>@@ -819,7 +819,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
> return;
>
> intel_csr_ucode_suspend(dev_priv);
>- drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
>+ drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
>
>- kfree(dev_priv->csr.dmc_payload);
>+ kfree(dev_priv->dmc.dmc_payload);
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index d77a0ab5cacf..a875f3c9b358 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -532,24 +532,24 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> intel_wakeref_t wakeref;
>- struct intel_csr *csr;
>+ struct intel_dmc *dmc;
> i915_reg_t dc5_reg, dc6_reg = {};
>
> if (!HAS_CSR(dev_priv))
> return -ENODEV;
>
>- csr = &dev_priv->csr;
>+ dmc = &dev_priv->dmc;
>
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>
>- seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
>- seq_printf(m, "path: %s\n", csr->fw_path);
>+ seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload));
>+ seq_printf(m, "path: %s\n", dmc->fw_path);
>
>- if (!csr->dmc_payload)
>+ if (!dmc->dmc_payload)
> goto out;
>
>- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>- CSR_VERSION_MINOR(csr->version));
>+ seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version),
>+ CSR_VERSION_MINOR(dmc->version));
>
> if (DISPLAY_VER(dev_priv) >= 12) {
> if (IS_DGFX(dev_priv)) {
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 54c6d65011ee..0a05d0f90f28 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -829,8 +829,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
>
> drm_dbg_kms(&dev_priv->drm,
> "Resetting DC state tracking from %02x to %02x\n",
>- dev_priv->csr.dc_state, val);
>- dev_priv->csr.dc_state = val;
>+ dev_priv->dmc.dc_state, val);
>+ dev_priv->dmc.dc_state = val;
> }
>
> /**
>@@ -865,8 +865,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> return;
>
> if (drm_WARN_ON_ONCE(&dev_priv->drm,
>- state & ~dev_priv->csr.allowed_dc_mask))
>- state &= dev_priv->csr.allowed_dc_mask;
>+ state & ~dev_priv->dmc.allowed_dc_mask))
>+ state &= dev_priv->dmc.allowed_dc_mask;
>
> val = intel_de_read(dev_priv, DC_STATE_EN);
> mask = gen9_dc_mask(dev_priv);
>@@ -874,16 +874,16 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> val & mask, state);
>
> /* Check if DMC is ignoring our DC state requests */
>- if ((val & mask) != dev_priv->csr.dc_state)
>+ if ((val & mask) != dev_priv->dmc.dc_state)
> drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>- dev_priv->csr.dc_state, val & mask);
>+ dev_priv->dmc.dc_state, val & mask);
>
> val &= ~mask;
> val |= state;
>
> gen9_write_dc_state(dev_priv, val);
>
>- dev_priv->csr.dc_state = val & mask;
>+ dev_priv->dmc.dc_state = val & mask;
> }
>
> static u32
>@@ -902,7 +902,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
> if (target_dc_state != states[i])
> continue;
>
>- if (dev_priv->csr.allowed_dc_mask & target_dc_state)
>+ if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
> break;
>
> target_dc_state = states[i + 1];
>@@ -1016,7 +1016,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
>
> state = sanitize_target_dc_state(dev_priv, state);
>
>- if (state == dev_priv->csr.target_dc_state)
>+ if (state == dev_priv->dmc.target_dc_state)
> goto unlock;
>
> dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
>@@ -1028,7 +1028,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
> if (!dc_off_enabled)
> power_well->desc->ops->enable(dev_priv, power_well);
>
>- dev_priv->csr.target_dc_state = state;
>+ dev_priv->dmc.target_dc_state = state;
>
> if (!dc_off_enabled)
> power_well->desc->ops->disable(dev_priv, power_well);
>@@ -1181,7 +1181,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config = {};
>
>- if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
>+ if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
> tgl_disable_dc3co(dev_priv);
> return;
> }
>@@ -1220,10 +1220,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
>- if (!dev_priv->csr.dmc_payload)
>+ if (!dev_priv->dmc.dmc_payload)
> return;
>
>- switch (dev_priv->csr.target_dc_state) {
>+ switch (dev_priv->dmc.target_dc_state) {
> case DC_STATE_EN_DC3CO:
> tgl_enable_dc3co(dev_priv);
> break;
>@@ -5090,10 +5090,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> dev_priv->params.disable_power_well =
> sanitize_disable_power_well_option(dev_priv,
> dev_priv->params.disable_power_well);
>- dev_priv->csr.allowed_dc_mask =
>+ dev_priv->dmc.allowed_dc_mask =
> get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
>
>- dev_priv->csr.target_dc_state =
>+ dev_priv->dmc.target_dc_state =
> sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
>
> BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
>@@ -5573,7 +5573,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> gen9_dbuf_enable(dev_priv);
>
>- if (resume && dev_priv->csr.dmc_payload)
>+ if (resume && dev_priv->dmc.dmc_payload)
> intel_csr_load_program(dev_priv);
> }
>
>@@ -5640,7 +5640,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> gen9_dbuf_enable(dev_priv);
>
>- if (resume && dev_priv->csr.dmc_payload)
>+ if (resume && dev_priv->dmc.dmc_payload)
> intel_csr_load_program(dev_priv);
> }
>
>@@ -5706,7 +5706,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
>
>- if (resume && dev_priv->csr.dmc_payload)
>+ if (resume && dev_priv->dmc.dmc_payload)
> intel_csr_load_program(dev_priv);
> }
>
>@@ -5863,7 +5863,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> if (DISPLAY_VER(dev_priv) >= 12)
> tgl_bw_buddy_init(dev_priv);
>
>- if (resume && dev_priv->csr.dmc_payload)
>+ if (resume && dev_priv->dmc.dmc_payload)
> intel_csr_load_program(dev_priv);
>
> /* Wa_14011508470 */
>@@ -6222,9 +6222,9 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
> * resources as required and also enable deeper system power states
> * that would be blocked if the firmware was inactive.
> */
>- if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
>+ if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
> suspend_mode == I915_DRM_SUSPEND_IDLE &&
>- i915->csr.dmc_payload) {
>+ i915->dmc.dmc_payload) {
> intel_display_power_flush_work(i915);
> intel_power_domains_verify_state(i915);
> return;
>@@ -6414,19 +6414,19 @@ void intel_display_power_resume(struct drm_i915_private *i915)
> if (DISPLAY_VER(i915) >= 11) {
> bxt_disable_dc9(i915);
> icl_display_core_init(i915, true);
>- if (i915->csr.dmc_payload) {
>- if (i915->csr.allowed_dc_mask &
>+ if (i915->dmc.dmc_payload) {
>+ if (i915->dmc.allowed_dc_mask &
> DC_STATE_EN_UPTO_DC6)
> skl_enable_dc6(i915);
>- else if (i915->csr.allowed_dc_mask &
>+ else if (i915->dmc.allowed_dc_mask &
> DC_STATE_EN_UPTO_DC5)
> gen9_enable_dc5(i915);
> }
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> bxt_disable_dc9(i915);
> bxt_display_core_init(i915, true);
>- if (i915->csr.dmc_payload &&
>- (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
>+ if (i915->dmc.dmc_payload &&
>+ (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> gen9_enable_dc5(i915);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> hsw_disable_pc8(i915);
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index acaf3d459821..0905386b2270 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -669,7 +669,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
> if (crtc_state->enable_psr2_sel_fetch)
> return;
>
>- if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
>+ if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
> return;
>
> /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 9aee6a045590..3c9f6bbb5dd7 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -328,7 +328,7 @@ struct drm_i915_display_funcs {
> void (*read_luts)(struct intel_crtc_state *crtc_state);
> };
>
>-struct intel_csr {
>+struct intel_dmc {
> struct work_struct work;
> const char *fw_path;
> u32 required_version;
>@@ -824,7 +824,7 @@ struct drm_i915_private {
>
> struct intel_wopcm wopcm;
>
>- struct intel_csr csr;
>+ struct intel_dmc dmc;
>
> struct intel_gmbus gmbus[GMBUS_NUM_PINS];
>
>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>index 99ca242ec13b..03d1221de13b 100644
>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>@@ -789,13 +789,13 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
> err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
> if (HAS_CSR(m->i915)) {
>- struct intel_csr *csr = &m->i915->csr;
>+ struct intel_dmc *dmc = &m->i915->dmc;
>
> err_printf(m, "DMC loaded: %s\n",
>- yesno(csr->dmc_payload != NULL));
>+ yesno(dmc->dmc_payload));
> err_printf(m, "DMC fw version: %d.%d\n",
>- CSR_VERSION_MAJOR(csr->version),
>- CSR_VERSION_MINOR(csr->version));
>+ CSR_VERSION_MAJOR(dmc->version),
>+ CSR_VERSION_MINOR(dmc->version));
> }
>
> err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
>--
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
2021-05-18 21:34 ` [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc Anusha Srivatsa
@ 2021-05-18 21:34 ` Anusha Srivatsa
2021-05-19 5:42 ` Lucas De Marchi
2021-05-18 21:34 ` [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr Anusha Srivatsa
` (6 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Anusha Srivatsa @ 2021-05-18 21:34 UTC (permalink / raw)
To: intel-gfx
No functional change.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
7 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index a22339ebdffd..5ed286dc6720 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -315,9 +315,9 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
u32 *payload = dev_priv->dmc.dmc_payload;
u32 i, fw_size;
- if (!HAS_CSR(dev_priv)) {
+ if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
- "No CSR support available for this platform\n");
+ "No DMC support available for this platform\n");
return;
}
@@ -686,7 +686,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
- if (!HAS_CSR(dev_priv))
+ if (!HAS_DMC(dev_priv))
return;
/*
@@ -776,7 +776,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
*/
void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
{
- if (!HAS_CSR(dev_priv))
+ if (!HAS_DMC(dev_priv))
return;
flush_work(&dev_priv->dmc.work);
@@ -795,7 +795,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
*/
void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
{
- if (!HAS_CSR(dev_priv))
+ if (!HAS_DMC(dev_priv))
return;
/*
@@ -815,7 +815,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
*/
void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
{
- if (!HAS_CSR(dev_priv))
+ if (!HAS_DMC(dev_priv))
return;
intel_csr_ucode_suspend(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index a875f3c9b358..6cd7f8c1724f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -535,7 +535,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
struct intel_dmc *dmc;
i915_reg_t dc5_reg, dc6_reg = {};
- if (!HAS_CSR(dev_priv))
+ if (!HAS_DMC(dev_priv))
return -ENODEV;
dmc = &dev_priv->dmc;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c9f6bbb5dd7..469783003309 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1662,7 +1662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
-#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
+#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
#define HAS_MSO(i915) (INTEL_GEN(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 03d1221de13b..06828ff90ccf 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -788,7 +788,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
- if (HAS_CSR(m->i915)) {
+ if (HAS_DMC(m->i915)) {
struct intel_dmc *dmc = &m->i915->dmc;
err_printf(m, "DMC loaded: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 574881c0e339..97c98f4fb265 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -643,7 +643,7 @@ static const struct intel_device_info chv_info = {
GEN8_FEATURES, \
GEN(9), \
GEN9_DEFAULT_PAGE_SIZES, \
- .display.has_csr = 1, \
+ .display.has_dmc = 1, \
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
@@ -698,7 +698,7 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
- .display.has_csr = 1, \
+ .display.has_dmc = 1, \
.has_rc6 = 1, \
.has_rps = true, \
.display.has_dp_mst = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 8cb58a238c68..e16599b67b83 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -353,7 +353,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->display.has_fbc = 0;
if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
- info->display.has_csr = 0;
+ info->display.has_dmc = 0;
if (INTEL_GEN(dev_priv) >= 10 &&
(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e98b36959736..1390fad5ec06 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -141,7 +141,7 @@ enum intel_ppgtt_type {
#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
/* Keep in alphabetical order */ \
func(cursor_needs_physical); \
- func(has_csr); \
+ func(has_dmc); \
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC
2021-05-18 21:34 ` [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC Anusha Srivatsa
@ 2021-05-19 5:42 ` Lucas De Marchi
0 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2021-05-19 5:42 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Tue, May 18, 2021 at 02:34:41PM -0700, Anusha Srivatsa wrote:
>No functional change.
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_csr.c | 12 ++++++------
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 7 files changed, 13 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>index a22339ebdffd..5ed286dc6720 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
>@@ -315,9 +315,9 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
> u32 *payload = dev_priv->dmc.dmc_payload;
> u32 i, fw_size;
>
>- if (!HAS_CSR(dev_priv)) {
>+ if (!HAS_DMC(dev_priv)) {
> drm_err(&dev_priv->drm,
>- "No CSR support available for this platform\n");
>+ "No DMC support available for this platform\n");
> return;
> }
>
>@@ -686,7 +686,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>
> INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
>
>- if (!HAS_CSR(dev_priv))
>+ if (!HAS_DMC(dev_priv))
> return;
>
> /*
>@@ -776,7 +776,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> */
> void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
> {
>- if (!HAS_CSR(dev_priv))
>+ if (!HAS_DMC(dev_priv))
> return;
>
> flush_work(&dev_priv->dmc.work);
>@@ -795,7 +795,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
> */
> void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
> {
>- if (!HAS_CSR(dev_priv))
>+ if (!HAS_DMC(dev_priv))
> return;
>
> /*
>@@ -815,7 +815,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
> */
> void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
> {
>- if (!HAS_CSR(dev_priv))
>+ if (!HAS_DMC(dev_priv))
> return;
>
> intel_csr_ucode_suspend(dev_priv);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index a875f3c9b358..6cd7f8c1724f 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -535,7 +535,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> struct intel_dmc *dmc;
> i915_reg_t dc5_reg, dc6_reg = {};
>
>- if (!HAS_CSR(dev_priv))
>+ if (!HAS_DMC(dev_priv))
> return -ENODEV;
>
> dmc = &dev_priv->dmc;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 3c9f6bbb5dd7..469783003309 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1662,7 +1662,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
>
>-#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
>+#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
>
> #define HAS_MSO(i915) (INTEL_GEN(i915) >= 12)
>
>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>index 03d1221de13b..06828ff90ccf 100644
>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>@@ -788,7 +788,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>
> err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
>- if (HAS_CSR(m->i915)) {
>+ if (HAS_DMC(m->i915)) {
> struct intel_dmc *dmc = &m->i915->dmc;
>
> err_printf(m, "DMC loaded: %s\n",
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 574881c0e339..97c98f4fb265 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -643,7 +643,7 @@ static const struct intel_device_info chv_info = {
> GEN8_FEATURES, \
> GEN(9), \
> GEN9_DEFAULT_PAGE_SIZES, \
>- .display.has_csr = 1, \
>+ .display.has_dmc = 1, \
> .has_gt_uc = 1, \
> .display.has_hdcp = 1, \
> .display.has_ipc = 1, \
>@@ -698,7 +698,7 @@ static const struct intel_device_info skl_gt4_info = {
> .display.has_psr = 1, \
> .display.has_psr_hw_tracking = 1, \
> .has_runtime_pm = 1, \
>- .display.has_csr = 1, \
>+ .display.has_dmc = 1, \
> .has_rc6 = 1, \
> .has_rps = true, \
> .display.has_dp_mst = 1, \
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index 8cb58a238c68..e16599b67b83 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -353,7 +353,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> info->display.has_fbc = 0;
>
> if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>- info->display.has_csr = 0;
>+ info->display.has_dmc = 0;
>
> if (INTEL_GEN(dev_priv) >= 10 &&
> (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index e98b36959736..1390fad5ec06 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -141,7 +141,7 @@ enum intel_ppgtt_type {
> #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> /* Keep in alphabetical order */ \
> func(cursor_needs_physical); \
>- func(has_csr); \
>+ func(has_dmc); \
> func(has_ddi); \
> func(has_dp_mst); \
> func(has_dsb); \
>--
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
2021-05-18 21:34 ` [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc Anusha Srivatsa
2021-05-18 21:34 ` [Intel-gfx] [CI 2/5] drm/i915/dmc: s/HAS_CSR/HAS_DMC Anusha Srivatsa
@ 2021-05-18 21:34 ` Anusha Srivatsa
2021-05-19 5:45 ` Lucas De Marchi
2021-05-18 21:34 ` [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr" Anusha Srivatsa
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Anusha Srivatsa @ 2021-05-18 21:34 UTC (permalink / raw)
To: intel-gfx
Rename all occurences of CSR_* with DMC_*
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 167 +++++++++---------
drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 16 +-
.../drm/i915/display/intel_display_power.c | 14 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 28 +--
6 files changed, 117 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 5ed286dc6720..f2124796ce77 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -30,10 +30,9 @@
#include "intel_de.h"
/**
- * DOC: csr support for dmc
+ * DOC: DMC firmware support
*
- * Display Context Save and Restore (CSR) firmware support added from gen9
- * onwards to drive newly added DMC (Display microcontroller) in display
+ * From gen9 onwards we have newly added DMC (Display microcontroller) in display
* engine to save and restore the state of display engine when it enter into
* low-power state and comes back to normal.
*/
@@ -44,55 +43,55 @@
__stringify(major) "_" \
__stringify(minor) ".bin"
-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
-#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01)
-#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
-MODULE_FIRMWARE(ADLS_CSR_PATH);
+#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
+#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_DMC_PATH);
-#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02)
-#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
-MODULE_FIRMWARE(DG1_CSR_PATH);
+#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02)
+#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
+MODULE_FIRMWARE(DG1_DMC_PATH);
-#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02)
-#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
-MODULE_FIRMWARE(RKL_CSR_PATH);
+#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02)
+#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
+MODULE_FIRMWARE(RKL_DMC_PATH);
-#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08)
-#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
-MODULE_FIRMWARE(TGL_CSR_PATH);
+#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08)
+#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
+MODULE_FIRMWARE(TGL_DMC_PATH);
-#define ICL_CSR_PATH DMC_PATH(icl, 1, 09)
-#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9)
-#define ICL_CSR_MAX_FW_SIZE 0x6000
-MODULE_FIRMWARE(ICL_CSR_PATH);
+#define ICL_DMC_PATH DMC_PATH(icl, 1, 09)
+#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9)
+#define ICL_DMC_MAX_FW_SIZE 0x6000
+MODULE_FIRMWARE(ICL_DMC_PATH);
-#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07)
-#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
-#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
-MODULE_FIRMWARE(CNL_CSR_PATH);
+#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07)
+#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
+#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE
+MODULE_FIRMWARE(CNL_DMC_PATH);
-#define GLK_CSR_PATH DMC_PATH(glk, 1, 04)
-#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
-#define GLK_CSR_MAX_FW_SIZE 0x4000
-MODULE_FIRMWARE(GLK_CSR_PATH);
+#define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
+#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
+#define GLK_DMC_MAX_FW_SIZE 0x4000
+MODULE_FIRMWARE(GLK_DMC_PATH);
-#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04)
-#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
-#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
-MODULE_FIRMWARE(KBL_CSR_PATH);
+#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04)
+#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
+#define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
+MODULE_FIRMWARE(KBL_DMC_PATH);
-#define SKL_CSR_PATH DMC_PATH(skl, 1, 27)
-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
-#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
-MODULE_FIRMWARE(SKL_CSR_PATH);
+#define SKL_DMC_PATH DMC_PATH(skl, 1, 27)
+#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27)
+#define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
+MODULE_FIRMWARE(SKL_DMC_PATH);
-#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07)
-#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
-#define BXT_CSR_MAX_FW_SIZE 0x3000
-MODULE_FIRMWARE(BXT_CSR_PATH);
+#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07)
+#define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
+#define BXT_DMC_MAX_FW_SIZE 0x3000
+MODULE_FIRMWARE(BXT_DMC_PATH);
-#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
+#define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
#define PACKAGE_MAX_FW_INFO_ENTRIES 20
#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
#define DMC_V1_MAX_MMIO_COUNT 8
@@ -333,7 +332,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
preempt_disable();
for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
+ intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
payload[i]);
preempt_enable();
@@ -357,7 +356,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
const struct stepping_info *si,
u8 package_ver)
{
- u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
+ u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
unsigned int i;
for (i = 0; i < num_entries; i++) {
@@ -458,8 +457,8 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
- mmioaddr[i] > CSR_MMIO_END_RANGE) {
+ if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
+ mmioaddr[i] > DMC_MMIO_END_RANGE) {
DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
mmioaddr[i]);
return 0;
@@ -543,7 +542,7 @@ parse_csr_fw_package(struct intel_dmc *dmc,
((u8 *)package_header + sizeof(*package_header));
dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
package_header->header_ver);
- if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
+ if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
DRM_ERROR("DMC firmware not supported for %c stepping\n",
si->stepping);
return 0;
@@ -579,10 +578,10 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc,
css_header->version != dmc->required_version) {
DRM_INFO("Refusing to load DMC firmware v%u.%u,"
" please use v%u.%u\n",
- CSR_VERSION_MAJOR(css_header->version),
- CSR_VERSION_MINOR(css_header->version),
- CSR_VERSION_MAJOR(dmc->required_version),
- CSR_VERSION_MINOR(dmc->required_version));
+ DMC_VERSION_MAJOR(css_header->version),
+ DMC_VERSION_MINOR(css_header->version),
+ DMC_VERSION_MAJOR(dmc->required_version),
+ DMC_VERSION_MINOR(dmc->required_version));
return 0;
}
@@ -659,8 +658,8 @@ static void csr_load_work_fn(struct work_struct *work)
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
- dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version),
- CSR_VERSION_MINOR(dmc->version));
+ dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
+ DMC_VERSION_MINOR(dmc->version));
} else {
drm_notice(&dev_priv->drm,
"Failed to load DMC firmware %s."
@@ -690,57 +689,57 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
return;
/*
- * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
+ * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
* runtime-suspend.
*
* On error, we return with the rpm wakeref held to prevent runtime
- * suspend as runtime suspend *requires* a working CSR for whatever
+ * suspend as runtime suspend *requires* a working DMC for whatever
* reason.
*/
intel_csr_runtime_pm_get(dev_priv);
if (IS_ALDERLAKE_S(dev_priv)) {
- dmc->fw_path = ADLS_CSR_PATH;
- dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = ADLS_DMC_PATH;
+ dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
} else if (IS_DG1(dev_priv)) {
- dmc->fw_path = DG1_CSR_PATH;
- dmc->required_version = DG1_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = DG1_DMC_PATH;
+ dmc->required_version = DG1_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dmc->fw_path = RKL_CSR_PATH;
- dmc->required_version = RKL_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = RKL_DMC_PATH;
+ dmc->required_version = RKL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dmc->fw_path = TGL_CSR_PATH;
- dmc->required_version = TGL_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = TGL_DMC_PATH;
+ dmc->required_version = TGL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) == 11) {
- dmc->fw_path = ICL_CSR_PATH;
- dmc->required_version = ICL_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = ICL_DMC_PATH;
+ dmc->required_version = ICL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
} else if (IS_CANNONLAKE(dev_priv)) {
- dmc->fw_path = CNL_CSR_PATH;
- dmc->required_version = CNL_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = CNL_DMC_PATH;
+ dmc->required_version = CNL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
} else if (IS_GEMINILAKE(dev_priv)) {
- dmc->fw_path = GLK_CSR_PATH;
- dmc->required_version = GLK_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
+ dmc->fw_path = GLK_DMC_PATH;
+ dmc->required_version = GLK_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
} else if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
- dmc->fw_path = KBL_CSR_PATH;
- dmc->required_version = KBL_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = KBL_DMC_PATH;
+ dmc->required_version = KBL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
} else if (IS_SKYLAKE(dev_priv)) {
- dmc->fw_path = SKL_CSR_PATH;
- dmc->required_version = SKL_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = SKL_DMC_PATH;
+ dmc->required_version = SKL_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
} else if (IS_BROXTON(dev_priv)) {
- dmc->fw_path = BXT_CSR_PATH;
- dmc->required_version = BXT_CSR_VERSION_REQUIRED;
- dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
+ dmc->fw_path = BXT_DMC_PATH;
+ dmc->required_version = BXT_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
}
if (dev_priv->params.dmc_firmware_path) {
diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
index 03c64f8af7ab..984e9fb250f8 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.h
+++ b/drivers/gpu/drm/i915/display/intel_csr.h
@@ -8,9 +8,9 @@
struct drm_i915_private;
-#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
-#define CSR_VERSION_MAJOR(version) ((version) >> 16)
-#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
+#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
+#define DMC_VERSION_MAJOR(version) ((version) >> 16)
+#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
void intel_csr_ucode_init(struct drm_i915_private *i915);
void intel_csr_load_program(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 6cd7f8c1724f..e43abdf0e3d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -548,8 +548,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
if (!dmc->dmc_payload)
goto out;
- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version),
- CSR_VERSION_MINOR(dmc->version));
+ seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
+ DMC_VERSION_MINOR(dmc->version));
if (DISPLAY_VER(dev_priv) >= 12) {
if (IS_DGFX(dev_priv)) {
@@ -568,10 +568,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "DC3CO count: %d\n",
intel_de_read(dev_priv, DMC_DEBUG3));
} else {
- dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
- SKL_CSR_DC3_DC5_COUNT;
+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
+ SKL_DMC_DC3_DC5_COUNT;
if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
- dc6_reg = SKL_CSR_DC5_DC6_COUNT;
+ dc6_reg = SKL_DMC_DC5_DC6_COUNT;
}
seq_printf(m, "DC3 -> DC5 count: %d\n",
@@ -582,10 +582,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, CSR_PROGRAM(0)));
+ intel_de_read(dev_priv, DMC_PROGRAM(0)));
seq_printf(m, "ssp base: 0x%08x\n",
- intel_de_read(dev_priv, CSR_SSP_BASE));
- seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
+ intel_de_read(dev_priv, DMC_SSP_BASE));
+ seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0a05d0f90f28..de58abdd838b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,12 +961,12 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
static void assert_csr_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, CSR_PROGRAM(0)),
- "CSR program storage start is NULL\n");
- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_SSP_BASE),
- "CSR SSP Base Not fine\n");
- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_HTP_SKL),
- "CSR HTP Not fine\n");
+ !intel_de_read(dev_priv, DMC_PROGRAM(0)),
+ "DMC program storage start is NULL\n");
+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
+ "DMC SSP Base Not fine\n");
+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
+ "DMC HTP Not fine\n");
}
static struct i915_power_well *
@@ -6218,7 +6218,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
/*
* In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
* support don't manually deinit the power domains. This also means the
- * CSR/DMC firmware will stay active, it will power down any HW
+ * DMC firmware will stay active, it will power down any HW
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 06828ff90ccf..edd108d41318 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -794,8 +794,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "DMC loaded: %s\n",
yesno(dmc->dmc_payload));
err_printf(m, "DMC fw version: %d.%d\n",
- CSR_VERSION_MAJOR(dmc->version),
- CSR_VERSION_MINOR(dmc->version));
+ DMC_VERSION_MAJOR(dmc->version),
+ DMC_VERSION_MINOR(dmc->version));
}
err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 089b5a59bed3..73a33ffc0559 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7686,20 +7686,20 @@ enum {
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
-/* DMC/CSR */
-#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
-#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
-#define CSR_HTP_ADDR_SKL 0x00500034
-#define CSR_SSP_BASE _MMIO(0x8F074)
-#define CSR_HTP_SKL _MMIO(0x8F004)
-#define CSR_LAST_WRITE _MMIO(0x8F034)
-#define CSR_LAST_WRITE_VALUE 0xc003b400
-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
-#define CSR_MMIO_START_RANGE 0x80000
-#define CSR_MMIO_END_RANGE 0x8FFFF
-#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
-#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
-#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
+/* DMC */
+#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
+#define DMC_HTP_ADDR_SKL 0x00500034
+#define DMC_SSP_BASE _MMIO(0x8F074)
+#define DMC_HTP_SKL _MMIO(0x8F004)
+#define DMC_LAST_WRITE _MMIO(0x8F034)
+#define DMC_LAST_WRITE_VALUE 0xc003b400
+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
+#define DMC_MMIO_START_RANGE 0x80000
+#define DMC_MMIO_END_RANGE 0x8FFFF
+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
2021-05-18 21:34 ` [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr Anusha Srivatsa
@ 2021-05-19 5:45 ` Lucas De Marchi
2021-05-21 7:45 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Lucas De Marchi @ 2021-05-19 5:45 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote:
>Rename all occurences of CSR_* with DMC_*
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_csr.c | 167 +++++++++---------
> drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
> .../drm/i915/display/intel_display_debugfs.c | 16 +-
> .../drm/i915/display/intel_display_power.c | 14 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 28 +--
> 6 files changed, 117 insertions(+), 118 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>index 5ed286dc6720..f2124796ce77 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
>@@ -30,10 +30,9 @@
> #include "intel_de.h"
>
> /**
>- * DOC: csr support for dmc
>+ * DOC: DMC firmware support
> *
>- * Display Context Save and Restore (CSR) firmware support added from gen9
>- * onwards to drive newly added DMC (Display microcontroller) in display
>+ * From gen9 onwards we have newly added DMC (Display microcontroller) in display
> * engine to save and restore the state of display engine when it enter into
> * low-power state and comes back to normal.
> */
>@@ -44,55 +43,55 @@
> __stringify(major) "_" \
> __stringify(minor) ".bin"
>
>-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
>+#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
>
>-#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01)
>-#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
>-MODULE_FIRMWARE(ADLS_CSR_PATH);
>+#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
>+#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
>+MODULE_FIRMWARE(ADLS_DMC_PATH);
>
>-#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02)
>-#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
>-MODULE_FIRMWARE(DG1_CSR_PATH);
>+#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02)
>+#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
>+MODULE_FIRMWARE(DG1_DMC_PATH);
>
>-#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02)
>-#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
>-MODULE_FIRMWARE(RKL_CSR_PATH);
>+#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02)
>+#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
>+MODULE_FIRMWARE(RKL_DMC_PATH);
>
>-#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08)
>-#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
>-MODULE_FIRMWARE(TGL_CSR_PATH);
>+#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08)
>+#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
>+MODULE_FIRMWARE(TGL_DMC_PATH);
>
>-#define ICL_CSR_PATH DMC_PATH(icl, 1, 09)
>-#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9)
>-#define ICL_CSR_MAX_FW_SIZE 0x6000
>-MODULE_FIRMWARE(ICL_CSR_PATH);
>+#define ICL_DMC_PATH DMC_PATH(icl, 1, 09)
>+#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9)
>+#define ICL_DMC_MAX_FW_SIZE 0x6000
>+MODULE_FIRMWARE(ICL_DMC_PATH);
>
>-#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07)
>-#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>-#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
>-MODULE_FIRMWARE(CNL_CSR_PATH);
>+#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07)
>+#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
>+#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE
>+MODULE_FIRMWARE(CNL_DMC_PATH);
>
>-#define GLK_CSR_PATH DMC_PATH(glk, 1, 04)
>-#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>-#define GLK_CSR_MAX_FW_SIZE 0x4000
>-MODULE_FIRMWARE(GLK_CSR_PATH);
>+#define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
>+#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
>+#define GLK_DMC_MAX_FW_SIZE 0x4000
>+MODULE_FIRMWARE(GLK_DMC_PATH);
>
>-#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04)
>-#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>-#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
>-MODULE_FIRMWARE(KBL_CSR_PATH);
>+#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04)
>+#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
>+#define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
>+MODULE_FIRMWARE(KBL_DMC_PATH);
>
>-#define SKL_CSR_PATH DMC_PATH(skl, 1, 27)
>-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
>-#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
>-MODULE_FIRMWARE(SKL_CSR_PATH);
>+#define SKL_DMC_PATH DMC_PATH(skl, 1, 27)
>+#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27)
>+#define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
>+MODULE_FIRMWARE(SKL_DMC_PATH);
>
>-#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07)
>-#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>-#define BXT_CSR_MAX_FW_SIZE 0x3000
>-MODULE_FIRMWARE(BXT_CSR_PATH);
>+#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07)
>+#define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
>+#define BXT_DMC_MAX_FW_SIZE 0x3000
>+MODULE_FIRMWARE(BXT_DMC_PATH);
>
>-#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
>+#define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
> #define PACKAGE_MAX_FW_INFO_ENTRIES 20
> #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
> #define DMC_V1_MAX_MMIO_COUNT 8
>@@ -333,7 +332,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
> preempt_disable();
>
> for (i = 0; i < fw_size; i++)
>- intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
>+ intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
> payload[i]);
>
> preempt_enable();
>@@ -357,7 +356,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
> const struct stepping_info *si,
> u8 package_ver)
> {
>- u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
>+ u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
> unsigned int i;
>
> for (i = 0; i < num_entries; i++) {
>@@ -458,8 +457,8 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
> }
>
> for (i = 0; i < mmio_count; i++) {
>- if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
>- mmioaddr[i] > CSR_MMIO_END_RANGE) {
>+ if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
>+ mmioaddr[i] > DMC_MMIO_END_RANGE) {
> DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
> mmioaddr[i]);
> return 0;
>@@ -543,7 +542,7 @@ parse_csr_fw_package(struct intel_dmc *dmc,
> ((u8 *)package_header + sizeof(*package_header));
> dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
> package_header->header_ver);
>- if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
>+ if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
> DRM_ERROR("DMC firmware not supported for %c stepping\n",
> si->stepping);
> return 0;
>@@ -579,10 +578,10 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc,
> css_header->version != dmc->required_version) {
> DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> " please use v%u.%u\n",
>- CSR_VERSION_MAJOR(css_header->version),
>- CSR_VERSION_MINOR(css_header->version),
>- CSR_VERSION_MAJOR(dmc->required_version),
>- CSR_VERSION_MINOR(dmc->required_version));
>+ DMC_VERSION_MAJOR(css_header->version),
>+ DMC_VERSION_MINOR(css_header->version),
>+ DMC_VERSION_MAJOR(dmc->required_version),
>+ DMC_VERSION_MINOR(dmc->required_version));
> return 0;
> }
>
>@@ -659,8 +658,8 @@ static void csr_load_work_fn(struct work_struct *work)
>
> drm_info(&dev_priv->drm,
> "Finished loading DMC firmware %s (v%u.%u)\n",
>- dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version),
>- CSR_VERSION_MINOR(dmc->version));
>+ dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
>+ DMC_VERSION_MINOR(dmc->version));
> } else {
> drm_notice(&dev_priv->drm,
> "Failed to load DMC firmware %s."
>@@ -690,57 +689,57 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> return;
>
> /*
>- * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
>+ * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
> * runtime-suspend.
> *
> * On error, we return with the rpm wakeref held to prevent runtime
>- * suspend as runtime suspend *requires* a working CSR for whatever
>+ * suspend as runtime suspend *requires* a working DMC for whatever
> * reason.
> */
> intel_csr_runtime_pm_get(dev_priv);
>
> if (IS_ALDERLAKE_S(dev_priv)) {
>- dmc->fw_path = ADLS_CSR_PATH;
>- dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = ADLS_DMC_PATH;
>+ dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> } else if (IS_DG1(dev_priv)) {
>- dmc->fw_path = DG1_CSR_PATH;
>- dmc->required_version = DG1_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = DG1_DMC_PATH;
>+ dmc->required_version = DG1_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> } else if (IS_ROCKETLAKE(dev_priv)) {
>- dmc->fw_path = RKL_CSR_PATH;
>- dmc->required_version = RKL_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = RKL_DMC_PATH;
>+ dmc->required_version = RKL_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
>- dmc->fw_path = TGL_CSR_PATH;
>- dmc->required_version = TGL_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = TGL_DMC_PATH;
>+ dmc->required_version = TGL_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> } else if (DISPLAY_VER(dev_priv) == 11) {
>- dmc->fw_path = ICL_CSR_PATH;
>- dmc->required_version = ICL_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = ICL_DMC_PATH;
>+ dmc->required_version = ICL_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
> } else if (IS_CANNONLAKE(dev_priv)) {
>- dmc->fw_path = CNL_CSR_PATH;
>- dmc->required_version = CNL_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = CNL_DMC_PATH;
>+ dmc->required_version = CNL_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
> } else if (IS_GEMINILAKE(dev_priv)) {
>- dmc->fw_path = GLK_CSR_PATH;
>- dmc->required_version = GLK_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = GLK_DMC_PATH;
>+ dmc->required_version = GLK_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
> } else if (IS_KABYLAKE(dev_priv) ||
> IS_COFFEELAKE(dev_priv) ||
> IS_COMETLAKE(dev_priv)) {
>- dmc->fw_path = KBL_CSR_PATH;
>- dmc->required_version = KBL_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = KBL_DMC_PATH;
>+ dmc->required_version = KBL_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
> } else if (IS_SKYLAKE(dev_priv)) {
>- dmc->fw_path = SKL_CSR_PATH;
>- dmc->required_version = SKL_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = SKL_DMC_PATH;
>+ dmc->required_version = SKL_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
> } else if (IS_BROXTON(dev_priv)) {
>- dmc->fw_path = BXT_CSR_PATH;
>- dmc->required_version = BXT_CSR_VERSION_REQUIRED;
>- dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
>+ dmc->fw_path = BXT_DMC_PATH;
>+ dmc->required_version = BXT_DMC_VERSION_REQUIRED;
>+ dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
> }
>
> if (dev_priv->params.dmc_firmware_path) {
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
>index 03c64f8af7ab..984e9fb250f8 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.h
>+++ b/drivers/gpu/drm/i915/display/intel_csr.h
>@@ -8,9 +8,9 @@
>
> struct drm_i915_private;
>
>-#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
>-#define CSR_VERSION_MAJOR(version) ((version) >> 16)
>-#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
>+#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
>+#define DMC_VERSION_MAJOR(version) ((version) >> 16)
>+#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
>
> void intel_csr_ucode_init(struct drm_i915_private *i915);
> void intel_csr_load_program(struct drm_i915_private *i915);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index 6cd7f8c1724f..e43abdf0e3d9 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -548,8 +548,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> if (!dmc->dmc_payload)
> goto out;
>
>- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version),
>- CSR_VERSION_MINOR(dmc->version));
>+ seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
>+ DMC_VERSION_MINOR(dmc->version));
>
> if (DISPLAY_VER(dev_priv) >= 12) {
> if (IS_DGFX(dev_priv)) {
>@@ -568,10 +568,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> seq_printf(m, "DC3CO count: %d\n",
> intel_de_read(dev_priv, DMC_DEBUG3));
> } else {
>- dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>- SKL_CSR_DC3_DC5_COUNT;
>+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
>+ SKL_DMC_DC3_DC5_COUNT;
> if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
>- dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>+ dc6_reg = SKL_DMC_DC5_DC6_COUNT;
> }
>
> seq_printf(m, "DC3 -> DC5 count: %d\n",
>@@ -582,10 +582,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>
> out:
> seq_printf(m, "program base: 0x%08x\n",
>- intel_de_read(dev_priv, CSR_PROGRAM(0)));
>+ intel_de_read(dev_priv, DMC_PROGRAM(0)));
> seq_printf(m, "ssp base: 0x%08x\n",
>- intel_de_read(dev_priv, CSR_SSP_BASE));
>- seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
>+ intel_de_read(dev_priv, DMC_SSP_BASE));
>+ seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
>
> intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 0a05d0f90f28..de58abdd838b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -961,12 +961,12 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> static void assert_csr_loaded(struct drm_i915_private *dev_priv)
> {
> drm_WARN_ONCE(&dev_priv->drm,
>- !intel_de_read(dev_priv, CSR_PROGRAM(0)),
>- "CSR program storage start is NULL\n");
>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_SSP_BASE),
>- "CSR SSP Base Not fine\n");
>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_HTP_SKL),
>- "CSR HTP Not fine\n");
>+ !intel_de_read(dev_priv, DMC_PROGRAM(0)),
>+ "DMC program storage start is NULL\n");
>+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
>+ "DMC SSP Base Not fine\n");
>+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>+ "DMC HTP Not fine\n");
> }
>
> static struct i915_power_well *
>@@ -6218,7 +6218,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
> /*
> * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
> * support don't manually deinit the power domains. This also means the
>- * CSR/DMC firmware will stay active, it will power down any HW
>+ * DMC firmware will stay active, it will power down any HW
> * resources as required and also enable deeper system power states
> * that would be blocked if the firmware was inactive.
> */
>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>index 06828ff90ccf..edd108d41318 100644
>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>@@ -794,8 +794,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
> err_printf(m, "DMC loaded: %s\n",
> yesno(dmc->dmc_payload));
> err_printf(m, "DMC fw version: %d.%d\n",
>- CSR_VERSION_MAJOR(dmc->version),
>- CSR_VERSION_MINOR(dmc->version));
>+ DMC_VERSION_MAJOR(dmc->version),
>+ DMC_VERSION_MINOR(dmc->version));
> }
>
> err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 089b5a59bed3..73a33ffc0559 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7686,20 +7686,20 @@ enum {
> #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
> #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
>
>-/* DMC/CSR */
>-#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
>-#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
>-#define CSR_HTP_ADDR_SKL 0x00500034
>-#define CSR_SSP_BASE _MMIO(0x8F074)
>-#define CSR_HTP_SKL _MMIO(0x8F004)
>-#define CSR_LAST_WRITE _MMIO(0x8F034)
>-#define CSR_LAST_WRITE_VALUE 0xc003b400
>-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
>-#define CSR_MMIO_START_RANGE 0x80000
>-#define CSR_MMIO_END_RANGE 0x8FFFF
>-#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
>-#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
>-#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
>+/* DMC */
>+#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
>+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
>+#define DMC_HTP_ADDR_SKL 0x00500034
>+#define DMC_SSP_BASE _MMIO(0x8F074)
>+#define DMC_HTP_SKL _MMIO(0x8F004)
>+#define DMC_LAST_WRITE _MMIO(0x8F034)
>+#define DMC_LAST_WRITE_VALUE 0xc003b400
>+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
>+#define DMC_MMIO_START_RANGE 0x80000
>+#define DMC_MMIO_END_RANGE 0x8FFFF
>+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
>+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
>+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
> #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
> #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
> #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
>--
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
2021-05-19 5:45 ` Lucas De Marchi
@ 2021-05-21 7:45 ` Jani Nikula
2021-05-21 16:31 ` Srivatsa, Anusha
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2021-05-21 7:45 UTC (permalink / raw)
To: Lucas De Marchi, Anusha Srivatsa; +Cc: intel-gfx
On Tue, 18 May 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote:
>>Rename all occurences of CSR_* with DMC_*
>>
>>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
We failed to take GVT into account, and apparently neither CI or Anusha
has CONFIG_DRM_I915_GVT=y. They use the register definitions, and this
broke the build.
Anusha, please enable the config, and fix the fallout. Cc: the patch to
GVT folks for ack.
Thanks,
Jani.
>
> Lucas De Marchi
>
>>---
>> drivers/gpu/drm/i915/display/intel_csr.c | 167 +++++++++---------
>> drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
>> .../drm/i915/display/intel_display_debugfs.c | 16 +-
>> .../drm/i915/display/intel_display_power.c | 14 +-
>> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
>> drivers/gpu/drm/i915/i915_reg.h | 28 +--
>> 6 files changed, 117 insertions(+), 118 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>>index 5ed286dc6720..f2124796ce77 100644
>>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
>>@@ -30,10 +30,9 @@
>> #include "intel_de.h"
>>
>> /**
>>- * DOC: csr support for dmc
>>+ * DOC: DMC firmware support
>> *
>>- * Display Context Save and Restore (CSR) firmware support added from gen9
>>- * onwards to drive newly added DMC (Display microcontroller) in display
>>+ * From gen9 onwards we have newly added DMC (Display microcontroller) in display
>> * engine to save and restore the state of display engine when it enter into
>> * low-power state and comes back to normal.
>> */
>>@@ -44,55 +43,55 @@
>> __stringify(major) "_" \
>> __stringify(minor) ".bin"
>>
>>-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
>>+#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
>>
>>-#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01)
>>-#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
>>-MODULE_FIRMWARE(ADLS_CSR_PATH);
>>+#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
>>+#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
>>+MODULE_FIRMWARE(ADLS_DMC_PATH);
>>
>>-#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02)
>>-#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
>>-MODULE_FIRMWARE(DG1_CSR_PATH);
>>+#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02)
>>+#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
>>+MODULE_FIRMWARE(DG1_DMC_PATH);
>>
>>-#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02)
>>-#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
>>-MODULE_FIRMWARE(RKL_CSR_PATH);
>>+#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02)
>>+#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
>>+MODULE_FIRMWARE(RKL_DMC_PATH);
>>
>>-#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08)
>>-#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
>>-MODULE_FIRMWARE(TGL_CSR_PATH);
>>+#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08)
>>+#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
>>+MODULE_FIRMWARE(TGL_DMC_PATH);
>>
>>-#define ICL_CSR_PATH DMC_PATH(icl, 1, 09)
>>-#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9)
>>-#define ICL_CSR_MAX_FW_SIZE 0x6000
>>-MODULE_FIRMWARE(ICL_CSR_PATH);
>>+#define ICL_DMC_PATH DMC_PATH(icl, 1, 09)
>>+#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9)
>>+#define ICL_DMC_MAX_FW_SIZE 0x6000
>>+MODULE_FIRMWARE(ICL_DMC_PATH);
>>
>>-#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07)
>>-#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>>-#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
>>-MODULE_FIRMWARE(CNL_CSR_PATH);
>>+#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07)
>>+#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
>>+#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE
>>+MODULE_FIRMWARE(CNL_DMC_PATH);
>>
>>-#define GLK_CSR_PATH DMC_PATH(glk, 1, 04)
>>-#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>>-#define GLK_CSR_MAX_FW_SIZE 0x4000
>>-MODULE_FIRMWARE(GLK_CSR_PATH);
>>+#define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
>>+#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
>>+#define GLK_DMC_MAX_FW_SIZE 0x4000
>>+MODULE_FIRMWARE(GLK_DMC_PATH);
>>
>>-#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04)
>>-#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
>>-#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
>>-MODULE_FIRMWARE(KBL_CSR_PATH);
>>+#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04)
>>+#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
>>+#define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
>>+MODULE_FIRMWARE(KBL_DMC_PATH);
>>
>>-#define SKL_CSR_PATH DMC_PATH(skl, 1, 27)
>>-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
>>-#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
>>-MODULE_FIRMWARE(SKL_CSR_PATH);
>>+#define SKL_DMC_PATH DMC_PATH(skl, 1, 27)
>>+#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27)
>>+#define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
>>+MODULE_FIRMWARE(SKL_DMC_PATH);
>>
>>-#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07)
>>-#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>>-#define BXT_CSR_MAX_FW_SIZE 0x3000
>>-MODULE_FIRMWARE(BXT_CSR_PATH);
>>+#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07)
>>+#define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
>>+#define BXT_DMC_MAX_FW_SIZE 0x3000
>>+MODULE_FIRMWARE(BXT_DMC_PATH);
>>
>>-#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
>>+#define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
>> #define PACKAGE_MAX_FW_INFO_ENTRIES 20
>> #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
>> #define DMC_V1_MAX_MMIO_COUNT 8
>>@@ -333,7 +332,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
>> preempt_disable();
>>
>> for (i = 0; i < fw_size; i++)
>>- intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
>>+ intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
>> payload[i]);
>>
>> preempt_enable();
>>@@ -357,7 +356,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
>> const struct stepping_info *si,
>> u8 package_ver)
>> {
>>- u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
>>+ u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
>> unsigned int i;
>>
>> for (i = 0; i < num_entries; i++) {
>>@@ -458,8 +457,8 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
>> }
>>
>> for (i = 0; i < mmio_count; i++) {
>>- if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
>>- mmioaddr[i] > CSR_MMIO_END_RANGE) {
>>+ if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
>>+ mmioaddr[i] > DMC_MMIO_END_RANGE) {
>> DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
>> mmioaddr[i]);
>> return 0;
>>@@ -543,7 +542,7 @@ parse_csr_fw_package(struct intel_dmc *dmc,
>> ((u8 *)package_header + sizeof(*package_header));
>> dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
>> package_header->header_ver);
>>- if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
>>+ if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
>> DRM_ERROR("DMC firmware not supported for %c stepping\n",
>> si->stepping);
>> return 0;
>>@@ -579,10 +578,10 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc,
>> css_header->version != dmc->required_version) {
>> DRM_INFO("Refusing to load DMC firmware v%u.%u,"
>> " please use v%u.%u\n",
>>- CSR_VERSION_MAJOR(css_header->version),
>>- CSR_VERSION_MINOR(css_header->version),
>>- CSR_VERSION_MAJOR(dmc->required_version),
>>- CSR_VERSION_MINOR(dmc->required_version));
>>+ DMC_VERSION_MAJOR(css_header->version),
>>+ DMC_VERSION_MINOR(css_header->version),
>>+ DMC_VERSION_MAJOR(dmc->required_version),
>>+ DMC_VERSION_MINOR(dmc->required_version));
>> return 0;
>> }
>>
>>@@ -659,8 +658,8 @@ static void csr_load_work_fn(struct work_struct *work)
>>
>> drm_info(&dev_priv->drm,
>> "Finished loading DMC firmware %s (v%u.%u)\n",
>>- dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version),
>>- CSR_VERSION_MINOR(dmc->version));
>>+ dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
>>+ DMC_VERSION_MINOR(dmc->version));
>> } else {
>> drm_notice(&dev_priv->drm,
>> "Failed to load DMC firmware %s."
>>@@ -690,57 +689,57 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>> return;
>>
>> /*
>>- * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
>>+ * Obtain a runtime pm reference, until DMC is loaded, to avoid entering
>> * runtime-suspend.
>> *
>> * On error, we return with the rpm wakeref held to prevent runtime
>>- * suspend as runtime suspend *requires* a working CSR for whatever
>>+ * suspend as runtime suspend *requires* a working DMC for whatever
>> * reason.
>> */
>> intel_csr_runtime_pm_get(dev_priv);
>>
>> if (IS_ALDERLAKE_S(dev_priv)) {
>>- dmc->fw_path = ADLS_CSR_PATH;
>>- dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = ADLS_DMC_PATH;
>>+ dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>> } else if (IS_DG1(dev_priv)) {
>>- dmc->fw_path = DG1_CSR_PATH;
>>- dmc->required_version = DG1_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = DG1_DMC_PATH;
>>+ dmc->required_version = DG1_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>> } else if (IS_ROCKETLAKE(dev_priv)) {
>>- dmc->fw_path = RKL_CSR_PATH;
>>- dmc->required_version = RKL_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = RKL_DMC_PATH;
>>+ dmc->required_version = RKL_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>> } else if (DISPLAY_VER(dev_priv) >= 12) {
>>- dmc->fw_path = TGL_CSR_PATH;
>>- dmc->required_version = TGL_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = TGL_DMC_PATH;
>>+ dmc->required_version = TGL_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>> } else if (DISPLAY_VER(dev_priv) == 11) {
>>- dmc->fw_path = ICL_CSR_PATH;
>>- dmc->required_version = ICL_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = ICL_DMC_PATH;
>>+ dmc->required_version = ICL_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
>> } else if (IS_CANNONLAKE(dev_priv)) {
>>- dmc->fw_path = CNL_CSR_PATH;
>>- dmc->required_version = CNL_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = CNL_DMC_PATH;
>>+ dmc->required_version = CNL_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
>> } else if (IS_GEMINILAKE(dev_priv)) {
>>- dmc->fw_path = GLK_CSR_PATH;
>>- dmc->required_version = GLK_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = GLK_DMC_PATH;
>>+ dmc->required_version = GLK_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
>> } else if (IS_KABYLAKE(dev_priv) ||
>> IS_COFFEELAKE(dev_priv) ||
>> IS_COMETLAKE(dev_priv)) {
>>- dmc->fw_path = KBL_CSR_PATH;
>>- dmc->required_version = KBL_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = KBL_DMC_PATH;
>>+ dmc->required_version = KBL_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
>> } else if (IS_SKYLAKE(dev_priv)) {
>>- dmc->fw_path = SKL_CSR_PATH;
>>- dmc->required_version = SKL_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = SKL_DMC_PATH;
>>+ dmc->required_version = SKL_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
>> } else if (IS_BROXTON(dev_priv)) {
>>- dmc->fw_path = BXT_CSR_PATH;
>>- dmc->required_version = BXT_CSR_VERSION_REQUIRED;
>>- dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
>>+ dmc->fw_path = BXT_DMC_PATH;
>>+ dmc->required_version = BXT_DMC_VERSION_REQUIRED;
>>+ dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
>> }
>>
>> if (dev_priv->params.dmc_firmware_path) {
>>diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
>>index 03c64f8af7ab..984e9fb250f8 100644
>>--- a/drivers/gpu/drm/i915/display/intel_csr.h
>>+++ b/drivers/gpu/drm/i915/display/intel_csr.h
>>@@ -8,9 +8,9 @@
>>
>> struct drm_i915_private;
>>
>>-#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
>>-#define CSR_VERSION_MAJOR(version) ((version) >> 16)
>>-#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
>>+#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
>>+#define DMC_VERSION_MAJOR(version) ((version) >> 16)
>>+#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
>>
>> void intel_csr_ucode_init(struct drm_i915_private *i915);
>> void intel_csr_load_program(struct drm_i915_private *i915);
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>index 6cd7f8c1724f..e43abdf0e3d9 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>@@ -548,8 +548,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> if (!dmc->dmc_payload)
>> goto out;
>>
>>- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version),
>>- CSR_VERSION_MINOR(dmc->version));
>>+ seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
>>+ DMC_VERSION_MINOR(dmc->version));
>>
>> if (DISPLAY_VER(dev_priv) >= 12) {
>> if (IS_DGFX(dev_priv)) {
>>@@ -568,10 +568,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> seq_printf(m, "DC3CO count: %d\n",
>> intel_de_read(dev_priv, DMC_DEBUG3));
>> } else {
>>- dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>>- SKL_CSR_DC3_DC5_COUNT;
>>+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
>>+ SKL_DMC_DC3_DC5_COUNT;
>> if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
>>- dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>>+ dc6_reg = SKL_DMC_DC5_DC6_COUNT;
>> }
>>
>> seq_printf(m, "DC3 -> DC5 count: %d\n",
>>@@ -582,10 +582,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>>
>> out:
>> seq_printf(m, "program base: 0x%08x\n",
>>- intel_de_read(dev_priv, CSR_PROGRAM(0)));
>>+ intel_de_read(dev_priv, DMC_PROGRAM(0)));
>> seq_printf(m, "ssp base: 0x%08x\n",
>>- intel_de_read(dev_priv, CSR_SSP_BASE));
>>- seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL));
>>+ intel_de_read(dev_priv, DMC_SSP_BASE));
>>+ seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
>>
>> intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>index 0a05d0f90f28..de58abdd838b 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>@@ -961,12 +961,12 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
>> static void assert_csr_loaded(struct drm_i915_private *dev_priv)
>> {
>> drm_WARN_ONCE(&dev_priv->drm,
>>- !intel_de_read(dev_priv, CSR_PROGRAM(0)),
>>- "CSR program storage start is NULL\n");
>>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_SSP_BASE),
>>- "CSR SSP Base Not fine\n");
>>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_HTP_SKL),
>>- "CSR HTP Not fine\n");
>>+ !intel_de_read(dev_priv, DMC_PROGRAM(0)),
>>+ "DMC program storage start is NULL\n");
>>+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
>>+ "DMC SSP Base Not fine\n");
>>+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>>+ "DMC HTP Not fine\n");
>> }
>>
>> static struct i915_power_well *
>>@@ -6218,7 +6218,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
>> /*
>> * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9
>> * support don't manually deinit the power domains. This also means the
>>- * CSR/DMC firmware will stay active, it will power down any HW
>>+ * DMC firmware will stay active, it will power down any HW
>> * resources as required and also enable deeper system power states
>> * that would be blocked if the firmware was inactive.
>> */
>>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>>index 06828ff90ccf..edd108d41318 100644
>>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>>@@ -794,8 +794,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>> err_printf(m, "DMC loaded: %s\n",
>> yesno(dmc->dmc_payload));
>> err_printf(m, "DMC fw version: %d.%d\n",
>>- CSR_VERSION_MAJOR(dmc->version),
>>- CSR_VERSION_MINOR(dmc->version));
>>+ DMC_VERSION_MAJOR(dmc->version),
>>+ DMC_VERSION_MINOR(dmc->version));
>> }
>>
>> err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>index 089b5a59bed3..73a33ffc0559 100644
>>--- a/drivers/gpu/drm/i915/i915_reg.h
>>+++ b/drivers/gpu/drm/i915/i915_reg.h
>>@@ -7686,20 +7686,20 @@ enum {
>> #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
>> #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
>>
>>-/* DMC/CSR */
>>-#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
>>-#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
>>-#define CSR_HTP_ADDR_SKL 0x00500034
>>-#define CSR_SSP_BASE _MMIO(0x8F074)
>>-#define CSR_HTP_SKL _MMIO(0x8F004)
>>-#define CSR_LAST_WRITE _MMIO(0x8F034)
>>-#define CSR_LAST_WRITE_VALUE 0xc003b400
>>-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
>>-#define CSR_MMIO_START_RANGE 0x80000
>>-#define CSR_MMIO_END_RANGE 0x8FFFF
>>-#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
>>-#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
>>-#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
>>+/* DMC */
>>+#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
>>+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
>>+#define DMC_HTP_ADDR_SKL 0x00500034
>>+#define DMC_SSP_BASE _MMIO(0x8F074)
>>+#define DMC_HTP_SKL _MMIO(0x8F004)
>>+#define DMC_LAST_WRITE _MMIO(0x8F034)
>>+#define DMC_LAST_WRITE_VALUE 0xc003b400
>>+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
>>+#define DMC_MMIO_START_RANGE 0x80000
>>+#define DMC_MMIO_END_RANGE 0x8FFFF
>>+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
>>+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
>>+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
>> #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
>> #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
>> #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
>>--
>>2.25.0
>>
>>_______________________________________________
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr
2021-05-21 7:45 ` Jani Nikula
@ 2021-05-21 16:31 ` Srivatsa, Anusha
0 siblings, 0 replies; 18+ messages in thread
From: Srivatsa, Anusha @ 2021-05-21 16:31 UTC (permalink / raw)
To: Jani Nikula, De Marchi, Lucas; +Cc: intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, May 21, 2021 12:45 AM
> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names
> containing csr
>
> On Tue, 18 May 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> > On Tue, May 18, 2021 at 02:34:42PM -0700, Anusha Srivatsa wrote:
> >>Rename all occurences of CSR_* with DMC_*
> >>
> >>Cc: Jani Nikula <jani.nikula@linux.intel.com>
> >>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> We failed to take GVT into account, and apparently neither CI or Anusha has
> CONFIG_DRM_I915_GVT=y. They use the register definitions, and this broke
> the build.
>
> Anusha, please enable the config, and fix the fallout. Cc: the patch to GVT
> folks for ack.
On it.
Anusha
>
>
> Thanks,
> Jani.
>
>
>
> >
> > Lucas De Marchi
> >
> >>---
> >> drivers/gpu/drm/i915/display/intel_csr.c | 167 +++++++++---------
> >> drivers/gpu/drm/i915/display/intel_csr.h | 6 +-
> >> .../drm/i915/display/intel_display_debugfs.c | 16 +-
> >> .../drm/i915/display/intel_display_power.c | 14 +-
> >> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> >> drivers/gpu/drm/i915/i915_reg.h | 28 +--
> >> 6 files changed, 117 insertions(+), 118 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
> >>b/drivers/gpu/drm/i915/display/intel_csr.c
> >>index 5ed286dc6720..f2124796ce77 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_csr.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
> >>@@ -30,10 +30,9 @@
> >> #include "intel_de.h"
> >>
> >> /**
> >>- * DOC: csr support for dmc
> >>+ * DOC: DMC firmware support
> >> *
> >>- * Display Context Save and Restore (CSR) firmware support added from
> >>gen9
> >>- * onwards to drive newly added DMC (Display microcontroller) in
> >>display
> >>+ * From gen9 onwards we have newly added DMC (Display
> >>+ microcontroller) in display
> >> * engine to save and restore the state of display engine when it
> >>enter into
> >> * low-power state and comes back to normal.
> >> */
> >>@@ -44,55 +43,55 @@
> >> __stringify(major) "_" \
> >> __stringify(minor) ".bin"
> >>
> >>-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
> >>+#define GEN12_DMC_MAX_FW_SIZE
> ICL_DMC_MAX_FW_SIZE
> >>
> >>-#define ADLS_CSR_PATH DMC_PATH(adls, 2, 01)
> >>-#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
> >>-MODULE_FIRMWARE(ADLS_CSR_PATH);
> >>+#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
> >>+#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
> >>+MODULE_FIRMWARE(ADLS_DMC_PATH);
> >>
> >>-#define DG1_CSR_PATH DMC_PATH(dg1, 2, 02)
> >>-#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
> >>-MODULE_FIRMWARE(DG1_CSR_PATH);
> >>+#define DG1_DMC_PATH DMC_PATH(dg1, 2, 02)
> >>+#define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
> >>+MODULE_FIRMWARE(DG1_DMC_PATH);
> >>
> >>-#define RKL_CSR_PATH DMC_PATH(rkl, 2, 02)
> >>-#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
> >>-MODULE_FIRMWARE(RKL_CSR_PATH);
> >>+#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02)
> >>+#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2)
> >>+MODULE_FIRMWARE(RKL_DMC_PATH);
> >>
> >>-#define TGL_CSR_PATH DMC_PATH(tgl, 2, 08)
> >>-#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
> >>-MODULE_FIRMWARE(TGL_CSR_PATH);
> >>+#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08)
> >>+#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8)
> >>+MODULE_FIRMWARE(TGL_DMC_PATH);
> >>
> >>-#define ICL_CSR_PATH DMC_PATH(icl, 1, 09)
> >>-#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9)
> >>-#define ICL_CSR_MAX_FW_SIZE 0x6000
> >>-MODULE_FIRMWARE(ICL_CSR_PATH);
> >>+#define ICL_DMC_PATH DMC_PATH(icl, 1, 09)
> >>+#define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9)
> >>+#define ICL_DMC_MAX_FW_SIZE 0x6000
> >>+MODULE_FIRMWARE(ICL_DMC_PATH);
> >>
> >>-#define CNL_CSR_PATH DMC_PATH(cnl, 1, 07)
> >>-#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> >>-#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
> >>-MODULE_FIRMWARE(CNL_CSR_PATH);
> >>+#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07)
> >>+#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
> >>+#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE
> >>+MODULE_FIRMWARE(CNL_DMC_PATH);
> >>
> >>-#define GLK_CSR_PATH DMC_PATH(glk, 1, 04)
> >>-#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
> >>-#define GLK_CSR_MAX_FW_SIZE 0x4000
> >>-MODULE_FIRMWARE(GLK_CSR_PATH);
> >>+#define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
> >>+#define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
> >>+#define GLK_DMC_MAX_FW_SIZE 0x4000
> >>+MODULE_FIRMWARE(GLK_DMC_PATH);
> >>
> >>-#define KBL_CSR_PATH DMC_PATH(kbl, 1, 04)
> >>-#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
> >>-#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
> >>-MODULE_FIRMWARE(KBL_CSR_PATH);
> >>+#define KBL_DMC_PATH DMC_PATH(kbl, 1, 04)
> >>+#define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
> >>+#define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
> >>+MODULE_FIRMWARE(KBL_DMC_PATH);
> >>
> >>-#define SKL_CSR_PATH DMC_PATH(skl, 1, 27)
> >>-#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
> >>-#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
> >>-MODULE_FIRMWARE(SKL_CSR_PATH);
> >>+#define SKL_DMC_PATH DMC_PATH(skl, 1, 27)
> >>+#define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27)
> >>+#define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE
> >>+MODULE_FIRMWARE(SKL_DMC_PATH);
> >>
> >>-#define BXT_CSR_PATH DMC_PATH(bxt, 1, 07)
> >>-#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> >>-#define BXT_CSR_MAX_FW_SIZE 0x3000
> >>-MODULE_FIRMWARE(BXT_CSR_PATH);
> >>+#define BXT_DMC_PATH DMC_PATH(bxt, 1, 07)
> >>+#define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
> >>+#define BXT_DMC_MAX_FW_SIZE 0x3000
> >>+MODULE_FIRMWARE(BXT_DMC_PATH);
> >>
> >>-#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
> >>+#define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF
> >> #define PACKAGE_MAX_FW_INFO_ENTRIES 20
> >> #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
> >> #define DMC_V1_MAX_MMIO_COUNT 8
> >>@@ -333,7 +332,7 @@ void intel_csr_load_program(struct
> drm_i915_private *dev_priv)
> >> preempt_disable();
> >>
> >> for (i = 0; i < fw_size; i++)
> >>- intel_uncore_write_fw(&dev_priv->uncore,
> CSR_PROGRAM(i),
> >>+ intel_uncore_write_fw(&dev_priv->uncore,
> DMC_PROGRAM(i),
> >> payload[i]);
> >>
> >> preempt_enable();
> >>@@ -357,7 +356,7 @@ static u32 find_dmc_fw_offset(const struct
> intel_fw_info *fw_info,
> >> const struct stepping_info *si,
> >> u8 package_ver)
> >> {
> >>- u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
> >>+ u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
> >> unsigned int i;
> >>
> >> for (i = 0; i < num_entries; i++) {
> >>@@ -458,8 +457,8 @@ static u32 parse_csr_fw_dmc(struct intel_dmc
> *dmc,
> >> }
> >>
> >> for (i = 0; i < mmio_count; i++) {
> >>- if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
> >>- mmioaddr[i] > CSR_MMIO_END_RANGE) {
> >>+ if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
> >>+ mmioaddr[i] > DMC_MMIO_END_RANGE) {
> >> DRM_ERROR("DMC firmware has wrong mmio
> address 0x%x\n",
> >> mmioaddr[i]);
> >> return 0;
> >>@@ -543,7 +542,7 @@ parse_csr_fw_package(struct intel_dmc *dmc,
> >> ((u8 *)package_header + sizeof(*package_header));
> >> dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
> >> package_header->header_ver);
> >>- if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
> >>+ if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
> >> DRM_ERROR("DMC firmware not supported for %c
> stepping\n",
> >> si->stepping);
> >> return 0;
> >>@@ -579,10 +578,10 @@ static u32 parse_csr_fw_css(struct intel_dmc
> *dmc,
> >> css_header->version != dmc->required_version) {
> >> DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> >> " please use v%u.%u\n",
> >>- CSR_VERSION_MAJOR(css_header->version),
> >>- CSR_VERSION_MINOR(css_header->version),
> >>- CSR_VERSION_MAJOR(dmc->required_version),
> >>- CSR_VERSION_MINOR(dmc->required_version));
> >>+ DMC_VERSION_MAJOR(css_header->version),
> >>+ DMC_VERSION_MINOR(css_header->version),
> >>+ DMC_VERSION_MAJOR(dmc->required_version),
> >>+ DMC_VERSION_MINOR(dmc->required_version));
> >> return 0;
> >> }
> >>
> >>@@ -659,8 +658,8 @@ static void csr_load_work_fn(struct work_struct
> >>*work)
> >>
> >> drm_info(&dev_priv->drm,
> >> "Finished loading DMC firmware %s (v%u.%u)\n",
> >>- dev_priv->dmc.fw_path,
> CSR_VERSION_MAJOR(dmc->version),
> >>- CSR_VERSION_MINOR(dmc->version));
> >>+ dev_priv->dmc.fw_path,
> DMC_VERSION_MAJOR(dmc->version),
> >>+ DMC_VERSION_MINOR(dmc->version));
> >> } else {
> >> drm_notice(&dev_priv->drm,
> >> "Failed to load DMC firmware %s."
> >>@@ -690,57 +689,57 @@ void intel_csr_ucode_init(struct
> drm_i915_private *dev_priv)
> >> return;
> >>
> >> /*
> >>- * Obtain a runtime pm reference, until CSR is loaded, to avoid
> entering
> >>+ * Obtain a runtime pm reference, until DMC is loaded, to avoid
> >>+entering
> >> * runtime-suspend.
> >> *
> >> * On error, we return with the rpm wakeref held to prevent runtime
> >>- * suspend as runtime suspend *requires* a working CSR for
> whatever
> >>+ * suspend as runtime suspend *requires* a working DMC for
> whatever
> >> * reason.
> >> */
> >> intel_csr_runtime_pm_get(dev_priv);
> >>
> >> if (IS_ALDERLAKE_S(dev_priv)) {
> >>- dmc->fw_path = ADLS_CSR_PATH;
> >>- dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = ADLS_DMC_PATH;
> >>+ dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> >> } else if (IS_DG1(dev_priv)) {
> >>- dmc->fw_path = DG1_CSR_PATH;
> >>- dmc->required_version = DG1_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = DG1_DMC_PATH;
> >>+ dmc->required_version = DG1_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> >> } else if (IS_ROCKETLAKE(dev_priv)) {
> >>- dmc->fw_path = RKL_CSR_PATH;
> >>- dmc->required_version = RKL_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = RKL_DMC_PATH;
> >>+ dmc->required_version = RKL_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> >> } else if (DISPLAY_VER(dev_priv) >= 12) {
> >>- dmc->fw_path = TGL_CSR_PATH;
> >>- dmc->required_version = TGL_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = TGL_DMC_PATH;
> >>+ dmc->required_version = TGL_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
> >> } else if (DISPLAY_VER(dev_priv) == 11) {
> >>- dmc->fw_path = ICL_CSR_PATH;
> >>- dmc->required_version = ICL_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = ICL_DMC_PATH;
> >>+ dmc->required_version = ICL_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
> >> } else if (IS_CANNONLAKE(dev_priv)) {
> >>- dmc->fw_path = CNL_CSR_PATH;
> >>- dmc->required_version = CNL_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = CNL_DMC_PATH;
> >>+ dmc->required_version = CNL_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
> >> } else if (IS_GEMINILAKE(dev_priv)) {
> >>- dmc->fw_path = GLK_CSR_PATH;
> >>- dmc->required_version = GLK_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = GLK_DMC_PATH;
> >>+ dmc->required_version = GLK_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE;
> >> } else if (IS_KABYLAKE(dev_priv) ||
> >> IS_COFFEELAKE(dev_priv) ||
> >> IS_COMETLAKE(dev_priv)) {
> >>- dmc->fw_path = KBL_CSR_PATH;
> >>- dmc->required_version = KBL_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = KBL_DMC_PATH;
> >>+ dmc->required_version = KBL_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE;
> >> } else if (IS_SKYLAKE(dev_priv)) {
> >>- dmc->fw_path = SKL_CSR_PATH;
> >>- dmc->required_version = SKL_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = SKL_DMC_PATH;
> >>+ dmc->required_version = SKL_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE;
> >> } else if (IS_BROXTON(dev_priv)) {
> >>- dmc->fw_path = BXT_CSR_PATH;
> >>- dmc->required_version = BXT_CSR_VERSION_REQUIRED;
> >>- dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
> >>+ dmc->fw_path = BXT_DMC_PATH;
> >>+ dmc->required_version = BXT_DMC_VERSION_REQUIRED;
> >>+ dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE;
> >> }
> >>
> >> if (dev_priv->params.dmc_firmware_path) { diff --git
> >>a/drivers/gpu/drm/i915/display/intel_csr.h
> >>b/drivers/gpu/drm/i915/display/intel_csr.h
> >>index 03c64f8af7ab..984e9fb250f8 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_csr.h
> >>+++ b/drivers/gpu/drm/i915/display/intel_csr.h
> >>@@ -8,9 +8,9 @@
> >>
> >> struct drm_i915_private;
> >>
> >>-#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
> >>-#define CSR_VERSION_MAJOR(version) ((version) >> 16)
> >>-#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
> >>+#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
> >>+#define DMC_VERSION_MAJOR(version) ((version) >> 16)
> >>+#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
> >>
> >> void intel_csr_ucode_init(struct drm_i915_private *i915); void
> >>intel_csr_load_program(struct drm_i915_private *i915); diff --git
> >>a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>index 6cd7f8c1724f..e43abdf0e3d9 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >>@@ -548,8 +548,8 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> >> if (!dmc->dmc_payload)
> >> goto out;
> >>
> >>- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc-
> >version),
> >>- CSR_VERSION_MINOR(dmc->version));
> >>+ seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc-
> >version),
> >>+ DMC_VERSION_MINOR(dmc->version));
> >>
> >> if (DISPLAY_VER(dev_priv) >= 12) {
> >> if (IS_DGFX(dev_priv)) {
> >>@@ -568,10 +568,10 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> >> seq_printf(m, "DC3CO count: %d\n",
> >> intel_de_read(dev_priv, DMC_DEBUG3));
> >> } else {
> >>- dc5_reg = IS_BROXTON(dev_priv) ?
> BXT_CSR_DC3_DC5_COUNT :
> >>- SKL_CSR_DC3_DC5_COUNT;
> >>+ dc5_reg = IS_BROXTON(dev_priv) ?
> BXT_DMC_DC3_DC5_COUNT :
> >>+ SKL_DMC_DC3_DC5_COUNT;
> >> if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
> >>- dc6_reg = SKL_CSR_DC5_DC6_COUNT;
> >>+ dc6_reg = SKL_DMC_DC5_DC6_COUNT;
> >> }
> >>
> >> seq_printf(m, "DC3 -> DC5 count: %d\n", @@ -582,10 +582,10 @@
> static
> >>int i915_dmc_info(struct seq_file *m, void *unused)
> >>
> >> out:
> >> seq_printf(m, "program base: 0x%08x\n",
> >>- intel_de_read(dev_priv, CSR_PROGRAM(0)));
> >>+ intel_de_read(dev_priv, DMC_PROGRAM(0)));
> >> seq_printf(m, "ssp base: 0x%08x\n",
> >>- intel_de_read(dev_priv, CSR_SSP_BASE));
> >>- seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv,
> CSR_HTP_SKL));
> >>+ intel_de_read(dev_priv, DMC_SSP_BASE));
> >>+ seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv,
> >>+DMC_HTP_SKL));
> >>
> >> intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> >>
> >>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> >>b/drivers/gpu/drm/i915/display/intel_display_power.c
> >>index 0a05d0f90f28..de58abdd838b 100644
> >>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
> >>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> >>@@ -961,12 +961,12 @@ static void bxt_disable_dc9(struct
> >>drm_i915_private *dev_priv) static void assert_csr_loaded(struct
> >>drm_i915_private *dev_priv) {
> >> drm_WARN_ONCE(&dev_priv->drm,
> >>- !intel_de_read(dev_priv, CSR_PROGRAM(0)),
> >>- "CSR program storage start is NULL\n");
> >>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> CSR_SSP_BASE),
> >>- "CSR SSP Base Not fine\n");
> >>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> CSR_HTP_SKL),
> >>- "CSR HTP Not fine\n");
> >>+ !intel_de_read(dev_priv, DMC_PROGRAM(0)),
> >>+ "DMC program storage start is NULL\n");
> >>+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_SSP_BASE),
> >>+ "DMC SSP Base Not fine\n");
> >>+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_HTP_SKL),
> >>+ "DMC HTP Not fine\n");
> >> }
> >>
> >> static struct i915_power_well *
> >>@@ -6218,7 +6218,7 @@ void intel_power_domains_suspend(struct
> drm_i915_private *i915,
> >> /*
> >> * In case of suspend-to-idle (aka S0ix) on a DMC platform without
> DC9
> >> * support don't manually deinit the power domains. This also means
> the
> >>- * CSR/DMC firmware will stay active, it will power down any HW
> >>+ * DMC firmware will stay active, it will power down any HW
> >> * resources as required and also enable deeper system power states
> >> * that would be blocked if the firmware was inactive.
> >> */
> >>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> >>b/drivers/gpu/drm/i915/i915_gpu_error.c
> >>index 06828ff90ccf..edd108d41318 100644
> >>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
> >>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> >>@@ -794,8 +794,8 @@ static void __err_print_to_sgl(struct
> drm_i915_error_state_buf *m,
> >> err_printf(m, "DMC loaded: %s\n",
> >> yesno(dmc->dmc_payload));
> >> err_printf(m, "DMC fw version: %d.%d\n",
> >>- CSR_VERSION_MAJOR(dmc->version),
> >>- CSR_VERSION_MINOR(dmc->version));
> >>+ DMC_VERSION_MAJOR(dmc->version),
> >>+ DMC_VERSION_MINOR(dmc->version));
> >> }
> >>
> >> err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); diff
> >>--git a/drivers/gpu/drm/i915/i915_reg.h
> >>b/drivers/gpu/drm/i915/i915_reg.h index 089b5a59bed3..73a33ffc0559
> >>100644
> >>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>@@ -7686,20 +7686,20 @@ enum {
> >> #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
> >> #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 <<
> 0) /* icl + */
> >>
> >>-/* DMC/CSR */
> >>-#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
> >>-#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
> >>-#define CSR_HTP_ADDR_SKL 0x00500034
> >>-#define CSR_SSP_BASE _MMIO(0x8F074)
> >>-#define CSR_HTP_SKL _MMIO(0x8F004)
> >>-#define CSR_LAST_WRITE _MMIO(0x8F034)
> >>-#define CSR_LAST_WRITE_VALUE 0xc003b400
> >>-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
> >>-#define CSR_MMIO_START_RANGE 0x80000
> >>-#define CSR_MMIO_END_RANGE 0x8FFFF
> >>-#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
> >>-#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
> >>-#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> >>+/* DMC */
> >>+#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
> >>+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
> >>+#define DMC_HTP_ADDR_SKL 0x00500034
> >>+#define DMC_SSP_BASE _MMIO(0x8F074)
> >>+#define DMC_HTP_SKL _MMIO(0x8F004)
> >>+#define DMC_LAST_WRITE _MMIO(0x8F034)
> >>+#define DMC_LAST_WRITE_VALUE 0xc003b400
> >>+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
> >>+#define DMC_MMIO_START_RANGE 0x80000
> >>+#define DMC_MMIO_END_RANGE 0x8FFFF
> >>+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
> >>+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
> >>+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
> >> #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
> >> #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
> >> #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
> >>--
> >>2.25.0
> >>
> >>_______________________________________________
> >>Intel-gfx mailing list
> >>Intel-gfx@lists.freedesktop.org
> >>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr"
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
` (2 preceding siblings ...)
2021-05-18 21:34 ` [Intel-gfx] [CI 3/5] drm/i915/dmc: Rename macro names containing csr Anusha Srivatsa
@ 2021-05-18 21:34 ` Anusha Srivatsa
2021-05-19 5:46 ` Lucas De Marchi
2021-05-18 21:34 ` [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h Anusha Srivatsa
` (4 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Anusha Srivatsa @ 2021-05-18 21:34 UTC (permalink / raw)
To: intel-gfx
No functional change.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 64 +++++++++----------
drivers/gpu/drm/i915/display/intel_csr.h | 10 +--
drivers/gpu/drm/i915/display/intel_display.c | 14 ++--
.../drm/i915/display/intel_display_power.c | 14 ++--
drivers/gpu/drm/i915/i915_drv.c | 6 +-
5 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index f2124796ce77..ae1dfafaff9a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -302,14 +302,14 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
}
/**
- * intel_csr_load_program() - write the firmware from memory to register.
+ * intel_dmc_load_program() - write the firmware from memory to register.
* @dev_priv: i915 drm device.
*
- * CSR firmware is read from a .bin file and kept in internal memory one time.
+ * DMC firmware is read from a .bin file and kept in internal memory one time.
* Everytime display comes back from low power state this function is called to
* copy the firmware from internal memory to registers.
*/
-void intel_csr_load_program(struct drm_i915_private *dev_priv)
+void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
u32 *payload = dev_priv->dmc.dmc_payload;
u32 i, fw_size;
@@ -391,9 +391,9 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
return dmc_offset;
}
-static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
- const struct intel_dmc_header_base *dmc_header,
- size_t rem_size)
+static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
+ const struct intel_dmc_header_base *dmc_header,
+ size_t rem_size)
{
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
@@ -498,7 +498,7 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
}
static u32
-parse_csr_fw_package(struct intel_dmc *dmc,
+parse_dmc_fw_package(struct intel_dmc *dmc,
const struct intel_package_header *package_header,
const struct stepping_info *si,
size_t rem_size)
@@ -557,7 +557,7 @@ parse_csr_fw_package(struct intel_dmc *dmc,
}
/* Return number of bytes parsed or 0 on error */
-static u32 parse_csr_fw_css(struct intel_dmc *dmc,
+static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
@@ -590,7 +590,7 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc,
return sizeof(struct intel_css_header);
}
-static void parse_csr_fw(struct drm_i915_private *dev_priv,
+static void parse_dmc_fw(struct drm_i915_private *dev_priv,
const struct firmware *fw)
{
struct intel_css_header *css_header;
@@ -606,7 +606,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract CSS Header information */
css_header = (struct intel_css_header *)fw->data;
- r = parse_csr_fw_css(dmc, css_header, fw->size);
+ r = parse_dmc_fw_css(dmc, css_header, fw->size);
if (!r)
return;
@@ -614,7 +614,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract Package Header information */
package_header = (struct intel_package_header *)&fw->data[readcount];
- r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount);
+ r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
if (!r)
return;
@@ -622,17 +622,17 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract dmc_header information */
dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
- parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount);
+ parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
}
-static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
+static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
{
drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
dev_priv->dmc.wakeref =
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
-static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
+static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
{
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&dev_priv->dmc.wakeref);
@@ -640,7 +640,7 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
}
-static void csr_load_work_fn(struct work_struct *work)
+static void dmc_load_work_fn(struct work_struct *work)
{
struct drm_i915_private *dev_priv;
struct intel_dmc *dmc;
@@ -650,11 +650,11 @@ static void csr_load_work_fn(struct work_struct *work)
dmc = &dev_priv->dmc;
request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
- parse_csr_fw(dev_priv, fw);
+ parse_dmc_fw(dev_priv, fw);
if (dev_priv->dmc.dmc_payload) {
- intel_csr_load_program(dev_priv);
- intel_csr_runtime_pm_put(dev_priv);
+ intel_dmc_load_program(dev_priv);
+ intel_dmc_runtime_pm_put(dev_priv);
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
@@ -673,17 +673,17 @@ static void csr_load_work_fn(struct work_struct *work)
}
/**
- * intel_csr_ucode_init() - initialize the firmware loading.
+ * intel_dmc_ucode_init() - initialize the firmware loading.
* @dev_priv: i915 drm device.
*
* This function is called at the time of loading the display driver to read
* firmware from a .bin file and copied into a internal memory.
*/
-void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
+void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
+ INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
if (!HAS_DMC(dev_priv))
return;
@@ -696,7 +696,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
* suspend as runtime suspend *requires* a working DMC for whatever
* reason.
*/
- intel_csr_runtime_pm_get(dev_priv);
+ intel_dmc_runtime_pm_get(dev_priv);
if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
@@ -766,14 +766,14 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
}
/**
- * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
+ * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend
* @dev_priv: i915 drm device
*
* Prepare the DMC firmware before entering system suspend. This includes
* flushing pending work items and releasing any resources acquired during
* init.
*/
-void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
+void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
{
if (!HAS_DMC(dev_priv))
return;
@@ -782,17 +782,17 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
/* Drop the reference held in case DMC isn't loaded. */
if (!dev_priv->dmc.dmc_payload)
- intel_csr_runtime_pm_put(dev_priv);
+ intel_dmc_runtime_pm_put(dev_priv);
}
/**
- * intel_csr_ucode_resume() - init CSR firmware during system resume
+ * intel_dmc_ucode_resume() - init DMC firmware during system resume
* @dev_priv: i915 drm device
*
* Reinitialize the DMC firmware during system resume, reacquiring any
- * resources released in intel_csr_ucode_suspend().
+ * resources released in intel_dmc_ucode_suspend().
*/
-void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
+void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
{
if (!HAS_DMC(dev_priv))
return;
@@ -802,22 +802,22 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
* loaded.
*/
if (!dev_priv->dmc.dmc_payload)
- intel_csr_runtime_pm_get(dev_priv);
+ intel_dmc_runtime_pm_get(dev_priv);
}
/**
- * intel_csr_ucode_fini() - unload the CSR firmware.
+ * intel_dmc_ucode_fini() - unload the DMC firmware.
* @dev_priv: i915 drm device.
*
* Firmmware unloading includes freeing the internal memory and reset the
* firmware loading status.
*/
-void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
+void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
{
if (!HAS_DMC(dev_priv))
return;
- intel_csr_ucode_suspend(dev_priv);
+ intel_dmc_ucode_suspend(dev_priv);
drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
kfree(dev_priv->dmc.dmc_payload);
diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
index 984e9fb250f8..fc4960b91686 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.h
+++ b/drivers/gpu/drm/i915/display/intel_csr.h
@@ -12,10 +12,10 @@ struct drm_i915_private;
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
-void intel_csr_ucode_init(struct drm_i915_private *i915);
-void intel_csr_load_program(struct drm_i915_private *i915);
-void intel_csr_ucode_fini(struct drm_i915_private *i915);
-void intel_csr_ucode_suspend(struct drm_i915_private *i915);
-void intel_csr_ucode_resume(struct drm_i915_private *i915);
+void intel_dmc_ucode_init(struct drm_i915_private *i915);
+void intel_dmc_load_program(struct drm_i915_private *i915);
+void intel_dmc_ucode_fini(struct drm_i915_private *i915);
+void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
+void intel_dmc_ucode_resume(struct drm_i915_private *i915);
#endif /* __INTEL_CSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 422b59ebf6dc..39c9c49b378b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12192,7 +12192,7 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return 0;
- intel_csr_ucode_init(i915);
+ intel_dmc_ucode_init(i915);
i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
@@ -12204,15 +12204,15 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
ret = intel_cdclk_init(i915);
if (ret)
- goto cleanup_vga_client_pw_domain_csr;
+ goto cleanup_vga_client_pw_domain_dmc;
ret = intel_dbuf_init(i915);
if (ret)
- goto cleanup_vga_client_pw_domain_csr;
+ goto cleanup_vga_client_pw_domain_dmc;
ret = intel_bw_init(i915);
if (ret)
- goto cleanup_vga_client_pw_domain_csr;
+ goto cleanup_vga_client_pw_domain_dmc;
init_llist_head(&i915->atomic_helper.free_list);
INIT_WORK(&i915->atomic_helper.free_work,
@@ -12224,8 +12224,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
return 0;
-cleanup_vga_client_pw_domain_csr:
- intel_csr_ucode_fini(i915);
+cleanup_vga_client_pw_domain_dmc:
+ intel_dmc_ucode_fini(i915);
intel_power_domains_driver_remove(i915);
intel_vga_unregister(i915);
cleanup_bios:
@@ -13304,7 +13304,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
/* part #3: call after gem init */
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
{
- intel_csr_ucode_fini(i915);
+ intel_dmc_ucode_fini(i915);
intel_power_domains_driver_remove(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index de58abdd838b..cbba41d3e6cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -958,7 +958,7 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
intel_pps_unlock_regs_wa(dev_priv);
}
-static void assert_csr_loaded(struct drm_i915_private *dev_priv)
+static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
!intel_de_read(dev_priv, DMC_PROGRAM(0)),
@@ -1057,7 +1057,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
"DC5 already programmed to be enabled.\n");
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
- assert_csr_loaded(dev_priv);
+ assert_dmc_loaded(dev_priv);
}
static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
@@ -1084,7 +1084,7 @@ static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
DC_STATE_EN_UPTO_DC6),
"DC6 already programmed to be enabled.\n");
- assert_csr_loaded(dev_priv);
+ assert_dmc_loaded(dev_priv);
}
static void skl_enable_dc6(struct drm_i915_private *dev_priv)
@@ -5574,7 +5574,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
if (resume && dev_priv->dmc.dmc_payload)
- intel_csr_load_program(dev_priv);
+ intel_dmc_load_program(dev_priv);
}
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -5641,7 +5641,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
if (resume && dev_priv->dmc.dmc_payload)
- intel_csr_load_program(dev_priv);
+ intel_dmc_load_program(dev_priv);
}
static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -5707,7 +5707,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
if (resume && dev_priv->dmc.dmc_payload)
- intel_csr_load_program(dev_priv);
+ intel_dmc_load_program(dev_priv);
}
static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -5864,7 +5864,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
tgl_bw_buddy_init(dev_priv);
if (resume && dev_priv->dmc.dmc_payload)
- intel_csr_load_program(dev_priv);
+ intel_dmc_load_program(dev_priv);
/* Wa_14011508470 */
if (DISPLAY_VER(dev_priv) == 12) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5118dc8386b2..f2a9583dfecc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1043,7 +1043,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_suspend_encoders(i915);
intel_shutdown_encoders(i915);
- intel_csr_ucode_suspend(i915);
+ intel_dmc_ucode_suspend(i915);
/*
* The only requirement is to reboot with display DC states disabled,
@@ -1124,7 +1124,7 @@ static int i915_drm_suspend(struct drm_device *dev)
dev_priv->suspend_count++;
- intel_csr_ucode_suspend(dev_priv);
+ intel_dmc_ucode_suspend(dev_priv);
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
@@ -1226,7 +1226,7 @@ static int i915_drm_resume(struct drm_device *dev)
i915_ggtt_resume(&dev_priv->ggtt);
- intel_csr_ucode_resume(dev_priv);
+ intel_dmc_ucode_resume(dev_priv);
i915_restore_display(dev_priv);
intel_pps_unlock_regs_wa(dev_priv);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr"
2021-05-18 21:34 ` [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr" Anusha Srivatsa
@ 2021-05-19 5:46 ` Lucas De Marchi
0 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2021-05-19 5:46 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Tue, May 18, 2021 at 02:34:43PM -0700, Anusha Srivatsa wrote:
>No functional change.
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_csr.c | 64 +++++++++----------
> drivers/gpu/drm/i915/display/intel_csr.h | 10 +--
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++--
> .../drm/i915/display/intel_display_power.c | 14 ++--
> drivers/gpu/drm/i915/i915_drv.c | 6 +-
> 5 files changed, 54 insertions(+), 54 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
>index f2124796ce77..ae1dfafaff9a 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>+++ b/drivers/gpu/drm/i915/display/intel_csr.c
>@@ -302,14 +302,14 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> }
>
> /**
>- * intel_csr_load_program() - write the firmware from memory to register.
>+ * intel_dmc_load_program() - write the firmware from memory to register.
> * @dev_priv: i915 drm device.
> *
>- * CSR firmware is read from a .bin file and kept in internal memory one time.
>+ * DMC firmware is read from a .bin file and kept in internal memory one time.
> * Everytime display comes back from low power state this function is called to
> * copy the firmware from internal memory to registers.
> */
>-void intel_csr_load_program(struct drm_i915_private *dev_priv)
>+void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> {
> u32 *payload = dev_priv->dmc.dmc_payload;
> u32 i, fw_size;
>@@ -391,9 +391,9 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
> return dmc_offset;
> }
>
>-static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
>- const struct intel_dmc_header_base *dmc_header,
>- size_t rem_size)
>+static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
>+ const struct intel_dmc_header_base *dmc_header,
>+ size_t rem_size)
> {
> unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> const u32 *mmioaddr, *mmiodata;
>@@ -498,7 +498,7 @@ static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
> }
>
> static u32
>-parse_csr_fw_package(struct intel_dmc *dmc,
>+parse_dmc_fw_package(struct intel_dmc *dmc,
> const struct intel_package_header *package_header,
> const struct stepping_info *si,
> size_t rem_size)
>@@ -557,7 +557,7 @@ parse_csr_fw_package(struct intel_dmc *dmc,
> }
>
> /* Return number of bytes parsed or 0 on error */
>-static u32 parse_csr_fw_css(struct intel_dmc *dmc,
>+static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
> struct intel_css_header *css_header,
> size_t rem_size)
> {
>@@ -590,7 +590,7 @@ static u32 parse_csr_fw_css(struct intel_dmc *dmc,
> return sizeof(struct intel_css_header);
> }
>
>-static void parse_csr_fw(struct drm_i915_private *dev_priv,
>+static void parse_dmc_fw(struct drm_i915_private *dev_priv,
> const struct firmware *fw)
> {
> struct intel_css_header *css_header;
>@@ -606,7 +606,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract CSS Header information */
> css_header = (struct intel_css_header *)fw->data;
>- r = parse_csr_fw_css(dmc, css_header, fw->size);
>+ r = parse_dmc_fw_css(dmc, css_header, fw->size);
> if (!r)
> return;
>
>@@ -614,7 +614,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract Package Header information */
> package_header = (struct intel_package_header *)&fw->data[readcount];
>- r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount);
>+ r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount);
> if (!r)
> return;
>
>@@ -622,17 +622,17 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract dmc_header information */
> dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
>- parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount);
>+ parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
> }
>
>-static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
>+static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
> {
> drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
> dev_priv->dmc.wakeref =
> intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> }
>
>-static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
>+static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
> {
> intel_wakeref_t wakeref __maybe_unused =
> fetch_and_zero(&dev_priv->dmc.wakeref);
>@@ -640,7 +640,7 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
> intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
> }
>
>-static void csr_load_work_fn(struct work_struct *work)
>+static void dmc_load_work_fn(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv;
> struct intel_dmc *dmc;
>@@ -650,11 +650,11 @@ static void csr_load_work_fn(struct work_struct *work)
> dmc = &dev_priv->dmc;
>
> request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
>- parse_csr_fw(dev_priv, fw);
>+ parse_dmc_fw(dev_priv, fw);
>
> if (dev_priv->dmc.dmc_payload) {
>- intel_csr_load_program(dev_priv);
>- intel_csr_runtime_pm_put(dev_priv);
>+ intel_dmc_load_program(dev_priv);
>+ intel_dmc_runtime_pm_put(dev_priv);
>
> drm_info(&dev_priv->drm,
> "Finished loading DMC firmware %s (v%u.%u)\n",
>@@ -673,17 +673,17 @@ static void csr_load_work_fn(struct work_struct *work)
> }
>
> /**
>- * intel_csr_ucode_init() - initialize the firmware loading.
>+ * intel_dmc_ucode_init() - initialize the firmware loading.
> * @dev_priv: i915 drm device.
> *
> * This function is called at the time of loading the display driver to read
> * firmware from a .bin file and copied into a internal memory.
> */
>-void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>+void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
> {
> struct intel_dmc *dmc = &dev_priv->dmc;
>
>- INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
>+ INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
>
> if (!HAS_DMC(dev_priv))
> return;
>@@ -696,7 +696,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> * suspend as runtime suspend *requires* a working DMC for whatever
> * reason.
> */
>- intel_csr_runtime_pm_get(dev_priv);
>+ intel_dmc_runtime_pm_get(dev_priv);
>
> if (IS_ALDERLAKE_S(dev_priv)) {
> dmc->fw_path = ADLS_DMC_PATH;
>@@ -766,14 +766,14 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> }
>
> /**
>- * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
>+ * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend
> * @dev_priv: i915 drm device
> *
> * Prepare the DMC firmware before entering system suspend. This includes
> * flushing pending work items and releasing any resources acquired during
> * init.
> */
>-void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
>+void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
> {
> if (!HAS_DMC(dev_priv))
> return;
>@@ -782,17 +782,17 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
>
> /* Drop the reference held in case DMC isn't loaded. */
> if (!dev_priv->dmc.dmc_payload)
>- intel_csr_runtime_pm_put(dev_priv);
>+ intel_dmc_runtime_pm_put(dev_priv);
> }
>
> /**
>- * intel_csr_ucode_resume() - init CSR firmware during system resume
>+ * intel_dmc_ucode_resume() - init DMC firmware during system resume
> * @dev_priv: i915 drm device
> *
> * Reinitialize the DMC firmware during system resume, reacquiring any
>- * resources released in intel_csr_ucode_suspend().
>+ * resources released in intel_dmc_ucode_suspend().
> */
>-void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
>+void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
> {
> if (!HAS_DMC(dev_priv))
> return;
>@@ -802,22 +802,22 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
> * loaded.
> */
> if (!dev_priv->dmc.dmc_payload)
>- intel_csr_runtime_pm_get(dev_priv);
>+ intel_dmc_runtime_pm_get(dev_priv);
> }
>
> /**
>- * intel_csr_ucode_fini() - unload the CSR firmware.
>+ * intel_dmc_ucode_fini() - unload the DMC firmware.
> * @dev_priv: i915 drm device.
> *
> * Firmmware unloading includes freeing the internal memory and reset the
> * firmware loading status.
> */
>-void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
>+void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
> {
> if (!HAS_DMC(dev_priv))
> return;
>
>- intel_csr_ucode_suspend(dev_priv);
>+ intel_dmc_ucode_suspend(dev_priv);
> drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
>
> kfree(dev_priv->dmc.dmc_payload);
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
>index 984e9fb250f8..fc4960b91686 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.h
>+++ b/drivers/gpu/drm/i915/display/intel_csr.h
>@@ -12,10 +12,10 @@ struct drm_i915_private;
> #define DMC_VERSION_MAJOR(version) ((version) >> 16)
> #define DMC_VERSION_MINOR(version) ((version) & 0xffff)
>
>-void intel_csr_ucode_init(struct drm_i915_private *i915);
>-void intel_csr_load_program(struct drm_i915_private *i915);
>-void intel_csr_ucode_fini(struct drm_i915_private *i915);
>-void intel_csr_ucode_suspend(struct drm_i915_private *i915);
>-void intel_csr_ucode_resume(struct drm_i915_private *i915);
>+void intel_dmc_ucode_init(struct drm_i915_private *i915);
>+void intel_dmc_load_program(struct drm_i915_private *i915);
>+void intel_dmc_ucode_fini(struct drm_i915_private *i915);
>+void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
>+void intel_dmc_ucode_resume(struct drm_i915_private *i915);
>
> #endif /* __INTEL_CSR_H__ */
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 422b59ebf6dc..39c9c49b378b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -12192,7 +12192,7 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
> if (!HAS_DISPLAY(i915))
> return 0;
>
>- intel_csr_ucode_init(i915);
>+ intel_dmc_ucode_init(i915);
>
> i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
> i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
>@@ -12204,15 +12204,15 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>
> ret = intel_cdclk_init(i915);
> if (ret)
>- goto cleanup_vga_client_pw_domain_csr;
>+ goto cleanup_vga_client_pw_domain_dmc;
>
> ret = intel_dbuf_init(i915);
> if (ret)
>- goto cleanup_vga_client_pw_domain_csr;
>+ goto cleanup_vga_client_pw_domain_dmc;
>
> ret = intel_bw_init(i915);
> if (ret)
>- goto cleanup_vga_client_pw_domain_csr;
>+ goto cleanup_vga_client_pw_domain_dmc;
>
> init_llist_head(&i915->atomic_helper.free_list);
> INIT_WORK(&i915->atomic_helper.free_work,
>@@ -12224,8 +12224,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>
> return 0;
>
>-cleanup_vga_client_pw_domain_csr:
>- intel_csr_ucode_fini(i915);
>+cleanup_vga_client_pw_domain_dmc:
>+ intel_dmc_ucode_fini(i915);
> intel_power_domains_driver_remove(i915);
> intel_vga_unregister(i915);
> cleanup_bios:
>@@ -13304,7 +13304,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
> /* part #3: call after gem init */
> void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
> {
>- intel_csr_ucode_fini(i915);
>+ intel_dmc_ucode_fini(i915);
>
> intel_power_domains_driver_remove(i915);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index de58abdd838b..cbba41d3e6cf 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -958,7 +958,7 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> intel_pps_unlock_regs_wa(dev_priv);
> }
>
>-static void assert_csr_loaded(struct drm_i915_private *dev_priv)
>+static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
> {
> drm_WARN_ONCE(&dev_priv->drm,
> !intel_de_read(dev_priv, DMC_PROGRAM(0)),
>@@ -1057,7 +1057,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> "DC5 already programmed to be enabled.\n");
> assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
>- assert_csr_loaded(dev_priv);
>+ assert_dmc_loaded(dev_priv);
> }
>
> static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>@@ -1084,7 +1084,7 @@ static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> DC_STATE_EN_UPTO_DC6),
> "DC6 already programmed to be enabled.\n");
>
>- assert_csr_loaded(dev_priv);
>+ assert_dmc_loaded(dev_priv);
> }
>
> static void skl_enable_dc6(struct drm_i915_private *dev_priv)
>@@ -5574,7 +5574,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> gen9_dbuf_enable(dev_priv);
>
> if (resume && dev_priv->dmc.dmc_payload)
>- intel_csr_load_program(dev_priv);
>+ intel_dmc_load_program(dev_priv);
> }
>
> static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>@@ -5641,7 +5641,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
> gen9_dbuf_enable(dev_priv);
>
> if (resume && dev_priv->dmc.dmc_payload)
>- intel_csr_load_program(dev_priv);
>+ intel_dmc_load_program(dev_priv);
> }
>
> static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>@@ -5707,7 +5707,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> gen9_dbuf_enable(dev_priv);
>
> if (resume && dev_priv->dmc.dmc_payload)
>- intel_csr_load_program(dev_priv);
>+ intel_dmc_load_program(dev_priv);
> }
>
> static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
>@@ -5864,7 +5864,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> tgl_bw_buddy_init(dev_priv);
>
> if (resume && dev_priv->dmc.dmc_payload)
>- intel_csr_load_program(dev_priv);
>+ intel_dmc_load_program(dev_priv);
>
> /* Wa_14011508470 */
> if (DISPLAY_VER(dev_priv) == 12) {
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 5118dc8386b2..f2a9583dfecc 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -1043,7 +1043,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
> intel_suspend_encoders(i915);
> intel_shutdown_encoders(i915);
>
>- intel_csr_ucode_suspend(i915);
>+ intel_dmc_ucode_suspend(i915);
>
> /*
> * The only requirement is to reboot with display DC states disabled,
>@@ -1124,7 +1124,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> dev_priv->suspend_count++;
>
>- intel_csr_ucode_suspend(dev_priv);
>+ intel_dmc_ucode_suspend(dev_priv);
>
> enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>
>@@ -1226,7 +1226,7 @@ static int i915_drm_resume(struct drm_device *dev)
>
> i915_ggtt_resume(&dev_priv->ggtt);
>
>- intel_csr_ucode_resume(dev_priv);
>+ intel_dmc_ucode_resume(dev_priv);
>
> i915_restore_display(dev_priv);
> intel_pps_unlock_regs_wa(dev_priv);
>--
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
` (3 preceding siblings ...)
2021-05-18 21:34 ` [Intel-gfx] [CI 4/5] drm/i915/dmc: Rename functions names having "csr" Anusha Srivatsa
@ 2021-05-18 21:34 ` Anusha Srivatsa
2021-05-19 5:48 ` Lucas De Marchi
2021-05-18 21:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rename all CSR references to DMC (rev5) Patchwork
` (3 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Anusha Srivatsa @ 2021-05-18 21:34 UTC (permalink / raw)
To: intel-gfx
Finally, rename the header and source file from csr to dmc.
v2: Add file rename in Documentation.
- Place headers in orders. (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
Documentation/gpu/i915.rst | 12 ++++++------
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
.../drm/i915/display/{intel_csr.c => intel_dmc.c} | 4 ++--
.../drm/i915/display/{intel_csr.h => intel_dmc.h} | 6 +++---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
9 files changed, 17 insertions(+), 17 deletions(-)
rename drivers/gpu/drm/i915/display/{intel_csr.c => intel_dmc.c} (99%)
rename drivers/gpu/drm/i915/display/{intel_csr.h => intel_dmc.h} (88%)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 486c720f3890..42ce0196930a 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -210,13 +210,13 @@ DPIO
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
:doc: DPIO
-CSR firmware support for DMC
-----------------------------
+DMC Firmware Support
+--------------------
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
- :doc: csr support for dmc
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
+ :doc: DMC Firmware Support
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
:internal:
Video BIOS Table (VBT)
@@ -537,7 +537,7 @@ The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
DMC
---
-See `CSR firmware support for DMC`_
+See `DMC Firmware Support`_
Tracing
=======
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d0d936d9137b..2da5bae8fa03 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -201,10 +201,10 @@ i915-y += \
display/intel_combo_phy.o \
display/intel_connector.o \
display/intel_crtc.o \
- display/intel_csr.o \
display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
+ display/intel_dmc.o \
display/intel_dpio_phy.o \
display/intel_dpll.o \
display/intel_dpll_mgr.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 39c9c49b378b..d98a314bb974 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -79,9 +79,9 @@
#include "intel_cdclk.h"
#include "intel_color.h"
#include "intel_crtc.h"
-#include "intel_csr.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
#include "intel_dp_link_training.h"
#include "intel_fbc.h"
#include "intel_fdi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index e43abdf0e3d9..94e5cbd86e77 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -7,11 +7,11 @@
#include <drm/drm_fourcc.h>
#include "i915_debugfs.h"
-#include "intel_csr.h"
#include "intel_display_debugfs.h"
#include "intel_display_power.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
#include "intel_dp.h"
#include "intel_fbc.h"
#include "intel_hdcp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cbba41d3e6cf..e8fcc3d02d01 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -9,10 +9,10 @@
#include "i915_irq.h"
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
-#include "intel_csr.h"
#include "intel_display_power.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
#include "intel_pm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_dmc.c
similarity index 99%
rename from drivers/gpu/drm/i915/display/intel_csr.c
rename to drivers/gpu/drm/i915/display/intel_dmc.c
index ae1dfafaff9a..560574dd929a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -26,11 +26,11 @@
#include "i915_drv.h"
#include "i915_reg.h"
-#include "intel_csr.h"
#include "intel_de.h"
+#include "intel_dmc.h"
/**
- * DOC: DMC firmware support
+ * DOC: DMC Firmware Support
*
* From gen9 onwards we have newly added DMC (Display microcontroller) in display
* engine to save and restore the state of display engine when it enter into
diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_dmc.h
similarity index 88%
rename from drivers/gpu/drm/i915/display/intel_csr.h
rename to drivers/gpu/drm/i915/display/intel_dmc.h
index fc4960b91686..57dd99da0ced 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -3,8 +3,8 @@
* Copyright © 2019 Intel Corporation
*/
-#ifndef __INTEL_CSR_H__
-#define __INTEL_CSR_H__
+#ifndef __INTEL_DMC_H__
+#define __INTEL_DMC_H__
struct drm_i915_private;
@@ -18,4 +18,4 @@ void intel_dmc_ucode_fini(struct drm_i915_private *i915);
void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
-#endif /* __INTEL_CSR_H__ */
+#endif /* __INTEL_DMC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2a9583dfecc..2f06bb7b3ed2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,7 +49,7 @@
#include "display/intel_acpi.h"
#include "display/intel_bw.h"
#include "display/intel_cdclk.h"
-#include "display/intel_csr.h"
+#include "display/intel_dmc.h"
#include "display/intel_display_types.h"
#include "display/intel_dp.h"
#include "display/intel_fbdev.h"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index edd108d41318..8b964e355cb5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -36,7 +36,7 @@
#include <drm/drm_print.h>
-#include "display/intel_csr.h"
+#include "display/intel_dmc.h"
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h
2021-05-18 21:34 ` [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h Anusha Srivatsa
@ 2021-05-19 5:48 ` Lucas De Marchi
0 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2021-05-19 5:48 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
On Tue, May 18, 2021 at 02:34:44PM -0700, Anusha Srivatsa wrote:
>Finally, rename the header and source file from csr to dmc.
>
>v2: Add file rename in Documentation.
>- Place headers in orders. (Jani)
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> Documentation/gpu/i915.rst | 12 ++++++------
> drivers/gpu/drm/i915/Makefile | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> .../drm/i915/display/{intel_csr.c => intel_dmc.c} | 4 ++--
> .../drm/i915/display/{intel_csr.h => intel_dmc.h} | 6 +++---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> 9 files changed, 17 insertions(+), 17 deletions(-)
> rename drivers/gpu/drm/i915/display/{intel_csr.c => intel_dmc.c} (99%)
> rename drivers/gpu/drm/i915/display/{intel_csr.h => intel_dmc.h} (88%)
>
>diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>index 486c720f3890..42ce0196930a 100644
>--- a/Documentation/gpu/i915.rst
>+++ b/Documentation/gpu/i915.rst
>@@ -210,13 +210,13 @@ DPIO
> .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
> :doc: DPIO
>
>-CSR firmware support for DMC
>-----------------------------
>+DMC Firmware Support
>+--------------------
>
>-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
>- :doc: csr support for dmc
>+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
>+ :doc: DMC Firmware Support
>
>-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
>+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
> :internal:
>
> Video BIOS Table (VBT)
>@@ -537,7 +537,7 @@ The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
>
> DMC
> ---
>-See `CSR firmware support for DMC`_
>+See `DMC Firmware Support`_
>
> Tracing
> =======
>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index d0d936d9137b..2da5bae8fa03 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -201,10 +201,10 @@ i915-y += \
> display/intel_combo_phy.o \
> display/intel_connector.o \
> display/intel_crtc.o \
>- display/intel_csr.o \
> display/intel_cursor.o \
> display/intel_display.o \
> display/intel_display_power.o \
>+ display/intel_dmc.o \
> display/intel_dpio_phy.o \
> display/intel_dpll.o \
> display/intel_dpll_mgr.o \
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 39c9c49b378b..d98a314bb974 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -79,9 +79,9 @@
> #include "intel_cdclk.h"
> #include "intel_color.h"
> #include "intel_crtc.h"
>-#include "intel_csr.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
>+#include "intel_dmc.h"
> #include "intel_dp_link_training.h"
> #include "intel_fbc.h"
> #include "intel_fdi.h"
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index e43abdf0e3d9..94e5cbd86e77 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -7,11 +7,11 @@
> #include <drm/drm_fourcc.h>
>
> #include "i915_debugfs.h"
>-#include "intel_csr.h"
> #include "intel_display_debugfs.h"
> #include "intel_display_power.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
>+#include "intel_dmc.h"
> #include "intel_dp.h"
> #include "intel_fbc.h"
> #include "intel_hdcp.h"
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index cbba41d3e6cf..e8fcc3d02d01 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -9,10 +9,10 @@
> #include "i915_irq.h"
> #include "intel_cdclk.h"
> #include "intel_combo_phy.h"
>-#include "intel_csr.h"
> #include "intel_display_power.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
>+#include "intel_dmc.h"
> #include "intel_dpio_phy.h"
> #include "intel_hotplug.h"
> #include "intel_pm.h"
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>similarity index 99%
>rename from drivers/gpu/drm/i915/display/intel_csr.c
>rename to drivers/gpu/drm/i915/display/intel_dmc.c
>index ae1dfafaff9a..560574dd929a 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -26,11 +26,11 @@
>
> #include "i915_drv.h"
> #include "i915_reg.h"
>-#include "intel_csr.h"
> #include "intel_de.h"
>+#include "intel_dmc.h"
>
> /**
>- * DOC: DMC firmware support
>+ * DOC: DMC Firmware Support
> *
> * From gen9 onwards we have newly added DMC (Display microcontroller) in display
> * engine to save and restore the state of display engine when it enter into
>diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>similarity index 88%
>rename from drivers/gpu/drm/i915/display/intel_csr.h
>rename to drivers/gpu/drm/i915/display/intel_dmc.h
>index fc4960b91686..57dd99da0ced 100644
>--- a/drivers/gpu/drm/i915/display/intel_csr.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -3,8 +3,8 @@
> * Copyright © 2019 Intel Corporation
> */
>
>-#ifndef __INTEL_CSR_H__
>-#define __INTEL_CSR_H__
>+#ifndef __INTEL_DMC_H__
>+#define __INTEL_DMC_H__
>
> struct drm_i915_private;
>
>@@ -18,4 +18,4 @@ void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
>
>-#endif /* __INTEL_CSR_H__ */
>+#endif /* __INTEL_DMC_H__ */
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index f2a9583dfecc..2f06bb7b3ed2 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -49,7 +49,7 @@
> #include "display/intel_acpi.h"
> #include "display/intel_bw.h"
> #include "display/intel_cdclk.h"
>-#include "display/intel_csr.h"
>+#include "display/intel_dmc.h"
> #include "display/intel_display_types.h"
this is not sorted alphabetically. Other than that:
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> #include "display/intel_dp.h"
> #include "display/intel_fbdev.h"
>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>index edd108d41318..8b964e355cb5 100644
>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>@@ -36,7 +36,7 @@
>
> #include <drm/drm_print.h>
>
>-#include "display/intel_csr.h"
>+#include "display/intel_dmc.h"
> #include "display/intel_overlay.h"
>
> #include "gem/i915_gem_context.h"
>--
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rename all CSR references to DMC (rev5)
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
` (4 preceding siblings ...)
2021-05-18 21:34 ` [Intel-gfx] [CI 5/5] drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h Anusha Srivatsa
@ 2021-05-18 21:45 ` Patchwork
2021-05-18 21:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-05-18 21:45 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c95595fe6606 drm/i915/dmc: s/intel_csr/intel_dmc
dcf0abc59e2e drm/i915/dmc: s/HAS_CSR/HAS_DMC
533a65622dfe drm/i915/dmc: Rename macro names containing csr
cf0a044aa3a8 drm/i915/dmc: Rename functions names having "csr"
7ffe49e365bd drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h
-:113: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#113:
rename from drivers/gpu/drm/i915/display/intel_csr.c
total: 0 errors, 1 warnings, 0 checks, 114 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Rename all CSR references to DMC (rev5)
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
` (5 preceding siblings ...)
2021-05-18 21:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Rename all CSR references to DMC (rev5) Patchwork
@ 2021-05-18 21:47 ` Patchwork
2021-05-18 22:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-20 0:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-05-18 21:47 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Rename all CSR references to DMC (rev5)
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
` (6 preceding siblings ...)
2021-05-18 21:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-05-18 22:16 ` Patchwork
2021-05-20 0:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-05-18 22:16 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 13381 bytes --]
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20149
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_20149 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20149, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20149:
### IGT changes ###
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][1] ([i915#2782] / [i915#2940]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
Known issues
------------
Here are the changes found in Patchwork_20149 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-elk-e7500: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@amdgpu/amd_basic@cs-compute.html
* igt@gem_busy@busy@all:
- fi-bsw-nick: [PASS][4] -> [FAIL][5] ([i915#3457]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_busy@busy@all.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-nick/igt@gem_busy@busy@all.html
* igt@gem_exec_fence@basic-await@bcs0:
- fi-bsw-n3050: [PASS][6] -> [FAIL][7] ([i915#3457]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
* igt@gem_wait@busy@all:
- fi-bsw-nick: [PASS][8] -> [FAIL][9] ([i915#3177] / [i915#3457])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_wait@busy@all.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-nick/igt@gem_wait@busy@all.html
* igt@i915_selftest@live@mman:
- fi-elk-e7500: NOTRUN -> [DMESG-FAIL][10] ([i915#3457])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@i915_selftest@live@mman.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-pnv-d510: [PASS][11] -> [FAIL][12] ([i915#53]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-pnv-d510/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-pnv-d510/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-elk-e7500: [PASS][13] -> [FAIL][14] ([i915#53])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bsw-kefka: [PASS][15] -> [FAIL][16] ([i915#53])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Possible fixes ####
* igt@gem_exec_fence@basic-await@rcs0:
- fi-elk-e7500: [FAIL][17] ([i915#3457]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@gem_exec_fence@basic-await@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@gem_exec_fence@basic-await@rcs0.html
* igt@gem_exec_fence@nb-await@vcs0:
- fi-bsw-kefka: [FAIL][19] ([i915#3457]) -> [PASS][20] +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html
- fi-bsw-n3050: [FAIL][21] ([i915#3457]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vcs0.html
* igt@gem_wait@wait@all:
- fi-bsw-nick: [FAIL][23] ([i915#3457]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_wait@wait@all.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-nick/igt@gem_wait@wait@all.html
* igt@i915_selftest@live@hangcheck:
- {fi-tgl-dsi}: [DMESG-FAIL][25] ([i915#2927]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-tgl-dsi/igt@i915_selftest@live@hangcheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-tgl-dsi/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@sanitycheck:
- fi-elk-e7500: [SKIP][27] ([fdo#109271]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@i915_selftest@live@sanitycheck.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@i915_selftest@live@sanitycheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- fi-ilk-650: [FAIL][29] ([i915#53]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-elk-e7500: [FAIL][31] ([i915#53]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-bsw-kefka: [FAIL][33] ([i915#53]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
#### Warnings ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][35] ([i915#3472]) -> [FAIL][36] ([i915#3457] / [i915#3472])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
- fi-ilk-650: [FAIL][37] ([i915#3472]) -> [FAIL][38] ([i915#3457] / [i915#3472])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-ilk-650/igt@gem_exec_gttfill@basic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-ilk-650/igt@gem_exec_gttfill@basic.html
* igt@i915_module_load@reload:
- fi-elk-e7500: [DMESG-FAIL][39] ([i915#3457]) -> [DMESG-WARN][40] ([i915#3457])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@i915_module_load@reload.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-elk-e7500/igt@i915_module_load@reload.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [DMESG-FAIL][41] -> [INCOMPLETE][42] ([i915#2782] / [i915#2940])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-bsw-nick/igt@i915_selftest@live@execlists.html
- fi-icl-u2: [DMESG-FAIL][43] ([i915#3462]) -> [INCOMPLETE][44] ([i915#2782] / [i915#3462])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@i915_selftest@live@execlists.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-icl-u2/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][45] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][46] ([i915#2782] / [i915#3363])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@runner@aborted.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-icl-u2/igt@runner@aborted.html
- fi-glk-dsi: [FAIL][47] ([i915#3363] / [k.org#202321]) -> [FAIL][48] ([i915#2426] / [i915#3363] / [k.org#202321])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-glk-dsi/igt@runner@aborted.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-glk-dsi/igt@runner@aborted.html
- fi-kbl-soraka: [FAIL][49] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][50] ([i915#1436] / [i915#3363])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-soraka/igt@runner@aborted.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-kbl-soraka/igt@runner@aborted.html
- fi-kbl-guc: [FAIL][51] ([i915#1436] / [i915#3363]) -> [FAIL][52] ([i915#1436] / [i915#2426] / [i915#3363])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-guc/igt@runner@aborted.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-kbl-guc/igt@runner@aborted.html
- fi-cml-u2: [FAIL][53] ([i915#2082] / [i915#2426] / [i915#3363]) -> [FAIL][54] ([i915#3363])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-cml-u2/igt@runner@aborted.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/fi-cml-u2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
[i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3468]: https://gitlab.freedesktop.org/drm/intel/issues/3468
[i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (43 -> 39)
------------------------------
Additional (1): fi-rkl-11500t
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10100 -> Patchwork_20149
CI-20190529: 20190529
CI_DRM_10100: cde0422496c99357e2fe968c091bf88ae0e96cd3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6087: a1772be7dede83a4f65e5986fd7083a9c8f89083 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20149: 7ffe49e365bd6883fa0e7c1b2419e034f0075f43 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7ffe49e365bd drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h
cf0a044aa3a8 drm/i915/dmc: Rename functions names having "csr"
533a65622dfe drm/i915/dmc: Rename macro names containing csr
dcf0abc59e2e drm/i915/dmc: s/HAS_CSR/HAS_DMC
c95595fe6606 drm/i915/dmc: s/intel_csr/intel_dmc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Rename all CSR references to DMC (rev5)
2021-05-18 21:34 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
` (7 preceding siblings ...)
2021-05-18 22:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-05-20 0:40 ` Patchwork
8 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-05-20 0:40 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30262 bytes --]
== Series Details ==
Series: Rename all CSR references to DMC (rev5)
URL : https://patchwork.freedesktop.org/series/90043/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10100_full -> Patchwork_20149_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20149_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20149_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20149_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-snb: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@plane-position-covered@pipe-a-planes}:
- shard-glk: [FAIL][2] ([i915#3457]) -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk4/igt@kms_plane@plane-position-covered@pipe-a-planes.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk4/igt@kms_plane@plane-position-covered@pipe-a-planes.html
* {igt@kms_plane@plane-position-hole@pipe-a-planes}:
- shard-glk: [PASS][4] -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk4/igt@kms_plane@plane-position-hole@pipe-a-planes.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk1/igt@kms_plane@plane-position-hole@pipe-a-planes.html
### Piglit changes ###
#### Possible regressions ####
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-inversesqrt-vec4 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][6] +7 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-inversesqrt-vec4.html
New tests
---------
New tests have been introduced between CI_DRM_10100_full and Patchwork_20149_full:
### New Piglit tests (8) ###
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-inverse-mat2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-inversesqrt-vec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-lshift-ivec3-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitor-not-uvec4-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-mult-vec3-mat4x3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-rshift-uvec3-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-step-vec4-vec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@built-in-functions@tcs-tan-vec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_20149_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-snb: NOTRUN -> [DMESG-WARN][7] ([i915#3457])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb5/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@gem_ctx_engines@invalid-engines:
- shard-snb: NOTRUN -> [INCOMPLETE][8] ([i915#3457] / [i915#3468])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb2/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_freq@sysfs:
- shard-apl: NOTRUN -> [FAIL][9] ([i915#3457]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@gem_ctx_freq@sysfs.html
* igt@gem_ctx_persistence@engines-persistence@rcs0:
- shard-apl: [PASS][10] -> [FAIL][11] ([i915#3457]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-apl7/igt@gem_ctx_persistence@engines-persistence@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@gem_ctx_persistence@engines-persistence@rcs0.html
* igt@gem_ctx_persistence@legacy-engines-persistence:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb5/igt@gem_ctx_persistence@legacy-engines-persistence.html
* igt@gem_ctx_shared@q-in-order:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271]) +150 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb2/igt@gem_ctx_shared@q-in-order.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][14] ([i915#3354] / [i915#3457])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][15] ([i915#2846] / [i915#3457])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842] / [i915#3457])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842] / [i915#3457]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-tglb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2842] / [i915#3457]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][21] -> [FAIL][22] ([i915#2842] / [i915#3457])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fence@keep-in-fence@vcs0:
- shard-glk: NOTRUN -> [INCOMPLETE][23] ([i915#3457])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk8/igt@gem_exec_fence@keep-in-fence@vcs0.html
* igt@gem_exec_gttfill@all:
- shard-apl: NOTRUN -> [FAIL][24] ([i915#3457] / [i915#3491])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@gem_exec_gttfill@all.html
* igt@gem_exec_gttfill@basic:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#3457] / [i915#3491])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk1/igt@gem_exec_gttfill@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk4/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_schedule@preempt-hang@vcs0:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#3457]) +21 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk8/igt@gem_exec_schedule@preempt-hang@vcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk1/igt@gem_exec_schedule@preempt-hang@vcs0.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-glk: [PASS][29] -> [DMESG-WARN][30] ([i915#118] / [i915#95])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk8/igt@gem_exec_whisper@basic-queues-priority.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk1/igt@gem_exec_whisper@basic-queues-priority.html
* igt@gem_mmap_gtt@big-copy:
- shard-glk: [PASS][31] -> [FAIL][32] ([i915#307])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk5/igt@gem_mmap_gtt@big-copy.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk7/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-kbl: NOTRUN -> [INCOMPLETE][33] ([i915#3468])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-skl: NOTRUN -> [INCOMPLETE][34] ([i915#3468])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-ccs-to-linear:
- shard-apl: NOTRUN -> [INCOMPLETE][35] ([i915#3468]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@gem_render_copy@yf-tiled-ccs-to-linear.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][36] ([i915#768]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_spin_batch@spin-each:
- shard-apl: NOTRUN -> [FAIL][37] ([i915#2898] / [i915#3457])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@gem_spin_batch@spin-each.html
* igt@gen3_mixed_blits:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109289])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@gen3_mixed_blits.html
* igt@gen9_exec_parse@bb-large:
- shard-kbl: NOTRUN -> [FAIL][39] ([i915#3296])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl2/igt@gen9_exec_parse@bb-large.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][40] ([i915#454])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#1937])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#1937])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@cursor:
- shard-kbl: [PASS][43] -> [DMESG-WARN][44] ([i915#3457])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl2/igt@i915_pm_rpm@cursor.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl6/igt@i915_pm_rpm@cursor.html
- shard-glk: [PASS][45] -> [DMESG-WARN][46] ([i915#3457])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk8/igt@i915_pm_rpm@cursor.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk1/igt@i915_pm_rpm@cursor.html
* igt@i915_pm_rpm@gem-mmap-type@uc:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#3475])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl7/igt@i915_pm_rpm@gem-mmap-type@uc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl3/igt@i915_pm_rpm@gem-mmap-type@uc.html
- shard-iclb: [PASS][49] -> [DMESG-WARN][50] ([i915#3475])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb8/igt@i915_pm_rpm@gem-mmap-type@uc.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@i915_pm_rpm@gem-mmap-type@uc.html
* igt@i915_pm_rpm@gem-mmap-type@wc:
- shard-iclb: [PASS][51] -> [DMESG-WARN][52] ([i915#3457])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb8/igt@i915_pm_rpm@gem-mmap-type@wc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@i915_pm_rpm@gem-mmap-type@wc.html
- shard-skl: NOTRUN -> [DMESG-WARN][53] ([i915#3457]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@i915_pm_rpm@gem-mmap-type@wc.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271]) +145 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#110725] / [fdo#111614])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#110723])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111304]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_ccs@pipe-c-ccs-on-another-bo.html
* igt@kms_color@pipe-c-degamma:
- shard-iclb: NOTRUN -> [FAIL][58] ([i915#1149])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_color@pipe-c-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +15 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][62] ([fdo#109271] / [fdo#111827]) +11 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb5/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [fdo#111827]) +9 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> [TIMEOUT][64] ([i915#1319])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-random:
- shard-snb: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#3457]) +23 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#3457]) +27 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-iclb: [PASS][67] -> [FAIL][68] ([i915#3457])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
- shard-kbl: [PASS][69] -> [FAIL][70] ([i915#3444] / [i915#3457])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
- shard-tglb: [PASS][71] -> [FAIL][72] ([i915#2124] / [i915#3457]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-dpms:
- shard-skl: NOTRUN -> [FAIL][73] ([i915#3444] / [i915#3457]) +7 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
- shard-iclb: NOTRUN -> [FAIL][74] ([i915#3457]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3457]) +18 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
- shard-apl: NOTRUN -> [FAIL][76] ([i915#3444] / [i915#3457]) +4 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
- shard-snb: NOTRUN -> [FAIL][77] ([i915#3457]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb2/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
- shard-kbl: NOTRUN -> [FAIL][78] ([i915#3444] / [i915#3457]) +5 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
- shard-apl: [PASS][79] -> [FAIL][80] ([i915#3444] / [i915#3457])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3457]) +8 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen:
- shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109278] / [i915#3457]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge:
- shard-glk: [PASS][83] -> [FAIL][84] ([i915#70])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk1/igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-top-edge.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][85] -> [FAIL][86] ([i915#72])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109274] / [fdo#109278]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271]) +87 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: NOTRUN -> [INCOMPLETE][89] ([i915#155] / [i915#180] / [i915#636])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109274]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: NOTRUN -> [FAIL][91] ([i915#79]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2672])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109280]) +7 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271]) +48 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][95] -> [DMESG-WARN][96] ([i915#180]) +3 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#533]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#533])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-a:
- shard-glk: [PASS][99] -> [FAIL][100] ([i915#2472])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-a.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-a.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- shard-skl: NOTRUN -> [DMESG-WARN][101] ([i915#1982])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][102] ([fdo#108145] / [i915#265]) +4 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-skl: NOTRUN -> [FAIL][103] ([fdo#108145] / [i915#265]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][104] ([i915#265])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
- shard-apl: NOTRUN -> [FAIL][105] ([i915#265])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-7efc:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109278]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_plane_alpha_blend@pipe-d-alpha-7efc.html
* igt@kms_plane_cursor@pipe-a-primary-size-256:
- shard-iclb: NOTRUN -> [FAIL][108] ([i915#2657])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_plane_cursor@pipe-a-primary-size-256.html
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-snb: NOTRUN -> [FAIL][109] ([i915#2657])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-snb5/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
* igt@kms_plane_cursor@pipe-b-viewport-size-256:
- shard-kbl: NOTRUN -> [FAIL][110] ([i915#2657])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_plane_cursor@pipe-b-viewport-size-256.html
* igt@kms_plane_cursor@pipe-c-primary-size-64:
- shard-iclb: NOTRUN -> [FAIL][111] ([i915#2657] / [i915#3457])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_plane_cursor@pipe-c-primary-size-64.html
* igt@kms_plane_cursor@pipe-c-viewport-size-128:
- shard-skl: NOTRUN -> [FAIL][112] ([i915#2657] / [i915#3457]) +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_plane_cursor@pipe-c-viewport-size-128.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-glk: [PASS][113] -> [FAIL][114] ([i915#1779])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk5/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-glk8/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#658]) +4 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#658])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#658]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109502])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2437])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@kms_writeback@writeback-fb-id.html
- shard-kbl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#2437])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-kbl4/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling-small-buf:
- shard-skl: NOTRUN -> [FAIL][121] ([i915#1722])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@perf@polling-small-buf.html
* igt@perf_pmu@render-node-busy-idle@rcs0:
- shard-apl: NOTRUN -> [WARN][122] ([i915#3457]) +3 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-apl6/igt@perf_pmu@render-node-busy-idle@rcs0.html
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][123] ([fdo#109291])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-iclb6/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html
* igt@prime_vgem@sync@rcs0:
- shard-tglb: [PASS][124] -> [INCOMPLETE][125] ([i915#409])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb6/igt@prime_vgem@sync@rcs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-tglb1/igt@prime_vgem@sync@rcs0.html
* igt@runner@aborted:
- shard-skl: NOTRUN -> ([FAIL][126], [FAIL][127]) ([i915#2029] / [i915#2722] / [i915#3363])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/shard-skl3/igt@runner@aborted.html
[127]: https://int
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20149/index.html
[-- Attachment #1.2: Type: text/html, Size: 33851 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [CI 1/5] drm/i915/dmc: s/intel_csr/intel_dmc
2021-05-18 19:53 [Intel-gfx] [CI 0/5] Rename all CSR references to DMC Anusha Srivatsa
@ 2021-05-18 19:53 ` Anusha Srivatsa
0 siblings, 0 replies; 18+ messages in thread
From: Anusha Srivatsa @ 2021-05-18 19:53 UTC (permalink / raw)
To: intel-gfx
No functional change.
v2: Chchpatch fixes.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 170 +++++++++---------
.../drm/i915/display/intel_display_debugfs.c | 14 +-
.../drm/i915/display/intel_display_power.c | 52 +++---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 8 +-
6 files changed, 125 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 26a922d34263..a22339ebdffd 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -312,7 +312,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
*/
void intel_csr_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->csr.dmc_payload;
+ u32 *payload = dev_priv->dmc.dmc_payload;
u32 i, fw_size;
if (!HAS_CSR(dev_priv)) {
@@ -321,13 +321,13 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!dev_priv->csr.dmc_payload) {
+ if (!dev_priv->dmc.dmc_payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->csr.dmc_fw_size;
+ fw_size = dev_priv->dmc.dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
@@ -338,12 +338,12 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
preempt_enable();
- for (i = 0; i < dev_priv->csr.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
- dev_priv->csr.mmiodata[i]);
+ for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
+ intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
+ dev_priv->dmc.mmiodata[i]);
}
- dev_priv->csr.dc_state = 0;
+ dev_priv->dmc.dc_state = 0;
gen9_set_dc_state_debugmask(dev_priv);
}
@@ -392,7 +392,7 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
return dmc_offset;
}
-static u32 parse_csr_fw_dmc(struct intel_csr *csr,
+static u32 parse_csr_fw_dmc(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
@@ -401,8 +401,8 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
- ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -464,10 +464,10 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
mmioaddr[i]);
return 0;
}
- csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
- csr->mmiodata[i] = mmiodata[i];
+ dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc->mmiodata[i] = mmiodata[i];
}
- csr->mmio_count = mmio_count;
+ dmc->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -476,20 +476,20 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
if (rem_size < payload_size)
goto error_truncated;
- if (payload_size > csr->max_fw_size) {
+ if (payload_size > dmc->max_fw_size) {
DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
- csr->dmc_fw_size = dmc_header->fw_size;
+ dmc->dmc_fw_size = dmc_header->fw_size;
- csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!csr->dmc_payload) {
+ dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc->dmc_payload) {
DRM_ERROR("Memory allocation failed for dmc payload\n");
return 0;
}
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(csr->dmc_payload, payload, payload_size);
+ memcpy(dmc->dmc_payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -499,7 +499,7 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
}
static u32
-parse_csr_fw_package(struct intel_csr *csr,
+parse_csr_fw_package(struct intel_dmc *dmc,
const struct intel_package_header *package_header,
const struct stepping_info *si,
size_t rem_size)
@@ -558,7 +558,7 @@ parse_csr_fw_package(struct intel_csr *csr,
}
/* Return number of bytes parsed or 0 on error */
-static u32 parse_csr_fw_css(struct intel_csr *csr,
+static u32 parse_csr_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
@@ -575,18 +575,18 @@ static u32 parse_csr_fw_css(struct intel_csr *csr,
return 0;
}
- if (csr->required_version &&
- css_header->version != csr->required_version) {
+ if (dmc->required_version &&
+ css_header->version != dmc->required_version) {
DRM_INFO("Refusing to load DMC firmware v%u.%u,"
" please use v%u.%u\n",
CSR_VERSION_MAJOR(css_header->version),
CSR_VERSION_MINOR(css_header->version),
- CSR_VERSION_MAJOR(csr->required_version),
- CSR_VERSION_MINOR(csr->required_version));
+ CSR_VERSION_MAJOR(dmc->required_version),
+ CSR_VERSION_MINOR(dmc->required_version));
return 0;
}
- csr->version = css_header->version;
+ dmc->version = css_header->version;
return sizeof(struct intel_css_header);
}
@@ -597,7 +597,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
- struct intel_csr *csr = &dev_priv->csr;
+ struct intel_dmc *dmc = &dev_priv->dmc;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
u32 readcount = 0;
u32 r;
@@ -607,7 +607,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract CSS Header information */
css_header = (struct intel_css_header *)fw->data;
- r = parse_csr_fw_css(csr, css_header, fw->size);
+ r = parse_csr_fw_css(dmc, css_header, fw->size);
if (!r)
return;
@@ -615,7 +615,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract Package Header information */
package_header = (struct intel_package_header *)&fw->data[readcount];
- r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
+ r = parse_csr_fw_package(dmc, package_header, si, fw->size - readcount);
if (!r)
return;
@@ -623,20 +623,20 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract dmc_header information */
dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
- parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
+ parse_csr_fw_dmc(dmc, dmc_header, fw->size - readcount);
}
static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
{
- drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
- dev_priv->csr.wakeref =
+ drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
+ dev_priv->dmc.wakeref =
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&dev_priv->csr.wakeref);
+ fetch_and_zero(&dev_priv->dmc.wakeref);
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
}
@@ -644,28 +644,28 @@ static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
static void csr_load_work_fn(struct work_struct *work)
{
struct drm_i915_private *dev_priv;
- struct intel_csr *csr;
+ struct intel_dmc *dmc;
const struct firmware *fw = NULL;
- dev_priv = container_of(work, typeof(*dev_priv), csr.work);
- csr = &dev_priv->csr;
+ dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
+ dmc = &dev_priv->dmc;
- request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
+ request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
parse_csr_fw(dev_priv, fw);
- if (dev_priv->csr.dmc_payload) {
+ if (dev_priv->dmc.dmc_payload) {
intel_csr_load_program(dev_priv);
intel_csr_runtime_pm_put(dev_priv);
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
- dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
- CSR_VERSION_MINOR(csr->version));
+ dev_priv->dmc.fw_path, CSR_VERSION_MAJOR(dmc->version),
+ CSR_VERSION_MINOR(dmc->version));
} else {
drm_notice(&dev_priv->drm,
"Failed to load DMC firmware %s."
" Disabling runtime power management.\n",
- csr->fw_path);
+ dmc->fw_path);
drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
INTEL_UC_FIRMWARE_URL);
}
@@ -682,9 +682,9 @@ static void csr_load_work_fn(struct work_struct *work)
*/
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
{
- struct intel_csr *csr = &dev_priv->csr;
+ struct intel_dmc *dmc = &dev_priv->dmc;
- INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
+ INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn);
if (!HAS_CSR(dev_priv))
return;
@@ -700,70 +700,70 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
intel_csr_runtime_pm_get(dev_priv);
if (IS_ALDERLAKE_S(dev_priv)) {
- csr->fw_path = ADLS_CSR_PATH;
- csr->required_version = ADLS_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = ADLS_CSR_PATH;
+ dmc->required_version = ADLS_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (IS_DG1(dev_priv)) {
- csr->fw_path = DG1_CSR_PATH;
- csr->required_version = DG1_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = DG1_CSR_PATH;
+ dmc->required_version = DG1_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (IS_ROCKETLAKE(dev_priv)) {
- csr->fw_path = RKL_CSR_PATH;
- csr->required_version = RKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = RKL_CSR_PATH;
+ dmc->required_version = RKL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- csr->fw_path = TGL_CSR_PATH;
- csr->required_version = TGL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ dmc->fw_path = TGL_CSR_PATH;
+ dmc->required_version = TGL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (DISPLAY_VER(dev_priv) == 11) {
- csr->fw_path = ICL_CSR_PATH;
- csr->required_version = ICL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = ICL_CSR_PATH;
+ dmc->required_version = ICL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = ICL_CSR_MAX_FW_SIZE;
} else if (IS_CANNONLAKE(dev_priv)) {
- csr->fw_path = CNL_CSR_PATH;
- csr->required_version = CNL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = CNL_CSR_PATH;
+ dmc->required_version = CNL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = CNL_CSR_MAX_FW_SIZE;
} else if (IS_GEMINILAKE(dev_priv)) {
- csr->fw_path = GLK_CSR_PATH;
- csr->required_version = GLK_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
+ dmc->fw_path = GLK_CSR_PATH;
+ dmc->required_version = GLK_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = GLK_CSR_MAX_FW_SIZE;
} else if (IS_KABYLAKE(dev_priv) ||
IS_COFFEELAKE(dev_priv) ||
IS_COMETLAKE(dev_priv)) {
- csr->fw_path = KBL_CSR_PATH;
- csr->required_version = KBL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = KBL_CSR_PATH;
+ dmc->required_version = KBL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = KBL_CSR_MAX_FW_SIZE;
} else if (IS_SKYLAKE(dev_priv)) {
- csr->fw_path = SKL_CSR_PATH;
- csr->required_version = SKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
+ dmc->fw_path = SKL_CSR_PATH;
+ dmc->required_version = SKL_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = SKL_CSR_MAX_FW_SIZE;
} else if (IS_BROXTON(dev_priv)) {
- csr->fw_path = BXT_CSR_PATH;
- csr->required_version = BXT_CSR_VERSION_REQUIRED;
- csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
+ dmc->fw_path = BXT_CSR_PATH;
+ dmc->required_version = BXT_CSR_VERSION_REQUIRED;
+ dmc->max_fw_size = BXT_CSR_MAX_FW_SIZE;
}
if (dev_priv->params.dmc_firmware_path) {
if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
- csr->fw_path = NULL;
+ dmc->fw_path = NULL;
drm_info(&dev_priv->drm,
- "Disabling CSR firmware and runtime PM\n");
+ "Disabling DMC firmware and runtime PM\n");
return;
}
- csr->fw_path = dev_priv->params.dmc_firmware_path;
+ dmc->fw_path = dev_priv->params.dmc_firmware_path;
/* Bypass version check for firmware override. */
- csr->required_version = 0;
+ dmc->required_version = 0;
}
- if (csr->fw_path == NULL) {
+ if (!dmc->fw_path) {
drm_dbg_kms(&dev_priv->drm,
- "No known CSR firmware for platform, disabling runtime PM\n");
+ "No known DMC firmware for platform, disabling runtime PM\n");
return;
}
- drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
- schedule_work(&dev_priv->csr.work);
+ drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
+ schedule_work(&dev_priv->dmc.work);
}
/**
@@ -779,10 +779,10 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
if (!HAS_CSR(dev_priv))
return;
- flush_work(&dev_priv->csr.work);
+ flush_work(&dev_priv->dmc.work);
/* Drop the reference held in case DMC isn't loaded. */
- if (!dev_priv->csr.dmc_payload)
+ if (!dev_priv->dmc.dmc_payload)
intel_csr_runtime_pm_put(dev_priv);
}
@@ -802,7 +802,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
* Reacquire the reference to keep RPM disabled in case DMC isn't
* loaded.
*/
- if (!dev_priv->csr.dmc_payload)
+ if (!dev_priv->dmc.dmc_payload)
intel_csr_runtime_pm_get(dev_priv);
}
@@ -819,7 +819,7 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
return;
intel_csr_ucode_suspend(dev_priv);
- drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- kfree(dev_priv->csr.dmc_payload);
+ kfree(dev_priv->dmc.dmc_payload);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d77a0ab5cacf..a875f3c9b358 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -532,24 +532,24 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
- struct intel_csr *csr;
+ struct intel_dmc *dmc;
i915_reg_t dc5_reg, dc6_reg = {};
if (!HAS_CSR(dev_priv))
return -ENODEV;
- csr = &dev_priv->csr;
+ dmc = &dev_priv->dmc;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
- seq_printf(m, "path: %s\n", csr->fw_path);
+ seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload));
+ seq_printf(m, "path: %s\n", dmc->fw_path);
- if (!csr->dmc_payload)
+ if (!dmc->dmc_payload)
goto out;
- seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
- CSR_VERSION_MINOR(csr->version));
+ seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(dmc->version),
+ CSR_VERSION_MINOR(dmc->version));
if (DISPLAY_VER(dev_priv) >= 12) {
if (IS_DGFX(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 54c6d65011ee..0a05d0f90f28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -829,8 +829,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"Resetting DC state tracking from %02x to %02x\n",
- dev_priv->csr.dc_state, val);
- dev_priv->csr.dc_state = val;
+ dev_priv->dmc.dc_state, val);
+ dev_priv->dmc.dc_state = val;
}
/**
@@ -865,8 +865,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm,
- state & ~dev_priv->csr.allowed_dc_mask))
- state &= dev_priv->csr.allowed_dc_mask;
+ state & ~dev_priv->dmc.allowed_dc_mask))
+ state &= dev_priv->dmc.allowed_dc_mask;
val = intel_de_read(dev_priv, DC_STATE_EN);
mask = gen9_dc_mask(dev_priv);
@@ -874,16 +874,16 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
val & mask, state);
/* Check if DMC is ignoring our DC state requests */
- if ((val & mask) != dev_priv->csr.dc_state)
+ if ((val & mask) != dev_priv->dmc.dc_state)
drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
- dev_priv->csr.dc_state, val & mask);
+ dev_priv->dmc.dc_state, val & mask);
val &= ~mask;
val |= state;
gen9_write_dc_state(dev_priv, val);
- dev_priv->csr.dc_state = val & mask;
+ dev_priv->dmc.dc_state = val & mask;
}
static u32
@@ -902,7 +902,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->csr.allowed_dc_mask & target_dc_state)
+ if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -1016,7 +1016,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->csr.target_dc_state)
+ if (state == dev_priv->dmc.target_dc_state)
goto unlock;
dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
@@ -1028,7 +1028,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (!dc_off_enabled)
power_well->desc->ops->enable(dev_priv, power_well);
- dev_priv->csr.target_dc_state = state;
+ dev_priv->dmc.target_dc_state = state;
if (!dc_off_enabled)
power_well->desc->ops->disable(dev_priv, power_well);
@@ -1181,7 +1181,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = {};
- if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
+ if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
return;
}
@@ -1220,10 +1220,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (!dev_priv->csr.dmc_payload)
+ if (!dev_priv->dmc.dmc_payload)
return;
- switch (dev_priv->csr.target_dc_state) {
+ switch (dev_priv->dmc.target_dc_state) {
case DC_STATE_EN_DC3CO:
tgl_enable_dc3co(dev_priv);
break;
@@ -5090,10 +5090,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->csr.allowed_dc_mask =
+ dev_priv->dmc.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->csr.target_dc_state =
+ dev_priv->dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
@@ -5573,7 +5573,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
}
@@ -5640,7 +5640,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
}
@@ -5706,7 +5706,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
}
@@ -5863,7 +5863,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && dev_priv->dmc.dmc_payload)
intel_csr_load_program(dev_priv);
/* Wa_14011508470 */
@@ -6222,9 +6222,9 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
- i915->csr.dmc_payload) {
+ i915->dmc.dmc_payload) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -6414,19 +6414,19 @@ void intel_display_power_resume(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
- if (i915->csr.dmc_payload) {
- if (i915->csr.allowed_dc_mask &
+ if (i915->dmc.dmc_payload) {
+ if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->csr.allowed_dc_mask &
+ else if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
- if (i915->csr.dmc_payload &&
- (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ if (i915->dmc.dmc_payload &&
+ (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index acaf3d459821..0905386b2270 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -669,7 +669,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (crtc_state->enable_psr2_sel_fetch)
return;
- if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9aee6a045590..3c9f6bbb5dd7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -328,7 +328,7 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_csr {
+struct intel_dmc {
struct work_struct work;
const char *fw_path;
u32 required_version;
@@ -824,7 +824,7 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- struct intel_csr csr;
+ struct intel_dmc dmc;
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 99ca242ec13b..03d1221de13b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -789,13 +789,13 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
if (HAS_CSR(m->i915)) {
- struct intel_csr *csr = &m->i915->csr;
+ struct intel_dmc *dmc = &m->i915->dmc;
err_printf(m, "DMC loaded: %s\n",
- yesno(csr->dmc_payload != NULL));
+ yesno(dmc->dmc_payload));
err_printf(m, "DMC fw version: %d.%d\n",
- CSR_VERSION_MAJOR(csr->version),
- CSR_VERSION_MINOR(csr->version));
+ CSR_VERSION_MAJOR(dmc->version),
+ CSR_VERSION_MINOR(dmc->version));
}
err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
--
2.25.0
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