[PATCH v6 0/4]Add Bitstream configuration support for Versal

[PATCH v6 0/4]Add Bitstream configuration support for Versal

[Nava kishore Manne]

This series Adds FPGA manager driver support for Xilinx Versal SoC.
it uses the firmware interface to configure the programmable logic.

Changes for v4:
                -Rebase the patch series on linux-next.
                https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

Changes for v5:
                -Updated binding doc's.

Changes for v6:
                -Updated firmware binding doc.

Appana Durga Kedareswara rao (1):
  dt-bindings: fpga: Add binding doc for versal fpga manager

Nava kishore Manne (3):
  drivers: firmware: Add PDI load API support
  dt-bindings: firmware: Add bindings for xilinx firmware
  fpga: versal-fpga: Add versal fpga manager driver

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102 +++++++++++++++
 .../bindings/fpga/xlnx,versal-fpga.yaml       |  33 +++++
 drivers/firmware/xilinx/zynqmp.c              |  17 +++
 drivers/fpga/Kconfig                          |   9 ++
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/versal-fpga.c                    | 117 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |  10 ++
 7 files changed, 289 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
 create mode 100644 drivers/fpga/versal-fpga.c

-- 
2.17.1

[PATCH v6 0/4]Add Bitstream configuration support for Versal

[Nava kishore Manne]

This series Adds FPGA manager driver support for Xilinx Versal SoC.
it uses the firmware interface to configure the programmable logic.

Changes for v4:
                -Rebase the patch series on linux-next.
                https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

Changes for v5:
                -Updated binding doc's.

Changes for v6:
                -Updated firmware binding doc.

Appana Durga Kedareswara rao (1):
  dt-bindings: fpga: Add binding doc for versal fpga manager

Nava kishore Manne (3):
  drivers: firmware: Add PDI load API support
  dt-bindings: firmware: Add bindings for xilinx firmware
  fpga: versal-fpga: Add versal fpga manager driver

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102 +++++++++++++++
 .../bindings/fpga/xlnx,versal-fpga.yaml       |  33 +++++
 drivers/firmware/xilinx/zynqmp.c              |  17 +++
 drivers/fpga/Kconfig                          |   9 ++
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/versal-fpga.c                    | 117 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |  10 ++
 7 files changed, 289 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
 create mode 100644 drivers/fpga/versal-fpga.c

-- 
2.17.1


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[PATCH v6 1/4] drivers: firmware: Add PDI load API support

[Nava kishore Manne]

This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
---
Changes for v2:
                -Updated API Doc and commit msg.
                 No functional changes.
Changes for v3:
                -None.
Changes for v4:
                -Rebased the changes on linux-next.
                 No functional changes
Changes for v5:
                -None.

Changes for v6:
               -None.

 drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 15b138326ecc..2db571da9ad8 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
 
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src:       Source device where PDI is located
+ * @address:   PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+				   lower_32_bits(address),
+				   upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
 /**
  * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
  * AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9d1a5c175065..56b426fe020c 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,10 @@
 #define	ZYNQMP_PM_CAPABILITY_WAKEUP	0x4U
 #define	ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
 
+/* Loader commands */
+#define PM_LOAD_PDI	0x701
+#define PDI_SRC_DDR	0xF
+
 /*
  * Firmware FPGA Manager flags
  * XILINX_ZYNQMP_PM_FPGA_FULL:	FPGA full reconfiguration
@@ -411,6 +415,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 				 u32 *value);
 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 				 u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 #else
 static inline int zynqmp_pm_get_api_version(u32 *version)
 {
@@ -622,6 +627,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 {
 	return -ENODEV;
 }
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.17.1

[PATCH v6 1/4] drivers: firmware: Add PDI load API support

[Nava kishore Manne]

This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
---
Changes for v2:
                -Updated API Doc and commit msg.
                 No functional changes.
Changes for v3:
                -None.
Changes for v4:
                -Rebased the changes on linux-next.
                 No functional changes
Changes for v5:
                -None.

Changes for v6:
               -None.

 drivers/firmware/xilinx/zynqmp.c     | 17 +++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 15b138326ecc..2db571da9ad8 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 }
 EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
 
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src:       Source device where PDI is located
+ * @address:   PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+	return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+				   lower_32_bits(address),
+				   upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
 /**
  * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
  * AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9d1a5c175065..56b426fe020c 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,10 @@
 #define	ZYNQMP_PM_CAPABILITY_WAKEUP	0x4U
 #define	ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
 
+/* Loader commands */
+#define PM_LOAD_PDI	0x701
+#define PDI_SRC_DDR	0xF
+
 /*
  * Firmware FPGA Manager flags
  * XILINX_ZYNQMP_PM_FPGA_FULL:	FPGA full reconfiguration
@@ -411,6 +415,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 				 u32 *value);
 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 				 u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 #else
 static inline int zynqmp_pm_get_api_version(u32 *version)
 {
@@ -622,6 +627,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 {
 	return -ENODEV;
 }
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+	return -ENODEV;
+}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.17.1


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[PATCH v6 2/4] dt-bindings: fpga: Add binding doc for versal fpga manager

[Nava kishore Manne]

From: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>

This patch adds binding doc for versal fpga manager driver.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
---
Changes for v2:
                -Fixed file format and syntax issues.
Changes for v3:
                -Removed unwated extra spaces.
Changes for v4:
                -Rebased the changes on linux-next.
                 No functional changes
Changes for v5:
                -Updated fpga node name to versal_fpga.

Changes for v6:
               -None.

 .../bindings/fpga/xlnx,versal-fpga.yaml       | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index 000000000000..ac6a207278d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal FPGA driver.
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description: |
+  Device Tree Versal FPGA bindings for the Versal SoC, controlled
+  using firmware interface.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,versal-fpga
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    versal_fpga: versal_fpga {
+         compatible = "xlnx,versal-fpga";
+    };
+
+...
-- 
2.17.1

[PATCH v6 2/4] dt-bindings: fpga: Add binding doc for versal fpga manager

[Nava kishore Manne]

From: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>

This patch adds binding doc for versal fpga manager driver.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
---
Changes for v2:
                -Fixed file format and syntax issues.
Changes for v3:
                -Removed unwated extra spaces.
Changes for v4:
                -Rebased the changes on linux-next.
                 No functional changes
Changes for v5:
                -Updated fpga node name to versal_fpga.

Changes for v6:
               -None.

 .../bindings/fpga/xlnx,versal-fpga.yaml       | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index 000000000000..ac6a207278d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal FPGA driver.
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description: |
+  Device Tree Versal FPGA bindings for the Versal SoC, controlled
+  using firmware interface.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,versal-fpga
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    versal_fpga: versal_fpga {
+         compatible = "xlnx,versal-fpga";
+    };
+
+...
-- 
2.17.1


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Re: [PATCH v6 2/4] dt-bindings: fpga: Add binding doc for versal fpga manager

[Rob Herring]

On Thu, 20 May 2021 13:39:52 +0530, Nava kishore Manne wrote:
> From: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> 
> This patch adds binding doc for versal fpga manager driver.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> ---
> Changes for v2:
>                 -Fixed file format and syntax issues.
> Changes for v3:
>                 -Removed unwated extra spaces.
> Changes for v4:
>                 -Rebased the changes on linux-next.
>                  No functional changes
> Changes for v5:
>                 -Updated fpga node name to versal_fpga.
> 
> Changes for v6:
>                -None.
> 
>  .../bindings/fpga/xlnx,versal-fpga.yaml       | 33 +++++++++++++++++++
>  1 file changed, 33 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v6 2/4] dt-bindings: fpga: Add binding doc for versal fpga manager

[Rob Herring]

On Thu, 20 May 2021 13:39:52 +0530, Nava kishore Manne wrote:
> From: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> 
> This patch adds binding doc for versal fpga manager driver.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> ---
> Changes for v2:
>                 -Fixed file format and syntax issues.
> Changes for v3:
>                 -Removed unwated extra spaces.
> Changes for v4:
>                 -Rebased the changes on linux-next.
>                  No functional changes
> Changes for v5:
>                 -Updated fpga node name to versal_fpga.
> 
> Changes for v6:
>                -None.
> 
>  .../bindings/fpga/xlnx,versal-fpga.yaml       | 33 +++++++++++++++++++
>  1 file changed, 33 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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[PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

[Nava kishore Manne]

Add documentation to describe Xilinx firmware driver bindings.
Firmware driver provides an interface to firmware APIs.
Interface APIs can be used by any driver to communicate
to Platform Management Unit.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v4:
                -Added new yaml file for xilinx firmware
                 as suggested by Rob.
Changes for v5:
                -Fixed some minor issues and updated the fpga node name to versal_fpga.

Changes for v6:
               -Added AES and Clk nodes as a sub nodes to the firmware node.

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
new file mode 100644
index 000000000000..58016191e150
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx firmware driver
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description:
+  The zynqmp-firmware node describes the interface to platform firmware.
+  ZynqMP has an interface to communicate with secure firmware. Firmware
+  driver provides an interface to firmware APIs. Interface APIs can be
+  used by any driver to communicate to PMUFW(Platform Management Unit).
+  These requests include clock management, pin control, device control,
+  power management service, FPGA service and other platform management
+  services.
+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          For implementations complying for Zynq Ultrascale+ MPSoC.
+        const: xlnx,zynqmp-firmware
+
+      - description:
+          For implementations complying for Versal.
+        const: xlnx,versal-firmware
+
+  method:
+    description: |
+                 The method of calling the PM-API firmware layer.
+                 Permitted values are.
+                 - "smc" : SMC #0, following the SMCCC
+                 - "hvc" : HVC #0, following the SMCCC
+
+    $ref: /schemas/types.yaml#/definitions/string-array
+    enum:
+      - smc
+      - hvc
+
+patternProperties:
+  "versal_fpga":
+    $ref: "../../fpga/xlnx,versal-fpga.yaml#"
+    description: Compatible of the FPGA device.
+    type: object
+    required:
+      - compatible
+
+  "zynqmp-aes":
+    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
+    description: |
+                 The ZynqMP AES-GCM hardened cryptographic accelerator is
+                 used to encrypt or decrypt the data with provided key and
+                 initialization vector.
+    type: object
+    required:
+      - compatible
+
+  "clock-controller":
+    $ref: "../../clock/xlnx,versal-clk.yaml#"
+    description: |
+                 The clock controller is a hardware block of Xilinx versal
+                 clock tree. It reads required input clock frequencies from
+                 the devicetree and acts as clock provider for all clock
+                 consumers of PS clocks.list of clock specifiers which are
+                 external input clocks to the given clock controller.
+    type: object
+    required:
+      - compatible
+      - "#clock-cells"
+      - clocks
+      - clock-names
+
+required:
+  - compatible
+
+examples:
+  - |
+    versal-firmware {
+      compatible = "xlnx,versal-firmware";
+      method = "smc";
+
+      versal_fpga: versal_fpga {
+        compatible = "xlnx,versal-fpga";
+      };
+
+      xlnx_aes: zynqmp-aes {
+        compatible = "xlnx,zynqmp-aes";
+      };
+
+      versal_clk: clock-controller {
+        #clock-cells = <1>;
+        compatible = "xlnx,versal-clk";
+        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
+        clock-names = "ref", "alt_ref", "pl_alt_ref";
+      };
+    };
+
+additionalProperties: false
-- 
2.17.1

[PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

[Nava kishore Manne]

Add documentation to describe Xilinx firmware driver bindings.
Firmware driver provides an interface to firmware APIs.
Interface APIs can be used by any driver to communicate
to Platform Management Unit.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v4:
                -Added new yaml file for xilinx firmware
                 as suggested by Rob.
Changes for v5:
                -Fixed some minor issues and updated the fpga node name to versal_fpga.

Changes for v6:
               -Added AES and Clk nodes as a sub nodes to the firmware node.

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
new file mode 100644
index 000000000000..58016191e150
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx firmware driver
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description:
+  The zynqmp-firmware node describes the interface to platform firmware.
+  ZynqMP has an interface to communicate with secure firmware. Firmware
+  driver provides an interface to firmware APIs. Interface APIs can be
+  used by any driver to communicate to PMUFW(Platform Management Unit).
+  These requests include clock management, pin control, device control,
+  power management service, FPGA service and other platform management
+  services.
+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          For implementations complying for Zynq Ultrascale+ MPSoC.
+        const: xlnx,zynqmp-firmware
+
+      - description:
+          For implementations complying for Versal.
+        const: xlnx,versal-firmware
+
+  method:
+    description: |
+                 The method of calling the PM-API firmware layer.
+                 Permitted values are.
+                 - "smc" : SMC #0, following the SMCCC
+                 - "hvc" : HVC #0, following the SMCCC
+
+    $ref: /schemas/types.yaml#/definitions/string-array
+    enum:
+      - smc
+      - hvc
+
+patternProperties:
+  "versal_fpga":
+    $ref: "../../fpga/xlnx,versal-fpga.yaml#"
+    description: Compatible of the FPGA device.
+    type: object
+    required:
+      - compatible
+
+  "zynqmp-aes":
+    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
+    description: |
+                 The ZynqMP AES-GCM hardened cryptographic accelerator is
+                 used to encrypt or decrypt the data with provided key and
+                 initialization vector.
+    type: object
+    required:
+      - compatible
+
+  "clock-controller":
+    $ref: "../../clock/xlnx,versal-clk.yaml#"
+    description: |
+                 The clock controller is a hardware block of Xilinx versal
+                 clock tree. It reads required input clock frequencies from
+                 the devicetree and acts as clock provider for all clock
+                 consumers of PS clocks.list of clock specifiers which are
+                 external input clocks to the given clock controller.
+    type: object
+    required:
+      - compatible
+      - "#clock-cells"
+      - clocks
+      - clock-names
+
+required:
+  - compatible
+
+examples:
+  - |
+    versal-firmware {
+      compatible = "xlnx,versal-firmware";
+      method = "smc";
+
+      versal_fpga: versal_fpga {
+        compatible = "xlnx,versal-fpga";
+      };
+
+      xlnx_aes: zynqmp-aes {
+        compatible = "xlnx,zynqmp-aes";
+      };
+
+      versal_clk: clock-controller {
+        #clock-cells = <1>;
+        compatible = "xlnx,versal-clk";
+        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
+        clock-names = "ref", "alt_ref", "pl_alt_ref";
+      };
+    };
+
+additionalProperties: false
-- 
2.17.1


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Re: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

[Rob Herring]

On Thu, May 20, 2021 at 01:39:53PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx firmware driver bindings.
> Firmware driver provides an interface to firmware APIs.
> Interface APIs can be used by any driver to communicate
> to Platform Management Unit.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v4:
>                 -Added new yaml file for xilinx firmware
>                  as suggested by Rob.
> Changes for v5:
>                 -Fixed some minor issues and updated the fpga node name to versal_fpga.
> 
> Changes for v6:
>                -Added AES and Clk nodes as a sub nodes to the firmware node.
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102 ++++++++++++++++++
>  1 file changed, 102 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> 
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> new file mode 100644
> index 000000000000..58016191e150
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx firmware driver
> +
> +maintainers:
> +  - Nava kishore Manne <nava.manne@xilinx.com>
> +
> +description:
> +  The zynqmp-firmware node describes the interface to platform firmware.
> +  ZynqMP has an interface to communicate with secure firmware. Firmware
> +  driver provides an interface to firmware APIs. Interface APIs can be
> +  used by any driver to communicate to PMUFW(Platform Management Unit).
> +  These requests include clock management, pin control, device control,
> +  power management service, FPGA service and other platform management
> +  services.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - description:
> +          For implementations complying for Zynq Ultrascale+ MPSoC.
> +        const: xlnx,zynqmp-firmware
> +
> +      - description:
> +          For implementations complying for Versal.
> +        const: xlnx,versal-firmware
> +
> +  method:
> +    description: |
> +                 The method of calling the PM-API firmware layer.
> +                 Permitted values are.
> +                 - "smc" : SMC #0, following the SMCCC
> +                 - "hvc" : HVC #0, following the SMCCC
> +
> +    $ref: /schemas/types.yaml#/definitions/string-array
> +    enum:
> +      - smc
> +      - hvc
> +
> +patternProperties:
> +  "versal_fpga":

This says 'fooversal_fpgabar' is a valid node name.

You don't need a pattern, move under 'properties'. Same for the other 
child nodes.

> +    $ref: "../../fpga/xlnx,versal-fpga.yaml#"

/schemas/fpga/...

Don't need quotes.

> +    description: Compatible of the FPGA device.
> +    type: object
> +    required:
> +      - compatible

Drop. What's required should be in xlnx,versal-fpga.yaml.

> +
> +  "zynqmp-aes":

Same comments as above on the rest of the child nodes.

> +    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
> +    description: |
> +                 The ZynqMP AES-GCM hardened cryptographic accelerator is
> +                 used to encrypt or decrypt the data with provided key and
> +                 initialization vector.
> +    type: object
> +    required:
> +      - compatible
> +
> +  "clock-controller":
> +    $ref: "../../clock/xlnx,versal-clk.yaml#"
> +    description: |
> +                 The clock controller is a hardware block of Xilinx versal
> +                 clock tree. It reads required input clock frequencies from
> +                 the devicetree and acts as clock provider for all clock
> +                 consumers of PS clocks.list of clock specifiers which are
> +                 external input clocks to the given clock controller.
> +    type: object
> +    required:
> +      - compatible
> +      - "#clock-cells"
> +      - clocks
> +      - clock-names
> +
> +required:
> +  - compatible
> +
> +examples:
> +  - |
> +    versal-firmware {
> +      compatible = "xlnx,versal-firmware";
> +      method = "smc";
> +
> +      versal_fpga: versal_fpga {
> +        compatible = "xlnx,versal-fpga";
> +      };
> +
> +      xlnx_aes: zynqmp-aes {
> +        compatible = "xlnx,zynqmp-aes";
> +      };
> +
> +      versal_clk: clock-controller {
> +        #clock-cells = <1>;
> +        compatible = "xlnx,versal-clk";
> +        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> +        clock-names = "ref", "alt_ref", "pl_alt_ref";
> +      };
> +    };
> +
> +additionalProperties: false

Move this before the example.

Re: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

[Rob Herring]

On Thu, May 20, 2021 at 01:39:53PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx firmware driver bindings.
> Firmware driver provides an interface to firmware APIs.
> Interface APIs can be used by any driver to communicate
> to Platform Management Unit.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v4:
>                 -Added new yaml file for xilinx firmware
>                  as suggested by Rob.
> Changes for v5:
>                 -Fixed some minor issues and updated the fpga node name to versal_fpga.
> 
> Changes for v6:
>                -Added AES and Clk nodes as a sub nodes to the firmware node.
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102 ++++++++++++++++++
>  1 file changed, 102 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> 
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> new file mode 100644
> index 000000000000..58016191e150
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx firmware driver
> +
> +maintainers:
> +  - Nava kishore Manne <nava.manne@xilinx.com>
> +
> +description:
> +  The zynqmp-firmware node describes the interface to platform firmware.
> +  ZynqMP has an interface to communicate with secure firmware. Firmware
> +  driver provides an interface to firmware APIs. Interface APIs can be
> +  used by any driver to communicate to PMUFW(Platform Management Unit).
> +  These requests include clock management, pin control, device control,
> +  power management service, FPGA service and other platform management
> +  services.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - description:
> +          For implementations complying for Zynq Ultrascale+ MPSoC.
> +        const: xlnx,zynqmp-firmware
> +
> +      - description:
> +          For implementations complying for Versal.
> +        const: xlnx,versal-firmware
> +
> +  method:
> +    description: |
> +                 The method of calling the PM-API firmware layer.
> +                 Permitted values are.
> +                 - "smc" : SMC #0, following the SMCCC
> +                 - "hvc" : HVC #0, following the SMCCC
> +
> +    $ref: /schemas/types.yaml#/definitions/string-array
> +    enum:
> +      - smc
> +      - hvc
> +
> +patternProperties:
> +  "versal_fpga":

This says 'fooversal_fpgabar' is a valid node name.

You don't need a pattern, move under 'properties'. Same for the other 
child nodes.

> +    $ref: "../../fpga/xlnx,versal-fpga.yaml#"

/schemas/fpga/...

Don't need quotes.

> +    description: Compatible of the FPGA device.
> +    type: object
> +    required:
> +      - compatible

Drop. What's required should be in xlnx,versal-fpga.yaml.

> +
> +  "zynqmp-aes":

Same comments as above on the rest of the child nodes.

> +    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
> +    description: |
> +                 The ZynqMP AES-GCM hardened cryptographic accelerator is
> +                 used to encrypt or decrypt the data with provided key and
> +                 initialization vector.
> +    type: object
> +    required:
> +      - compatible
> +
> +  "clock-controller":
> +    $ref: "../../clock/xlnx,versal-clk.yaml#"
> +    description: |
> +                 The clock controller is a hardware block of Xilinx versal
> +                 clock tree. It reads required input clock frequencies from
> +                 the devicetree and acts as clock provider for all clock
> +                 consumers of PS clocks.list of clock specifiers which are
> +                 external input clocks to the given clock controller.
> +    type: object
> +    required:
> +      - compatible
> +      - "#clock-cells"
> +      - clocks
> +      - clock-names
> +
> +required:
> +  - compatible
> +
> +examples:
> +  - |
> +    versal-firmware {
> +      compatible = "xlnx,versal-firmware";
> +      method = "smc";
> +
> +      versal_fpga: versal_fpga {
> +        compatible = "xlnx,versal-fpga";
> +      };
> +
> +      xlnx_aes: zynqmp-aes {
> +        compatible = "xlnx,zynqmp-aes";
> +      };
> +
> +      versal_clk: clock-controller {
> +        #clock-cells = <1>;
> +        compatible = "xlnx,versal-clk";
> +        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> +        clock-names = "ref", "alt_ref", "pl_alt_ref";
> +      };
> +    };
> +
> +additionalProperties: false

Move this before the example.

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RE: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

[Nava kishore Manne]

Hi Rob,

	Thanks for providing the review comments.
Please find my response inline.

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, June 3, 2021 12:02 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Michal Simek <michals@xilinx.com>; mdf@kernel.org; trix@redhat.com;
> arnd@arndb.de; Rajan Vaja <RAJANV@xilinx.com>;
> gregkh@linuxfoundation.org; Amit Sunil Dhamne
> <amitsuni@xlnx.xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>;
> zou_wei@huawei.com; Sai Krishna Potthuri <lakshmis@xilinx.com>; Ravi
> Patel <RAVIPATE@xilinx.com>; iwamatsu@nigauri.org; Jiaying Liang
> <jliang@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git <git@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx
> firmware
> 
> On Thu, May 20, 2021 at 01:39:53PM +0530, Nava kishore Manne wrote:
> > Add documentation to describe Xilinx firmware driver bindings.
> > Firmware driver provides an interface to firmware APIs.
> > Interface APIs can be used by any driver to communicate to Platform
> > Management Unit.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v4:
> >                 -Added new yaml file for xilinx firmware
> >                  as suggested by Rob.
> > Changes for v5:
> >                 -Fixed some minor issues and updated the fpga node name to
> versal_fpga.
> >
> > Changes for v6:
> >                -Added AES and Clk nodes as a sub nodes to the firmware node.
> >
> >  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102
> > ++++++++++++++++++
> >  1 file changed, 102 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmware
> > .yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > new file mode 100644
> > index 000000000000..58016191e150
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > +++ rmware.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.ya
> > +ml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx firmware driver
> > +
> > +maintainers:
> > +  - Nava kishore Manne <nava.manne@xilinx.com>
> > +
> > +description:
> > +  The zynqmp-firmware node describes the interface to platform
> firmware.
> > +  ZynqMP has an interface to communicate with secure firmware.
> > +Firmware
> > +  driver provides an interface to firmware APIs. Interface APIs can
> > +be
> > +  used by any driver to communicate to PMUFW(Platform Management
> Unit).
> > +  These requests include clock management, pin control, device
> > +control,
> > +  power management service, FPGA service and other platform
> > +management
> > +  services.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - description:
> > +          For implementations complying for Zynq Ultrascale+ MPSoC.
> > +        const: xlnx,zynqmp-firmware
> > +
> > +      - description:
> > +          For implementations complying for Versal.
> > +        const: xlnx,versal-firmware
> > +
> > +  method:
> > +    description: |
> > +                 The method of calling the PM-API firmware layer.
> > +                 Permitted values are.
> > +                 - "smc" : SMC #0, following the SMCCC
> > +                 - "hvc" : HVC #0, following the SMCCC
> > +
> > +    $ref: /schemas/types.yaml#/definitions/string-array
> > +    enum:
> > +      - smc
> > +      - hvc
> > +
> > +patternProperties:
> > +  "versal_fpga":
> 
> This says 'fooversal_fpgabar' is a valid node name.
> 
> You don't need a pattern, move under 'properties'. Same for the other child
> nodes.
> 

Will fix in v7.

> > +    $ref: "../../fpga/xlnx,versal-fpga.yaml#"
> 
> /schemas/fpga/...
> 
> Don't need quotes.
> 

Will fix in v7.

> > +    description: Compatible of the FPGA device.
> > +    type: object
> > +    required:
> > +      - compatible
> 
> Drop. What's required should be in xlnx,versal-fpga.yaml.
> 

Will fix in v7.

> > +
> > +  "zynqmp-aes":
> 
> Same comments as above on the rest of the child nodes.
> 

Will fix in v7.

> > +    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
> > +    description: |
> > +                 The ZynqMP AES-GCM hardened cryptographic accelerator is
> > +                 used to encrypt or decrypt the data with provided key and
> > +                 initialization vector.
> > +    type: object
> > +    required:
> > +      - compatible
> > +
> > +  "clock-controller":
> > +    $ref: "../../clock/xlnx,versal-clk.yaml#"
> > +    description: |
> > +                 The clock controller is a hardware block of Xilinx versal
> > +                 clock tree. It reads required input clock frequencies from
> > +                 the devicetree and acts as clock provider for all clock
> > +                 consumers of PS clocks.list of clock specifiers which are
> > +                 external input clocks to the given clock controller.
> > +    type: object
> > +    required:
> > +      - compatible
> > +      - "#clock-cells"
> > +      - clocks
> > +      - clock-names
> > +
> > +required:
> > +  - compatible
> > +
> > +examples:
> > +  - |
> > +    versal-firmware {
> > +      compatible = "xlnx,versal-firmware";
> > +      method = "smc";
> > +
> > +      versal_fpga: versal_fpga {
> > +        compatible = "xlnx,versal-fpga";
> > +      };
> > +
> > +      xlnx_aes: zynqmp-aes {
> > +        compatible = "xlnx,zynqmp-aes";
> > +      };
> > +
> > +      versal_clk: clock-controller {
> > +        #clock-cells = <1>;
> > +        compatible = "xlnx,versal-clk";
> > +        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> > +        clock-names = "ref", "alt_ref", "pl_alt_ref";
> > +      };
> > +    };
> > +
> > +additionalProperties: false
> 
> Move this before the example.

Will fix in v7.

Regards,
Navakishore.

RE: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx firmware

[Nava kishore Manne]

Hi Rob,

	Thanks for providing the review comments.
Please find my response inline.

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, June 3, 2021 12:02 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Michal Simek <michals@xilinx.com>; mdf@kernel.org; trix@redhat.com;
> arnd@arndb.de; Rajan Vaja <RAJANV@xilinx.com>;
> gregkh@linuxfoundation.org; Amit Sunil Dhamne
> <amitsuni@xlnx.xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>;
> zou_wei@huawei.com; Sai Krishna Potthuri <lakshmis@xilinx.com>; Ravi
> Patel <RAVIPATE@xilinx.com>; iwamatsu@nigauri.org; Jiaying Liang
> <jliang@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git <git@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx
> firmware
> 
> On Thu, May 20, 2021 at 01:39:53PM +0530, Nava kishore Manne wrote:
> > Add documentation to describe Xilinx firmware driver bindings.
> > Firmware driver provides an interface to firmware APIs.
> > Interface APIs can be used by any driver to communicate to Platform
> > Management Unit.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v4:
> >                 -Added new yaml file for xilinx firmware
> >                  as suggested by Rob.
> > Changes for v5:
> >                 -Fixed some minor issues and updated the fpga node name to
> versal_fpga.
> >
> > Changes for v6:
> >                -Added AES and Clk nodes as a sub nodes to the firmware node.
> >
> >  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102
> > ++++++++++++++++++
> >  1 file changed, 102 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmware
> > .yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > new file mode 100644
> > index 000000000000..58016191e150
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > +++ rmware.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.ya
> > +ml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx firmware driver
> > +
> > +maintainers:
> > +  - Nava kishore Manne <nava.manne@xilinx.com>
> > +
> > +description:
> > +  The zynqmp-firmware node describes the interface to platform
> firmware.
> > +  ZynqMP has an interface to communicate with secure firmware.
> > +Firmware
> > +  driver provides an interface to firmware APIs. Interface APIs can
> > +be
> > +  used by any driver to communicate to PMUFW(Platform Management
> Unit).
> > +  These requests include clock management, pin control, device
> > +control,
> > +  power management service, FPGA service and other platform
> > +management
> > +  services.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - description:
> > +          For implementations complying for Zynq Ultrascale+ MPSoC.
> > +        const: xlnx,zynqmp-firmware
> > +
> > +      - description:
> > +          For implementations complying for Versal.
> > +        const: xlnx,versal-firmware
> > +
> > +  method:
> > +    description: |
> > +                 The method of calling the PM-API firmware layer.
> > +                 Permitted values are.
> > +                 - "smc" : SMC #0, following the SMCCC
> > +                 - "hvc" : HVC #0, following the SMCCC
> > +
> > +    $ref: /schemas/types.yaml#/definitions/string-array
> > +    enum:
> > +      - smc
> > +      - hvc
> > +
> > +patternProperties:
> > +  "versal_fpga":
> 
> This says 'fooversal_fpgabar' is a valid node name.
> 
> You don't need a pattern, move under 'properties'. Same for the other child
> nodes.
> 

Will fix in v7.

> > +    $ref: "../../fpga/xlnx,versal-fpga.yaml#"
> 
> /schemas/fpga/...
> 
> Don't need quotes.
> 

Will fix in v7.

> > +    description: Compatible of the FPGA device.
> > +    type: object
> > +    required:
> > +      - compatible
> 
> Drop. What's required should be in xlnx,versal-fpga.yaml.
> 

Will fix in v7.

> > +
> > +  "zynqmp-aes":
> 
> Same comments as above on the rest of the child nodes.
> 

Will fix in v7.

> > +    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
> > +    description: |
> > +                 The ZynqMP AES-GCM hardened cryptographic accelerator is
> > +                 used to encrypt or decrypt the data with provided key and
> > +                 initialization vector.
> > +    type: object
> > +    required:
> > +      - compatible
> > +
> > +  "clock-controller":
> > +    $ref: "../../clock/xlnx,versal-clk.yaml#"
> > +    description: |
> > +                 The clock controller is a hardware block of Xilinx versal
> > +                 clock tree. It reads required input clock frequencies from
> > +                 the devicetree and acts as clock provider for all clock
> > +                 consumers of PS clocks.list of clock specifiers which are
> > +                 external input clocks to the given clock controller.
> > +    type: object
> > +    required:
> > +      - compatible
> > +      - "#clock-cells"
> > +      - clocks
> > +      - clock-names
> > +
> > +required:
> > +  - compatible
> > +
> > +examples:
> > +  - |
> > +    versal-firmware {
> > +      compatible = "xlnx,versal-firmware";
> > +      method = "smc";
> > +
> > +      versal_fpga: versal_fpga {
> > +        compatible = "xlnx,versal-fpga";
> > +      };
> > +
> > +      xlnx_aes: zynqmp-aes {
> > +        compatible = "xlnx,zynqmp-aes";
> > +      };
> > +
> > +      versal_clk: clock-controller {
> > +        #clock-cells = <1>;
> > +        compatible = "xlnx,versal-clk";
> > +        clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> > +        clock-names = "ref", "alt_ref", "pl_alt_ref";
> > +      };
> > +    };
> > +
> > +additionalProperties: false
> 
> Move this before the example.

Will fix in v7.

Regards,
Navakishore.

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[PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Nava kishore Manne]

Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
---
Changes for v2:
                -Updated the Fpga Mgr registrations call's
                 to 5.11
                -Fixed some minor coding issues as suggested by
                 Moritz.
Changes for v3:
                -Rewritten the Versal fpga Kconfig contents.
Changes for v4:
                -Rebased the changes on linux-next.
                 No functional changes.
Changes for v5:
                -None.
Changes for v6:
                -None.

 drivers/fpga/Kconfig       |   9 +++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++
 3 files changed, 127 insertions(+)
 create mode 100644 drivers/fpga/versal-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 33e15058d0dc..92c20b92357a 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
 	  to configure the programmable logic(PL) through PS
 	  on ZynqMP SoC.
 
+config FPGA_MGR_VERSAL_FPGA
+	tristate "Xilinx Versal FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  Select this option to enable FPGA manager driver support for
+	  Xilinx Versal SoC. This driver uses the firmware interface to
+	  configure the programmable logic(PL).
+
+	  To compile this as a module, choose M here.
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a..0bff783d1b61 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index 000000000000..5744e44f981d
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/**
+ * struct versal_fpga_priv - Private data structure
+ * @dev:	Device data structure
+ */
+struct versal_fpga_priv {
+	struct device *dev;
+};
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	struct versal_fpga_priv *priv;
+	dma_addr_t dma_addr = 0;
+	char *kbuf;
+	int ret;
+
+	priv = mgr->priv;
+
+	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+
+	wmb(); /* ensure all writes are done before initiate FW call */
+
+	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
+
+	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+	.state = versal_fpga_ops_state,
+	.write_init = versal_fpga_ops_write_init,
+	.write = versal_fpga_ops_write,
+	.write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct versal_fpga_priv *priv;
+	struct fpga_manager *mgr;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret < 0) {
+		dev_err(dev, "no usable DMA configuration\n");
+		return ret;
+	}
+
+	mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+				   &versal_fpga_ops, priv);
+	if (!mgr)
+		return -ENOMEM;
+
+	return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+	{ .compatible = "xlnx,versal-fpga", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_driver versal_fpga_driver = {
+	.probe = versal_fpga_probe,
+	.driver = {
+		.name = "versal_fpga_manager",
+		.of_match_table = of_match_ptr(versal_fpga_of_match),
+	},
+};
+module_platform_driver(versal_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
+MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.17.1

[PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Nava kishore Manne]

Add support for Xilinx Versal FPGA manager.

PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
---
Changes for v2:
                -Updated the Fpga Mgr registrations call's
                 to 5.11
                -Fixed some minor coding issues as suggested by
                 Moritz.
Changes for v3:
                -Rewritten the Versal fpga Kconfig contents.
Changes for v4:
                -Rebased the changes on linux-next.
                 No functional changes.
Changes for v5:
                -None.
Changes for v6:
                -None.

 drivers/fpga/Kconfig       |   9 +++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++
 3 files changed, 127 insertions(+)
 create mode 100644 drivers/fpga/versal-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 33e15058d0dc..92c20b92357a 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
 	  to configure the programmable logic(PL) through PS
 	  on ZynqMP SoC.
 
+config FPGA_MGR_VERSAL_FPGA
+	tristate "Xilinx Versal FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  Select this option to enable FPGA manager driver support for
+	  Xilinx Versal SoC. This driver uses the firmware interface to
+	  configure the programmable logic(PL).
+
+	  To compile this as a module, choose M here.
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a..0bff783d1b61 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index 000000000000..5744e44f981d
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/**
+ * struct versal_fpga_priv - Private data structure
+ * @dev:	Device data structure
+ */
+struct versal_fpga_priv {
+	struct device *dev;
+};
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	struct versal_fpga_priv *priv;
+	dma_addr_t dma_addr = 0;
+	char *kbuf;
+	int ret;
+
+	priv = mgr->priv;
+
+	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+
+	wmb(); /* ensure all writes are done before initiate FW call */
+
+	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
+
+	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+	.state = versal_fpga_ops_state,
+	.write_init = versal_fpga_ops_write_init,
+	.write = versal_fpga_ops_write,
+	.write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct versal_fpga_priv *priv;
+	struct fpga_manager *mgr;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	if (ret < 0) {
+		dev_err(dev, "no usable DMA configuration\n");
+		return ret;
+	}
+
+	mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+				   &versal_fpga_ops, priv);
+	if (!mgr)
+		return -ENOMEM;
+
+	return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+	{ .compatible = "xlnx,versal-fpga", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_driver versal_fpga_driver = {
+	.probe = versal_fpga_probe,
+	.driver = {
+		.name = "versal_fpga_manager",
+		.of_match_table = of_match_ptr(versal_fpga_of_match),
+	},
+};
+module_platform_driver(versal_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
+MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.17.1


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Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Greg KH]

On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote:
> Add support for Xilinx Versal FPGA manager.
> 
> PDI source type can be DDR, OCM, QSPI flash etc..
> But driver allocates memory always from DDR, Since driver supports only
> DDR source type.
> 
> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> Changes for v2:
>                 -Updated the Fpga Mgr registrations call's
>                  to 5.11
>                 -Fixed some minor coding issues as suggested by
>                  Moritz.
> Changes for v3:
>                 -Rewritten the Versal fpga Kconfig contents.
> Changes for v4:
>                 -Rebased the changes on linux-next.
>                  No functional changes.
> Changes for v5:
>                 -None.
> Changes for v6:
>                 -None.
> 
>  drivers/fpga/Kconfig       |   9 +++
>  drivers/fpga/Makefile      |   1 +
>  drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 127 insertions(+)
>  create mode 100644 drivers/fpga/versal-fpga.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 33e15058d0dc..92c20b92357a 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
>  	  to configure the programmable logic(PL) through PS
>  	  on ZynqMP SoC.
>  
> +config FPGA_MGR_VERSAL_FPGA
> +	tristate "Xilinx Versal FPGA"
> +	depends on ARCH_ZYNQMP || COMPILE_TEST
> +	help
> +	  Select this option to enable FPGA manager driver support for
> +	  Xilinx Versal SoC. This driver uses the firmware interface to
> +	  configure the programmable logic(PL).
> +
> +	  To compile this as a module, choose M here.
>  endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 18dc9885883a..0bff783d1b61 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
>  
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> new file mode 100644
> index 000000000000..5744e44f981d
> --- /dev/null
> +++ b/drivers/fpga/versal-fpga.c
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019-2021 Xilinx, Inc.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/string.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +/**
> + * struct versal_fpga_priv - Private data structure
> + * @dev:	Device data structure
> + */
> +struct versal_fpga_priv {
> +	struct device *dev;
> +};

Don't you have this pointer already?  What device is this exactly and
why does it differ from the structure it currently lives in?

> +
> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> +				      struct fpga_image_info *info,
> +				      const char *buf, size_t size)
> +{
> +	return 0;
> +}

If you don't need this, why include it?

> +
> +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> +				 const char *buf, size_t size)
> +{
> +	struct versal_fpga_priv *priv;
> +	dma_addr_t dma_addr = 0;
> +	char *kbuf;
> +	int ret;
> +
> +	priv = mgr->priv;
> +
> +	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> +	if (!kbuf)
> +		return -ENOMEM;
> +
> +	memcpy(kbuf, buf, size);
> +
> +	wmb(); /* ensure all writes are done before initiate FW call */

What "writes"?  The memcpy above?  Are you _SURE_ that really is correct
here?  This feels wrong.

> +
> +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);

If this needs some sort of barrier, shouldn't it be in this call?

> +
> +	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> +
> +	return ret;
> +}
> +
> +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> +					  struct fpga_image_info *info)
> +{
> +	return 0;
> +}

Again, why have it if it does nothing?

> +
> +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
> +{
> +	return FPGA_MGR_STATE_UNKNOWN;
> +}

Again, is this needed?  If so, then the fpga_manager core needs to be
fixed up :)

> +static const struct fpga_manager_ops versal_fpga_ops = {
> +	.state = versal_fpga_ops_state,
> +	.write_init = versal_fpga_ops_write_init,
> +	.write = versal_fpga_ops_write,
> +	.write_complete = versal_fpga_ops_write_complete,
> +};
> +
> +static int versal_fpga_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct versal_fpga_priv *priv;
> +	struct fpga_manager *mgr;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->dev = dev;

You save a pointer to a reference counted structure, without
incrementing the reference count.  What could go wrong?  :)

You are getting lucky here, but as stated above, why do you need this
pointer?

thanks,

greg k-h

Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Greg KH]

On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote:
> Add support for Xilinx Versal FPGA manager.
> 
> PDI source type can be DDR, OCM, QSPI flash etc..
> But driver allocates memory always from DDR, Since driver supports only
> DDR source type.
> 
> Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> Changes for v2:
>                 -Updated the Fpga Mgr registrations call's
>                  to 5.11
>                 -Fixed some minor coding issues as suggested by
>                  Moritz.
> Changes for v3:
>                 -Rewritten the Versal fpga Kconfig contents.
> Changes for v4:
>                 -Rebased the changes on linux-next.
>                  No functional changes.
> Changes for v5:
>                 -None.
> Changes for v6:
>                 -None.
> 
>  drivers/fpga/Kconfig       |   9 +++
>  drivers/fpga/Makefile      |   1 +
>  drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 127 insertions(+)
>  create mode 100644 drivers/fpga/versal-fpga.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 33e15058d0dc..92c20b92357a 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
>  	  to configure the programmable logic(PL) through PS
>  	  on ZynqMP SoC.
>  
> +config FPGA_MGR_VERSAL_FPGA
> +	tristate "Xilinx Versal FPGA"
> +	depends on ARCH_ZYNQMP || COMPILE_TEST
> +	help
> +	  Select this option to enable FPGA manager driver support for
> +	  Xilinx Versal SoC. This driver uses the firmware interface to
> +	  configure the programmable logic(PL).
> +
> +	  To compile this as a module, choose M here.
>  endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 18dc9885883a..0bff783d1b61 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
>  
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> new file mode 100644
> index 000000000000..5744e44f981d
> --- /dev/null
> +++ b/drivers/fpga/versal-fpga.c
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019-2021 Xilinx, Inc.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/string.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +/**
> + * struct versal_fpga_priv - Private data structure
> + * @dev:	Device data structure
> + */
> +struct versal_fpga_priv {
> +	struct device *dev;
> +};

Don't you have this pointer already?  What device is this exactly and
why does it differ from the structure it currently lives in?

> +
> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> +				      struct fpga_image_info *info,
> +				      const char *buf, size_t size)
> +{
> +	return 0;
> +}

If you don't need this, why include it?

> +
> +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> +				 const char *buf, size_t size)
> +{
> +	struct versal_fpga_priv *priv;
> +	dma_addr_t dma_addr = 0;
> +	char *kbuf;
> +	int ret;
> +
> +	priv = mgr->priv;
> +
> +	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> +	if (!kbuf)
> +		return -ENOMEM;
> +
> +	memcpy(kbuf, buf, size);
> +
> +	wmb(); /* ensure all writes are done before initiate FW call */

What "writes"?  The memcpy above?  Are you _SURE_ that really is correct
here?  This feels wrong.

> +
> +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);

If this needs some sort of barrier, shouldn't it be in this call?

> +
> +	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> +
> +	return ret;
> +}
> +
> +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> +					  struct fpga_image_info *info)
> +{
> +	return 0;
> +}

Again, why have it if it does nothing?

> +
> +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
> +{
> +	return FPGA_MGR_STATE_UNKNOWN;
> +}

Again, is this needed?  If so, then the fpga_manager core needs to be
fixed up :)

> +static const struct fpga_manager_ops versal_fpga_ops = {
> +	.state = versal_fpga_ops_state,
> +	.write_init = versal_fpga_ops_write_init,
> +	.write = versal_fpga_ops_write,
> +	.write_complete = versal_fpga_ops_write_complete,
> +};
> +
> +static int versal_fpga_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct versal_fpga_priv *priv;
> +	struct fpga_manager *mgr;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->dev = dev;

You save a pointer to a reference counted structure, without
incrementing the reference count.  What could go wrong?  :)

You are getting lucky here, but as stated above, why do you need this
pointer?

thanks,

greg k-h

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Nava kishore Manne]

Hi Greg,

	Thanks for providing the review comments.
Please find my response inline.

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, May 20, 2021 2:19 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: robh+dt@kernel.org; Michal Simek <michals@xilinx.com>;
> mdf@kernel.org; trix@redhat.com; arnd@arndb.de; Rajan Vaja
> <RAJANV@xilinx.com>; Amit Sunil Dhamne <amitsuni@xlnx.xilinx.com>;
> Tejas Patel <tejasp@xlnx.xilinx.com>; zou_wei@huawei.com; Sai Krishna
> Potthuri <lakshmis@xilinx.com>; Ravi Patel <RAVIPATE@xilinx.com>;
> iwamatsu@nigauri.org; Jiaying Liang <jliang@xilinx.com>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org; git <git@xilinx.com>;
> chinnikishore369@gmail.com; Appana Durga Kedareswara Rao
> <appanad@xilinx.com>
> Subject: Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver
> 
> On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote:
> > Add support for Xilinx Versal FPGA manager.
> >
> > PDI source type can be DDR, OCM, QSPI flash etc..
> > But driver allocates memory always from DDR, Since driver supports
> > only DDR source type.
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> > <appana.durga.rao@xilinx.com>
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > Reviewed-by: Moritz Fischer <mdf@kernel.org>
> > ---
> > Changes for v2:
> >                 -Updated the Fpga Mgr registrations call's
> >                  to 5.11
> >                 -Fixed some minor coding issues as suggested by
> >                  Moritz.
> > Changes for v3:
> >                 -Rewritten the Versal fpga Kconfig contents.
> > Changes for v4:
> >                 -Rebased the changes on linux-next.
> >                  No functional changes.
> > Changes for v5:
> >                 -None.
> > Changes for v6:
> >                 -None.
> >
> >  drivers/fpga/Kconfig       |   9 +++
> >  drivers/fpga/Makefile      |   1 +
> >  drivers/fpga/versal-fpga.c | 117
> > +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 127 insertions(+)
> >  create mode 100644 drivers/fpga/versal-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 33e15058d0dc..92c20b92357a 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> >  	  to configure the programmable logic(PL) through PS
> >  	  on ZynqMP SoC.
> >
> > +config FPGA_MGR_VERSAL_FPGA
> > +	tristate "Xilinx Versal FPGA"
> > +	depends on ARCH_ZYNQMP || COMPILE_TEST
> > +	help
> > +	  Select this option to enable FPGA manager driver support for
> > +	  Xilinx Versal SoC. This driver uses the firmware interface to
> > +	  configure the programmable logic(PL).
> > +
> > +	  To compile this as a module, choose M here.
> >  endif # FPGA
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 18dc9885883a..0bff783d1b61 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+=
> ts73xx-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> > new file mode 100644 index 000000000000..5744e44f981d
> > --- /dev/null
> > +++ b/drivers/fpga/versal-fpga.c
> > @@ -0,0 +1,117 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019-2021 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +/**
> > + * struct versal_fpga_priv - Private data structure
> > + * @dev:	Device data structure
> > + */
> > +struct versal_fpga_priv {
> > +	struct device *dev;
> > +};
> 
> Don't you have this pointer already?  What device is this exactly and why
> does it differ from the structure it currently lives in?
> 
Agree, this struct is not needed.
Will fix this issue in v7.

> > +
> > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> > +				      struct fpga_image_info *info,
> > +				      const char *buf, size_t size) {
> > +	return 0;
> > +}
> 
> If you don't need this, why include it?
> 

Agree this empty API is not needed.
It's a limitation with the framework and this needs to fixed in the fpga_manager core.
Will address this generic issue in a different series.
 
> > +
> > +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> > +				 const char *buf, size_t size)
> > +{
> > +	struct versal_fpga_priv *priv;
> > +	dma_addr_t dma_addr = 0;
> > +	char *kbuf;
> > +	int ret;
> > +
> > +	priv = mgr->priv;
> > +
> > +	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> GFP_KERNEL);
> > +	if (!kbuf)
> > +		return -ENOMEM;
> > +
> > +	memcpy(kbuf, buf, size);
> > +
> > +	wmb(); /* ensure all writes are done before initiate FW call */
> 
> What "writes"?  The memcpy above?  Are you _SURE_ that really is correct
> here?  This feels wrong.
> 

Will fix in v7.

> > +
> > +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
> 
> If this needs some sort of barrier, shouldn't it be in this call?
> 

Will fix in v7.

> > +
> > +	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> > +
> > +	return ret;
> > +}
> > +
> > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> > +					  struct fpga_image_info *info)
> > +{
> > +	return 0;
> > +}
> 
> Again, why have it if it does nothing?
> 

Same as above.

> > +
> > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager
> > +*mgr) {
> > +	return FPGA_MGR_STATE_UNKNOWN;
> > +}
> 
> Again, is this needed?  If so, then the fpga_manager core needs to be fixed
> up :)
>

Same as above.

> > +static const struct fpga_manager_ops versal_fpga_ops = {
> > +	.state = versal_fpga_ops_state,
> > +	.write_init = versal_fpga_ops_write_init,
> > +	.write = versal_fpga_ops_write,
> > +	.write_complete = versal_fpga_ops_write_complete, };
> > +
> > +static int versal_fpga_probe(struct platform_device *pdev) {
> > +	struct device *dev = &pdev->dev;
> > +	struct versal_fpga_priv *priv;
> > +	struct fpga_manager *mgr;
> > +	int ret;
> > +
> > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +
> > +	priv->dev = dev;
> 
> You save a pointer to a reference counted structure, without incrementing
> the reference count.  What could go wrong?  :)
> 
> You are getting lucky here, but as stated above, why do you need this
> pointer?
> 

Will fix in v7.

Regards,
Navakishore.

RE: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Nava kishore Manne]

Hi Greg,

	Thanks for providing the review comments.
Please find my response inline.

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, May 20, 2021 2:19 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: robh+dt@kernel.org; Michal Simek <michals@xilinx.com>;
> mdf@kernel.org; trix@redhat.com; arnd@arndb.de; Rajan Vaja
> <RAJANV@xilinx.com>; Amit Sunil Dhamne <amitsuni@xlnx.xilinx.com>;
> Tejas Patel <tejasp@xlnx.xilinx.com>; zou_wei@huawei.com; Sai Krishna
> Potthuri <lakshmis@xilinx.com>; Ravi Patel <RAVIPATE@xilinx.com>;
> iwamatsu@nigauri.org; Jiaying Liang <jliang@xilinx.com>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org; git <git@xilinx.com>;
> chinnikishore369@gmail.com; Appana Durga Kedareswara Rao
> <appanad@xilinx.com>
> Subject: Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver
> 
> On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote:
> > Add support for Xilinx Versal FPGA manager.
> >
> > PDI source type can be DDR, OCM, QSPI flash etc..
> > But driver allocates memory always from DDR, Since driver supports
> > only DDR source type.
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> > <appana.durga.rao@xilinx.com>
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > Reviewed-by: Moritz Fischer <mdf@kernel.org>
> > ---
> > Changes for v2:
> >                 -Updated the Fpga Mgr registrations call's
> >                  to 5.11
> >                 -Fixed some minor coding issues as suggested by
> >                  Moritz.
> > Changes for v3:
> >                 -Rewritten the Versal fpga Kconfig contents.
> > Changes for v4:
> >                 -Rebased the changes on linux-next.
> >                  No functional changes.
> > Changes for v5:
> >                 -None.
> > Changes for v6:
> >                 -None.
> >
> >  drivers/fpga/Kconfig       |   9 +++
> >  drivers/fpga/Makefile      |   1 +
> >  drivers/fpga/versal-fpga.c | 117
> > +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 127 insertions(+)
> >  create mode 100644 drivers/fpga/versal-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 33e15058d0dc..92c20b92357a 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> >  	  to configure the programmable logic(PL) through PS
> >  	  on ZynqMP SoC.
> >
> > +config FPGA_MGR_VERSAL_FPGA
> > +	tristate "Xilinx Versal FPGA"
> > +	depends on ARCH_ZYNQMP || COMPILE_TEST
> > +	help
> > +	  Select this option to enable FPGA manager driver support for
> > +	  Xilinx Versal SoC. This driver uses the firmware interface to
> > +	  configure the programmable logic(PL).
> > +
> > +	  To compile this as a module, choose M here.
> >  endif # FPGA
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 18dc9885883a..0bff783d1b61 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+=
> ts73xx-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> > new file mode 100644 index 000000000000..5744e44f981d
> > --- /dev/null
> > +++ b/drivers/fpga/versal-fpga.c
> > @@ -0,0 +1,117 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2019-2021 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +/**
> > + * struct versal_fpga_priv - Private data structure
> > + * @dev:	Device data structure
> > + */
> > +struct versal_fpga_priv {
> > +	struct device *dev;
> > +};
> 
> Don't you have this pointer already?  What device is this exactly and why
> does it differ from the structure it currently lives in?
> 
Agree, this struct is not needed.
Will fix this issue in v7.

> > +
> > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> > +				      struct fpga_image_info *info,
> > +				      const char *buf, size_t size) {
> > +	return 0;
> > +}
> 
> If you don't need this, why include it?
> 

Agree this empty API is not needed.
It's a limitation with the framework and this needs to fixed in the fpga_manager core.
Will address this generic issue in a different series.
 
> > +
> > +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> > +				 const char *buf, size_t size)
> > +{
> > +	struct versal_fpga_priv *priv;
> > +	dma_addr_t dma_addr = 0;
> > +	char *kbuf;
> > +	int ret;
> > +
> > +	priv = mgr->priv;
> > +
> > +	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> GFP_KERNEL);
> > +	if (!kbuf)
> > +		return -ENOMEM;
> > +
> > +	memcpy(kbuf, buf, size);
> > +
> > +	wmb(); /* ensure all writes are done before initiate FW call */
> 
> What "writes"?  The memcpy above?  Are you _SURE_ that really is correct
> here?  This feels wrong.
> 

Will fix in v7.

> > +
> > +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
> 
> If this needs some sort of barrier, shouldn't it be in this call?
> 

Will fix in v7.

> > +
> > +	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> > +
> > +	return ret;
> > +}
> > +
> > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> > +					  struct fpga_image_info *info)
> > +{
> > +	return 0;
> > +}
> 
> Again, why have it if it does nothing?
> 

Same as above.

> > +
> > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager
> > +*mgr) {
> > +	return FPGA_MGR_STATE_UNKNOWN;
> > +}
> 
> Again, is this needed?  If so, then the fpga_manager core needs to be fixed
> up :)
>

Same as above.

> > +static const struct fpga_manager_ops versal_fpga_ops = {
> > +	.state = versal_fpga_ops_state,
> > +	.write_init = versal_fpga_ops_write_init,
> > +	.write = versal_fpga_ops_write,
> > +	.write_complete = versal_fpga_ops_write_complete, };
> > +
> > +static int versal_fpga_probe(struct platform_device *pdev) {
> > +	struct device *dev = &pdev->dev;
> > +	struct versal_fpga_priv *priv;
> > +	struct fpga_manager *mgr;
> > +	int ret;
> > +
> > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +
> > +	priv->dev = dev;
> 
> You save a pointer to a reference counted structure, without incrementing
> the reference count.  What could go wrong?  :)
> 
> You are getting lucky here, but as stated above, why do you need this
> pointer?
> 

Will fix in v7.

Regards,
Navakishore.

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Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Moritz Fischer]

On Tue, Jun 01, 2021 at 06:56:32AM +0000, Nava kishore Manne wrote:
> Hi Greg,
> 
> 	Thanks for providing the review comments.
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Greg KH <gregkh@linuxfoundation.org>
> > Sent: Thursday, May 20, 2021 2:19 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: robh+dt@kernel.org; Michal Simek <michals@xilinx.com>;
> > mdf@kernel.org; trix@redhat.com; arnd@arndb.de; Rajan Vaja
> > <RAJANV@xilinx.com>; Amit Sunil Dhamne <amitsuni@xlnx.xilinx.com>;
> > Tejas Patel <tejasp@xlnx.xilinx.com>; zou_wei@huawei.com; Sai Krishna
> > Potthuri <lakshmis@xilinx.com>; Ravi Patel <RAVIPATE@xilinx.com>;
> > iwamatsu@nigauri.org; Jiaying Liang <jliang@xilinx.com>;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-fpga@vger.kernel.org; git <git@xilinx.com>;
> > chinnikishore369@gmail.com; Appana Durga Kedareswara Rao
> > <appanad@xilinx.com>
> > Subject: Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver
> > 
> > On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote:
> > > Add support for Xilinx Versal FPGA manager.
> > >
> > > PDI source type can be DDR, OCM, QSPI flash etc..
> > > But driver allocates memory always from DDR, Since driver supports
> > > only DDR source type.
> > >
> > > Signed-off-by: Appana Durga Kedareswara rao
> > > <appana.durga.rao@xilinx.com>
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > Reviewed-by: Moritz Fischer <mdf@kernel.org>
> > > ---
> > > Changes for v2:
> > >                 -Updated the Fpga Mgr registrations call's
> > >                  to 5.11
> > >                 -Fixed some minor coding issues as suggested by
> > >                  Moritz.
> > > Changes for v3:
> > >                 -Rewritten the Versal fpga Kconfig contents.
> > > Changes for v4:
> > >                 -Rebased the changes on linux-next.
> > >                  No functional changes.
> > > Changes for v5:
> > >                 -None.
> > > Changes for v6:
> > >                 -None.
> > >
> > >  drivers/fpga/Kconfig       |   9 +++
> > >  drivers/fpga/Makefile      |   1 +
> > >  drivers/fpga/versal-fpga.c | 117
> > > +++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 127 insertions(+)
> > >  create mode 100644 drivers/fpga/versal-fpga.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > 33e15058d0dc..92c20b92357a 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> > >  	  to configure the programmable logic(PL) through PS
> > >  	  on ZynqMP SoC.
> > >
> > > +config FPGA_MGR_VERSAL_FPGA
> > > +	tristate "Xilinx Versal FPGA"
> > > +	depends on ARCH_ZYNQMP || COMPILE_TEST
> > > +	help
> > > +	  Select this option to enable FPGA manager driver support for
> > > +	  Xilinx Versal SoC. This driver uses the firmware interface to
> > > +	  configure the programmable logic(PL).
> > > +
> > > +	  To compile this as a module, choose M here.
> > >  endif # FPGA
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > 18dc9885883a..0bff783d1b61 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+=
> > ts73xx-fpga.o
> > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
> > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
> > >  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> > > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > >
> > > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> > > new file mode 100644 index 000000000000..5744e44f981d
> > > --- /dev/null
> > > +++ b/drivers/fpga/versal-fpga.c
> > > @@ -0,0 +1,117 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2019-2021 Xilinx, Inc.
> > > + */
> > > +
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/fpga/fpga-mgr.h>
> > > +#include <linux/io.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/string.h>
> > > +#include <linux/firmware/xlnx-zynqmp.h>
> > > +
> > > +/**
> > > + * struct versal_fpga_priv - Private data structure
> > > + * @dev:	Device data structure
> > > + */
> > > +struct versal_fpga_priv {
> > > +	struct device *dev;
> > > +};
> > 
> > Don't you have this pointer already?  What device is this exactly and why
> > does it differ from the structure it currently lives in?
> > 
> Agree, this struct is not needed.
> Will fix this issue in v7.
> 
> > > +
> > > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> > > +				      struct fpga_image_info *info,
> > > +				      const char *buf, size_t size) {
> > > +	return 0;
> > > +}
> > 
> > If you don't need this, why include it?
> > 
> 
> Agree this empty API is not needed.
> It's a limitation with the framework and this needs to fixed in the fpga_manager core.
> Will address this generic issue in a different series.

I was working on a series to clean this up anyways :)
>  
> > > +
> > > +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> > > +				 const char *buf, size_t size)
> > > +{
> > > +	struct versal_fpga_priv *priv;
> > > +	dma_addr_t dma_addr = 0;
> > > +	char *kbuf;
> > > +	int ret;
> > > +
> > > +	priv = mgr->priv;
> > > +
> > > +	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> > GFP_KERNEL);
> > > +	if (!kbuf)
> > > +		return -ENOMEM;
> > > +
> > > +	memcpy(kbuf, buf, size);
> > > +
> > > +	wmb(); /* ensure all writes are done before initiate FW call */
> > 
> > What "writes"?  The memcpy above?  Are you _SURE_ that really is correct
> > here?  This feels wrong.
> > 
> 
> Will fix in v7.
> 
> > > +
> > > +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
> > 
> > If this needs some sort of barrier, shouldn't it be in this call?
> > 
> 
> Will fix in v7.
> 
> > > +
> > > +	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> > > +					  struct fpga_image_info *info)
> > > +{
> > > +	return 0;
> > > +}
> > 
> > Again, why have it if it does nothing?
> > 
> 
> Same as above.
> 
> > > +
> > > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager
> > > +*mgr) {
> > > +	return FPGA_MGR_STATE_UNKNOWN;
> > > +}
> > 
> > Again, is this needed?  If so, then the fpga_manager core needs to be fixed
> > up :)
> >
> 
> Same as above.
> 
> > > +static const struct fpga_manager_ops versal_fpga_ops = {
> > > +	.state = versal_fpga_ops_state,
> > > +	.write_init = versal_fpga_ops_write_init,
> > > +	.write = versal_fpga_ops_write,
> > > +	.write_complete = versal_fpga_ops_write_complete, };
> > > +
> > > +static int versal_fpga_probe(struct platform_device *pdev) {
> > > +	struct device *dev = &pdev->dev;
> > > +	struct versal_fpga_priv *priv;
> > > +	struct fpga_manager *mgr;
> > > +	int ret;
> > > +
> > > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > > +	if (!priv)
> > > +		return -ENOMEM;
> > > +
> > > +	priv->dev = dev;
> > 
> > You save a pointer to a reference counted structure, without incrementing
> > the reference count.  What could go wrong?  :)
> > 
> > You are getting lucky here, but as stated above, why do you need this
> > pointer?
> > 
> 
> Will fix in v7.
> 
> Regards,
> Navakishore.

- Moritz

Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver

[Moritz Fischer]

On Tue, Jun 01, 2021 at 06:56:32AM +0000, Nava kishore Manne wrote:
> Hi Greg,
> 
> 	Thanks for providing the review comments.
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Greg KH <gregkh@linuxfoundation.org>
> > Sent: Thursday, May 20, 2021 2:19 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: robh+dt@kernel.org; Michal Simek <michals@xilinx.com>;
> > mdf@kernel.org; trix@redhat.com; arnd@arndb.de; Rajan Vaja
> > <RAJANV@xilinx.com>; Amit Sunil Dhamne <amitsuni@xlnx.xilinx.com>;
> > Tejas Patel <tejasp@xlnx.xilinx.com>; zou_wei@huawei.com; Sai Krishna
> > Potthuri <lakshmis@xilinx.com>; Ravi Patel <RAVIPATE@xilinx.com>;
> > iwamatsu@nigauri.org; Jiaying Liang <jliang@xilinx.com>;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-fpga@vger.kernel.org; git <git@xilinx.com>;
> > chinnikishore369@gmail.com; Appana Durga Kedareswara Rao
> > <appanad@xilinx.com>
> > Subject: Re: [PATCH v6 4/4] fpga: versal-fpga: Add versal fpga manager driver
> > 
> > On Thu, May 20, 2021 at 01:39:54PM +0530, Nava kishore Manne wrote:
> > > Add support for Xilinx Versal FPGA manager.
> > >
> > > PDI source type can be DDR, OCM, QSPI flash etc..
> > > But driver allocates memory always from DDR, Since driver supports
> > > only DDR source type.
> > >
> > > Signed-off-by: Appana Durga Kedareswara rao
> > > <appana.durga.rao@xilinx.com>
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > Reviewed-by: Moritz Fischer <mdf@kernel.org>
> > > ---
> > > Changes for v2:
> > >                 -Updated the Fpga Mgr registrations call's
> > >                  to 5.11
> > >                 -Fixed some minor coding issues as suggested by
> > >                  Moritz.
> > > Changes for v3:
> > >                 -Rewritten the Versal fpga Kconfig contents.
> > > Changes for v4:
> > >                 -Rebased the changes on linux-next.
> > >                  No functional changes.
> > > Changes for v5:
> > >                 -None.
> > > Changes for v6:
> > >                 -None.
> > >
> > >  drivers/fpga/Kconfig       |   9 +++
> > >  drivers/fpga/Makefile      |   1 +
> > >  drivers/fpga/versal-fpga.c | 117
> > > +++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 127 insertions(+)
> > >  create mode 100644 drivers/fpga/versal-fpga.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > 33e15058d0dc..92c20b92357a 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> > >  	  to configure the programmable logic(PL) through PS
> > >  	  on ZynqMP SoC.
> > >
> > > +config FPGA_MGR_VERSAL_FPGA
> > > +	tristate "Xilinx Versal FPGA"
> > > +	depends on ARCH_ZYNQMP || COMPILE_TEST
> > > +	help
> > > +	  Select this option to enable FPGA manager driver support for
> > > +	  Xilinx Versal SoC. This driver uses the firmware interface to
> > > +	  configure the programmable logic(PL).
> > > +
> > > +	  To compile this as a module, choose M here.
> > >  endif # FPGA
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > 18dc9885883a..0bff783d1b61 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+=
> > ts73xx-fpga.o
> > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
> > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
> > >  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
> > > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)      += versal-fpga.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > >
> > > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> > > new file mode 100644 index 000000000000..5744e44f981d
> > > --- /dev/null
> > > +++ b/drivers/fpga/versal-fpga.c
> > > @@ -0,0 +1,117 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2019-2021 Xilinx, Inc.
> > > + */
> > > +
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/fpga/fpga-mgr.h>
> > > +#include <linux/io.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/string.h>
> > > +#include <linux/firmware/xlnx-zynqmp.h>
> > > +
> > > +/**
> > > + * struct versal_fpga_priv - Private data structure
> > > + * @dev:	Device data structure
> > > + */
> > > +struct versal_fpga_priv {
> > > +	struct device *dev;
> > > +};
> > 
> > Don't you have this pointer already?  What device is this exactly and why
> > does it differ from the structure it currently lives in?
> > 
> Agree, this struct is not needed.
> Will fix this issue in v7.
> 
> > > +
> > > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> > > +				      struct fpga_image_info *info,
> > > +				      const char *buf, size_t size) {
> > > +	return 0;
> > > +}
> > 
> > If you don't need this, why include it?
> > 
> 
> Agree this empty API is not needed.
> It's a limitation with the framework and this needs to fixed in the fpga_manager core.
> Will address this generic issue in a different series.

I was working on a series to clean this up anyways :)
>  
> > > +
> > > +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> > > +				 const char *buf, size_t size)
> > > +{
> > > +	struct versal_fpga_priv *priv;
> > > +	dma_addr_t dma_addr = 0;
> > > +	char *kbuf;
> > > +	int ret;
> > > +
> > > +	priv = mgr->priv;
> > > +
> > > +	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> > GFP_KERNEL);
> > > +	if (!kbuf)
> > > +		return -ENOMEM;
> > > +
> > > +	memcpy(kbuf, buf, size);
> > > +
> > > +	wmb(); /* ensure all writes are done before initiate FW call */
> > 
> > What "writes"?  The memcpy above?  Are you _SURE_ that really is correct
> > here?  This feels wrong.
> > 
> 
> Will fix in v7.
> 
> > > +
> > > +	ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
> > 
> > If this needs some sort of barrier, shouldn't it be in this call?
> > 
> 
> Will fix in v7.
> 
> > > +
> > > +	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> > > +					  struct fpga_image_info *info)
> > > +{
> > > +	return 0;
> > > +}
> > 
> > Again, why have it if it does nothing?
> > 
> 
> Same as above.
> 
> > > +
> > > +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager
> > > +*mgr) {
> > > +	return FPGA_MGR_STATE_UNKNOWN;
> > > +}
> > 
> > Again, is this needed?  If so, then the fpga_manager core needs to be fixed
> > up :)
> >
> 
> Same as above.
> 
> > > +static const struct fpga_manager_ops versal_fpga_ops = {
> > > +	.state = versal_fpga_ops_state,
> > > +	.write_init = versal_fpga_ops_write_init,
> > > +	.write = versal_fpga_ops_write,
> > > +	.write_complete = versal_fpga_ops_write_complete, };
> > > +
> > > +static int versal_fpga_probe(struct platform_device *pdev) {
> > > +	struct device *dev = &pdev->dev;
> > > +	struct versal_fpga_priv *priv;
> > > +	struct fpga_manager *mgr;
> > > +	int ret;
> > > +
> > > +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > > +	if (!priv)
> > > +		return -ENOMEM;
> > > +
> > > +	priv->dev = dev;
> > 
> > You save a pointer to a reference counted structure, without incrementing
> > the reference count.  What could go wrong?  :)
> > 
> > You are getting lucky here, but as stated above, why do you need this
> > pointer?
> > 
> 
> Will fix in v7.
> 
> Regards,
> Navakishore.

- Moritz

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