From: Pratyush Yadav <p.yadav@ti.com> To: Michael Walle <michael@walle.cc> Cc: <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Tudor Ambarus <tudor.ambarus@microchip.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com> Subject: Re: [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security registers in 4 byte mode Date: Thu, 20 May 2021 23:10:47 +0530 [thread overview] Message-ID: <20210520174045.sxbffwia7mec24rt@ti.com> (raw) In-Reply-To: <20210520155854.16547-2-michael@walle.cc> On 20/05/21 05:58PM, Michael Walle wrote: > The security registers either take a 3 byte or a 4 byte address offset, > depending on the address mode of the flash. Thus just leave the > nor->addr_width as is. > > Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes") > Signed-off-by: Michael Walle <michael@walle.cc> I have not done due diligence in researching this topic. But the premise sounds good to me. So, Acked-by: Pratyush Yadav <p.yadav@ti.com> > --- > drivers/mtd/spi-nor/otp.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c > index 61036c716abb..91a4c510ed51 100644 > --- a/drivers/mtd/spi-nor/otp.c > +++ b/drivers/mtd/spi-nor/otp.c > @@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf) > rdesc = nor->dirmap.rdesc; > > nor->read_opcode = SPINOR_OP_RSECR; > - nor->addr_width = 3; > nor->read_dummy = 8; > nor->read_proto = SNOR_PROTO_1_1_1; > nor->dirmap.rdesc = NULL; > @@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len, > wdesc = nor->dirmap.wdesc; > > nor->program_opcode = SPINOR_OP_PSECR; > - nor->addr_width = 3; > nor->write_proto = SNOR_PROTO_1_1_1; > nor->dirmap.wdesc = NULL; > > -- > 2.20.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.
WARNING: multiple messages have this Message-ID (diff)
From: Pratyush Yadav <p.yadav@ti.com> To: Michael Walle <michael@walle.cc> Cc: <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Tudor Ambarus <tudor.ambarus@microchip.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com> Subject: Re: [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security registers in 4 byte mode Date: Thu, 20 May 2021 23:10:47 +0530 [thread overview] Message-ID: <20210520174045.sxbffwia7mec24rt@ti.com> (raw) In-Reply-To: <20210520155854.16547-2-michael@walle.cc> On 20/05/21 05:58PM, Michael Walle wrote: > The security registers either take a 3 byte or a 4 byte address offset, > depending on the address mode of the flash. Thus just leave the > nor->addr_width as is. > > Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes") > Signed-off-by: Michael Walle <michael@walle.cc> I have not done due diligence in researching this topic. But the premise sounds good to me. So, Acked-by: Pratyush Yadav <p.yadav@ti.com> > --- > drivers/mtd/spi-nor/otp.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c > index 61036c716abb..91a4c510ed51 100644 > --- a/drivers/mtd/spi-nor/otp.c > +++ b/drivers/mtd/spi-nor/otp.c > @@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf) > rdesc = nor->dirmap.rdesc; > > nor->read_opcode = SPINOR_OP_RSECR; > - nor->addr_width = 3; > nor->read_dummy = 8; > nor->read_proto = SNOR_PROTO_1_1_1; > nor->dirmap.rdesc = NULL; > @@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len, > wdesc = nor->dirmap.wdesc; > > nor->program_opcode = SPINOR_OP_PSECR; > - nor->addr_width = 3; > nor->write_proto = SNOR_PROTO_1_1_1; > nor->dirmap.wdesc = NULL; > > -- > 2.20.1 > -- Regards, Pratyush Yadav Texas Instruments Inc. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-05-20 17:41 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-20 15:58 [PATCH v3 0/3] mtd: spi-nor: otp: 4 byte mode fix and erase support Michael Walle 2021-05-20 15:58 ` Michael Walle 2021-05-20 15:58 ` [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security registers in 4 byte mode Michael Walle 2021-05-20 15:58 ` Michael Walle 2021-05-20 17:40 ` Pratyush Yadav [this message] 2021-05-20 17:40 ` Pratyush Yadav 2021-05-31 8:00 ` Tudor.Ambarus 2021-05-31 8:00 ` Tudor.Ambarus 2021-05-31 8:07 ` Tudor.Ambarus 2021-05-31 8:07 ` Tudor.Ambarus 2021-05-20 15:58 ` [PATCH v3 2/3] mtd: spi-nor: otp: use more consistent wording Michael Walle 2021-05-20 15:58 ` Michael Walle 2021-05-20 17:39 ` Pratyush Yadav 2021-05-20 17:39 ` Pratyush Yadav 2021-05-20 19:48 ` Michael Walle 2021-05-20 19:48 ` Michael Walle 2021-05-31 8:12 ` Tudor.Ambarus 2021-05-31 8:12 ` Tudor.Ambarus 2021-05-20 15:58 ` [PATCH v3 3/3] mtd: spi-nor: otp: implement erase for Winbond and similar flashes Michael Walle 2021-05-20 15:58 ` Michael Walle 2021-05-20 17:51 ` Pratyush Yadav 2021-05-20 17:51 ` Pratyush Yadav 2021-05-20 19:42 ` Michael Walle 2021-05-20 19:42 ` Michael Walle
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