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From: <Tudor.Ambarus@microchip.com>
To: <michael@walle.cc>, <linux-mtd@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <p.yadav@ti.com>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
	<vigneshr@ti.com>
Subject: Re: [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security registers in 4 byte mode
Date: Mon, 31 May 2021 08:07:30 +0000	[thread overview]
Message-ID: <5b0a7c0d-734d-2e29-9d71-2230e7748d04@microchip.com> (raw)
In-Reply-To: <0cd72191-e195-eae3-f741-a3c3e38298cc@microchip.com>

On 5/31/21 11:00 AM, Tudor Ambarus - M18064 wrote:
> On 5/20/21 6:58 PM, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The security registers either take a 3 byte or a 4 byte address offset,
>> depending on the address mode of the flash. Thus just leave the
>> nor->addr_width as is.
>>
>> Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes")
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>>  drivers/mtd/spi-nor/otp.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
>> index 61036c716abb..91a4c510ed51 100644
>> --- a/drivers/mtd/spi-nor/otp.c
>> +++ b/drivers/mtd/spi-nor/otp.c
>> @@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf)
>>         rdesc = nor->dirmap.rdesc;
>>
>>         nor->read_opcode = SPINOR_OP_RSECR;
>> -       nor->addr_width = 3;
>>         nor->read_dummy = 8;
>>         nor->read_proto = SNOR_PROTO_1_1_1;
>>         nor->dirmap.rdesc = NULL;
>> @@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
>>         wdesc = nor->dirmap.wdesc;
>>
>>         nor->program_opcode = SPINOR_OP_PSECR;
>> -       nor->addr_width = 3;
>>         nor->write_proto = SNOR_PROTO_1_1_1;
>>         nor->dirmap.wdesc = NULL;
>>
> 
> I'm not convinced that this is good. I see that winbond uses 3 bytes addr with for the
> SPINOR_OP_RSECR and SPINOR_OP_PSECR, even for bigger flashes:
> https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25Q256JW
> 
> Micheal, can you double check?
> 

Doubled checked with Michael, looks good:

Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>



WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com>
To: <michael@walle.cc>, <linux-mtd@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <p.yadav@ti.com>, <miquel.raynal@bootlin.com>, <richard@nod.at>,
	<vigneshr@ti.com>
Subject: Re: [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security registers in 4 byte mode
Date: Mon, 31 May 2021 08:07:30 +0000	[thread overview]
Message-ID: <5b0a7c0d-734d-2e29-9d71-2230e7748d04@microchip.com> (raw)
In-Reply-To: <0cd72191-e195-eae3-f741-a3c3e38298cc@microchip.com>

On 5/31/21 11:00 AM, Tudor Ambarus - M18064 wrote:
> On 5/20/21 6:58 PM, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The security registers either take a 3 byte or a 4 byte address offset,
>> depending on the address mode of the flash. Thus just leave the
>> nor->addr_width as is.
>>
>> Fixes: cad3193fe9d1 ("mtd: spi-nor: implement OTP support for Winbond and similar flashes")
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>>  drivers/mtd/spi-nor/otp.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
>> index 61036c716abb..91a4c510ed51 100644
>> --- a/drivers/mtd/spi-nor/otp.c
>> +++ b/drivers/mtd/spi-nor/otp.c
>> @@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf)
>>         rdesc = nor->dirmap.rdesc;
>>
>>         nor->read_opcode = SPINOR_OP_RSECR;
>> -       nor->addr_width = 3;
>>         nor->read_dummy = 8;
>>         nor->read_proto = SNOR_PROTO_1_1_1;
>>         nor->dirmap.rdesc = NULL;
>> @@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
>>         wdesc = nor->dirmap.wdesc;
>>
>>         nor->program_opcode = SPINOR_OP_PSECR;
>> -       nor->addr_width = 3;
>>         nor->write_proto = SNOR_PROTO_1_1_1;
>>         nor->dirmap.wdesc = NULL;
>>
> 
> I'm not convinced that this is good. I see that winbond uses 3 bytes addr with for the
> SPINOR_OP_RSECR and SPINOR_OP_PSECR, even for bigger flashes:
> https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25Q256JW
> 
> Micheal, can you double check?
> 

Doubled checked with Michael, looks good:

Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>


______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/

  reply	other threads:[~2021-05-31  8:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-20 15:58 [PATCH v3 0/3] mtd: spi-nor: otp: 4 byte mode fix and erase support Michael Walle
2021-05-20 15:58 ` Michael Walle
2021-05-20 15:58 ` [PATCH v3 1/3] mtd: spi-nor: otp: fix access to security registers in 4 byte mode Michael Walle
2021-05-20 15:58   ` Michael Walle
2021-05-20 17:40   ` Pratyush Yadav
2021-05-20 17:40     ` Pratyush Yadav
2021-05-31  8:00   ` Tudor.Ambarus
2021-05-31  8:00     ` Tudor.Ambarus
2021-05-31  8:07     ` Tudor.Ambarus [this message]
2021-05-31  8:07       ` Tudor.Ambarus
2021-05-20 15:58 ` [PATCH v3 2/3] mtd: spi-nor: otp: use more consistent wording Michael Walle
2021-05-20 15:58   ` Michael Walle
2021-05-20 17:39   ` Pratyush Yadav
2021-05-20 17:39     ` Pratyush Yadav
2021-05-20 19:48     ` Michael Walle
2021-05-20 19:48       ` Michael Walle
2021-05-31  8:12   ` Tudor.Ambarus
2021-05-31  8:12     ` Tudor.Ambarus
2021-05-20 15:58 ` [PATCH v3 3/3] mtd: spi-nor: otp: implement erase for Winbond and similar flashes Michael Walle
2021-05-20 15:58   ` Michael Walle
2021-05-20 17:51   ` Pratyush Yadav
2021-05-20 17:51     ` Pratyush Yadav
2021-05-20 19:42     ` Michael Walle
2021-05-20 19:42       ` Michael Walle

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