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From: Vinod Koul <vkoul@kernel.org>
To: Rob Clark <robdclark@gmail.com>
Cc: linux-arm-msm@vger.kernel.org,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Vinod Koul <vkoul@kernel.org>, David Airlie <airlied@linux.ie>,
	Daniel Vetter <daniel@ffwll.ch>,
	Jonathan Marek <jonathan@marek.ca>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Abhinav Kumar <abhinavk@codeaurora.org>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org
Subject: [RFC PATCH 06/13] drm/msm/disp/dpu1: Add DSC support in RM
Date: Fri, 21 May 2021 18:19:38 +0530	[thread overview]
Message-ID: <20210521124946.3617862-10-vkoul@kernel.org> (raw)
In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org>

This add the bits in RM to enable the DSC blocks

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 32 +++++++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  |  1 +
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index d6717d6672f7..d56c05146dfe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -165,6 +165,7 @@ struct dpu_global_state {
 	uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
 	uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
 	uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
+	uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
 };
 
 struct dpu_global_state
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index fd2d104f0a91..4da6d72b7996 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -11,6 +11,7 @@
 #include "dpu_hw_intf.h"
 #include "dpu_hw_dspp.h"
 #include "dpu_hw_merge3d.h"
+#include "dpu_hw_dsc.h"
 #include "dpu_encoder.h"
 #include "dpu_trace.h"
 
@@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 			dpu_hw_intf_destroy(hw);
 		}
 	}
+	for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
+		struct dpu_hw_dsc *hw;
+
+		if (rm->intf_blks[i]) {
+			hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
+			dpu_hw_dsc_destroy(hw);
+		}
+	}
 
 	return 0;
 }
@@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
 		rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
 	}
 
+	for (i = 0; i < cat->dsc_count; i++) {
+		struct dpu_hw_dsc *hw;
+		const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
+
+		hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
+		if (IS_ERR_OR_NULL(hw)) {
+			rc = PTR_ERR(hw);
+			DPU_ERROR("failed dsc object creation: err %d\n", rc);
+			goto fail;
+		}
+		rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
+	}
+
 	return 0;
 
 fail:
@@ -476,6 +498,9 @@ static int _dpu_rm_reserve_intf(
 	}
 
 	global_state->intf_to_enc_id[idx] = enc_id;
+
+	global_state->dsc_to_enc_id[0] = enc_id;
+	global_state->dsc_to_enc_id[1] = enc_id;
 	return 0;
 }
 
@@ -567,6 +592,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
 		ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
 	_dpu_rm_clear_mapping(global_state->intf_to_enc_id,
 		ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
+	_dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
+		ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
 }
 
 int dpu_rm_reserve(
@@ -640,6 +667,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
 		hw_to_enc_id = global_state->dspp_to_enc_id;
 		max_blks = ARRAY_SIZE(rm->dspp_blks);
 		break;
+	case DPU_HW_BLK_DSC:
+		hw_blks = rm->dsc_blks;
+		hw_to_enc_id = global_state->dsc_to_enc_id;
+		max_blks = ARRAY_SIZE(rm->dsc_blks);
+		break;
 	default:
 		DPU_ERROR("blk type %d not managed by rm\n", type);
 		return 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 1f12c8d5b8aa..278d2a510b80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -30,6 +30,7 @@ struct dpu_rm {
 	struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
 	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
+	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
 
 	uint32_t lm_max_width;
 };
-- 
2.26.3


WARNING: multiple messages have this Message-ID
From: Vinod Koul <vkoul@kernel.org>
To: Rob Clark <robdclark@gmail.com>
Cc: Jonathan Marek <jonathan@marek.ca>,
	David Airlie <airlied@linux.ie>,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Abhinav Kumar <abhinavk@codeaurora.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Vinod Koul <vkoul@kernel.org>,
	dri-devel@lists.freedesktop.org,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	freedreno@lists.freedesktop.org
Subject: [RFC PATCH 06/13] drm/msm/disp/dpu1: Add DSC support in RM
Date: Fri, 21 May 2021 18:19:38 +0530	[thread overview]
Message-ID: <20210521124946.3617862-10-vkoul@kernel.org> (raw)
In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org>

This add the bits in RM to enable the DSC blocks

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 32 +++++++++++++++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  |  1 +
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index d6717d6672f7..d56c05146dfe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -165,6 +165,7 @@ struct dpu_global_state {
 	uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
 	uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
 	uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
+	uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
 };
 
 struct dpu_global_state
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index fd2d104f0a91..4da6d72b7996 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -11,6 +11,7 @@
 #include "dpu_hw_intf.h"
 #include "dpu_hw_dspp.h"
 #include "dpu_hw_merge3d.h"
+#include "dpu_hw_dsc.h"
 #include "dpu_encoder.h"
 #include "dpu_trace.h"
 
@@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 			dpu_hw_intf_destroy(hw);
 		}
 	}
+	for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
+		struct dpu_hw_dsc *hw;
+
+		if (rm->intf_blks[i]) {
+			hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
+			dpu_hw_dsc_destroy(hw);
+		}
+	}
 
 	return 0;
 }
@@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
 		rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
 	}
 
+	for (i = 0; i < cat->dsc_count; i++) {
+		struct dpu_hw_dsc *hw;
+		const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
+
+		hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
+		if (IS_ERR_OR_NULL(hw)) {
+			rc = PTR_ERR(hw);
+			DPU_ERROR("failed dsc object creation: err %d\n", rc);
+			goto fail;
+		}
+		rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
+	}
+
 	return 0;
 
 fail:
@@ -476,6 +498,9 @@ static int _dpu_rm_reserve_intf(
 	}
 
 	global_state->intf_to_enc_id[idx] = enc_id;
+
+	global_state->dsc_to_enc_id[0] = enc_id;
+	global_state->dsc_to_enc_id[1] = enc_id;
 	return 0;
 }
 
@@ -567,6 +592,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
 		ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
 	_dpu_rm_clear_mapping(global_state->intf_to_enc_id,
 		ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
+	_dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
+		ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
 }
 
 int dpu_rm_reserve(
@@ -640,6 +667,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
 		hw_to_enc_id = global_state->dspp_to_enc_id;
 		max_blks = ARRAY_SIZE(rm->dspp_blks);
 		break;
+	case DPU_HW_BLK_DSC:
+		hw_blks = rm->dsc_blks;
+		hw_to_enc_id = global_state->dsc_to_enc_id;
+		max_blks = ARRAY_SIZE(rm->dsc_blks);
+		break;
 	default:
 		DPU_ERROR("blk type %d not managed by rm\n", type);
 		return 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 1f12c8d5b8aa..278d2a510b80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -30,6 +30,7 @@ struct dpu_rm {
 	struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
 	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
+	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
 
 	uint32_t lm_max_width;
 };
-- 
2.26.3


  parent reply	other threads:[~2021-05-21 12:51 UTC|newest]

Thread overview: 91+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-21 12:49 [RFC PATCH 00/13] drm/msm: Add Display Stream Compression Support Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 01/13] drm/dsc: Add dsc pps header init function Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 15:29   ` Daniel Vetter
2021-05-21 15:29     ` Daniel Vetter
2021-05-24  7:26     ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 02/13] dt-bindings: msm/dsi: Document Display Stream Compression (DSC) parameters Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 13:18   ` Rob Herring
2021-05-21 13:18     ` Rob Herring
2021-05-21 13:23     ` Vinod Koul
2021-05-21 13:23       ` Vinod Koul
2021-05-21 14:42   ` Bjorn Andersson
2021-05-21 14:42     ` Bjorn Andersson
2021-05-24  7:30     ` Vinod Koul
2021-05-24  7:30       ` Vinod Koul
2021-05-24 15:08       ` Bjorn Andersson
2021-05-24 15:08         ` Bjorn Andersson
2021-05-26  5:32         ` Vinod Koul
2021-05-26  5:32           ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 03/13] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-27 23:49   ` Dmitry Baryshkov
2021-05-27 23:49     ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 03/13] drm/msm/dsi: add support for dsc data Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-27 23:45   ` Dmitry Baryshkov
2021-05-27 23:45     ` Dmitry Baryshkov
2021-06-02 11:06     ` Vinod Koul
2021-06-02 11:06       ` Vinod Koul
2021-05-28 10:29   ` Dmitry Baryshkov
2021-05-28 10:29     ` Dmitry Baryshkov
2021-06-02 11:17     ` Vinod Koul
2021-06-02 11:17       ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 04/13] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-28 10:31   ` Dmitry Baryshkov
2021-05-28 10:31     ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 05/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 05/13] drm/msm/dsi: add support for dsc data Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` Vinod Koul [this message]
2021-05-21 12:49   ` [RFC PATCH 06/13] drm/msm/disp/dpu1: Add DSC support in RM Vinod Koul
2021-05-28 10:33   ` Dmitry Baryshkov
2021-05-28 10:33     ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 07/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 09/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-28 10:36   ` Dmitry Baryshkov
2021-05-28 10:36     ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 09/13] drm/msm/disp/dpu1: Dont " Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 10/13] drm/msm/disp/dpu1: Add support for DSC in encoder Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 11/13] drm/msm/disp/dpu1: Add support for DSC in topology Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-28 10:39   ` Dmitry Baryshkov
2021-05-28 10:39     ` Dmitry Baryshkov
2021-05-28 22:23     ` abhinavk
2021-05-28 22:23       ` abhinavk
2021-05-28 22:29       ` Dmitry Baryshkov
2021-05-28 22:29         ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 12/13] drm/msm/dsi: Add support for DSC configuration Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 13/13] drm/msm/dsi: Pass DSC params to drm_panel Vinod Koul
2021-05-21 12:49   ` Vinod Koul
2021-05-21 14:09 ` [Freedreno] [RFC PATCH 00/13] drm/msm: Add Display Stream Compression Support Jeffrey Hugo
2021-05-21 14:09   ` Jeffrey Hugo
2021-05-26  5:46   ` Vinod Koul
2021-05-26  5:46     ` Vinod Koul
2021-05-26 15:00     ` Jeffrey Hugo
2021-05-26 15:00       ` Jeffrey Hugo
2021-05-27 23:30       ` Rob Clark
2021-05-27 23:30         ` Rob Clark
2021-06-02 11:01         ` Vinod Koul
2021-06-02 11:01           ` Vinod Koul
2021-06-03 23:40           ` abhinavk
2021-06-03 23:40             ` abhinavk
2021-06-17  8:06             ` Vinod Koul
2021-06-17  8:06               ` Vinod Koul
2021-06-04  2:36           ` Rob Clark
2021-06-04  2:36             ` Rob Clark
2021-06-02 10:56       ` Vinod Koul
2021-06-02 10:56         ` Vinod Koul

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