From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: Frank Chang <frank.chang@sifive.com>,
alistair23@gmail.com, Kito Cheng <kito.cheng@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension
Date: Tue, 8 Jun 2021 10:29:31 +1000 [thread overview]
Message-ID: <20210608002947.1649775-17-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210608002947.1649775-1-alistair.francis@wdc.com>
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8901ba1e1b..f75642bb0d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,7 +23,7 @@
%rd 7:5
%sh5 20:5
-%sh10 20:10
+%sh7 20:7
%csr 20:12
%rm 12:3
%nf 29:3 !function=ex_plus_1
@@ -59,7 +59,7 @@
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
-@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@@ -125,9 +125,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
-slli 00.... ...... ..... 001 ..... 0010011 @sh
-srli 00.... ...... ..... 101 ..... 0010011 @sh
-srai 01.... ...... ..... 101 ..... 0010011 @sh
+slli 00000. ...... ..... 001 ..... 0010011 @sh
+srli 00000. ...... ..... 101 ..... 0010011 @sh
+srai 01000. ...... ..... 101 ..... 0010011 @sh
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
--
2.31.1
next prev parent reply other threads:[~2021-06-08 0:41 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-08 0:29 [PULL 00/32] riscv-to-apply queue Alistair Francis
2021-06-08 0:29 ` [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Alistair Francis
2021-06-08 0:29 ` [PULL 02/32] hw/riscv: virt: " Alistair Francis
2021-06-08 0:29 ` [PULL 03/32] hw/riscv: Support the official CLINT DT bindings Alistair Francis
2021-06-08 0:29 ` [PULL 04/32] hw/riscv: Support the official PLIC " Alistair Francis
2021-06-08 0:29 ` [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices Alistair Francis
2021-06-08 0:29 ` [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage Alistair Francis
2021-06-08 0:29 ` [PULL 07/32] hw/riscv: Use macros for BIOS image names Alistair Francis
2021-06-08 0:29 ` [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot Alistair Francis
2021-06-08 0:29 ` [PULL 09/32] target/riscv: fix wfi exception behavior Alistair Francis
2021-06-08 0:29 ` [PULL 10/32] docs/system: Move the RISC-V -bios information to removed Alistair Francis
2021-06-08 0:29 ` [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation Alistair Francis
2021-06-08 0:29 ` [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration Alistair Francis
2021-06-08 0:29 ` [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp Alistair Francis
2021-06-08 0:29 ` [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations Alistair Francis
2021-06-08 0:29 ` [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz Alistair Francis
2021-06-08 0:29 ` Alistair Francis [this message]
2021-06-08 0:29 ` [PULL 17/32] target/riscv: rvb: count leading/trailing zeros Alistair Francis
2021-06-08 0:29 ` [PULL 18/32] target/riscv: rvb: count bits set Alistair Francis
2021-06-08 0:29 ` [PULL 19/32] target/riscv: rvb: logic-with-negate Alistair Francis
2021-06-08 0:29 ` [PULL 20/32] target/riscv: rvb: pack two words into one register Alistair Francis
2021-06-08 0:29 ` [PULL 21/32] target/riscv: rvb: min/max instructions Alistair Francis
2021-06-08 0:29 ` [PULL 22/32] target/riscv: rvb: sign-extend instructions Alistair Francis
2021-06-08 0:29 ` [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions Alistair Francis
2021-06-08 0:29 ` [PULL 24/32] target/riscv: rvb: single-bit instructions Alistair Francis
2021-06-08 0:29 ` [PULL 25/32] target/riscv: rvb: shift ones Alistair Francis
2021-06-08 0:29 ` [PULL 26/32] target/riscv: rvb: rotate (left/right) Alistair Francis
2021-06-08 0:29 ` [PULL 27/32] target/riscv: rvb: generalized reverse Alistair Francis
2021-06-08 0:29 ` [PULL 28/32] target/riscv: rvb: generalized or-combine Alistair Francis
2021-06-08 0:29 ` [PULL 29/32] target/riscv: rvb: address calculation Alistair Francis
2021-06-08 0:29 ` [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend Alistair Francis
2021-06-08 0:29 ` [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line Alistair Francis
2021-06-08 0:29 ` [PULL 32/32] target/riscv: rvb: add b-ext version cpu option Alistair Francis
2021-06-08 16:50 ` [PULL 00/32] riscv-to-apply queue Peter Maydell
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