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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: Frank Chang <frank.chang@sifive.com>,
	alistair23@gmail.com, Kito Cheng <kito.cheng@sifive.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend
Date: Tue,  8 Jun 2021 10:29:45 +1000	[thread overview]
Message-ID: <20210608002947.1649775-31-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210608002947.1649775-1-alistair.francis@wdc.com>

From: Kito Cheng <kito.cheng@sifive.com>

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  3 +++
 target/riscv/translate.c                |  6 ++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 26 +++++++++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 287920ee9b..f09f8d5faf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -720,6 +720,7 @@ gorcw      0010100 .......... 101 ..... 0111011 @r
 sh1add_uw  0010000 .......... 010 ..... 0111011 @r
 sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
+add_uw     0000100 .......... 000 ..... 0111011 @r
 
 bsetiw     0010100 .......... 001 ..... 0011011 @sh5
 bclriw     0100100 .......... 001 ..... 0011011 @sh5
@@ -729,3 +730,5 @@ sroiw      0010000 .......... 101 ..... 0011011 @sh5
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
+
+slli_uw    00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ae9b5f7a2e..c6e8739614 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -765,6 +765,12 @@ GEN_SHADD_UW(1)
 GEN_SHADD_UW(2)
 GEN_SHADD_UW(3)
 
+static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_add_tl(ret, arg1, arg2);
+}
+
 static bool gen_arith(DisasContext *ctx, arg_r *a,
                       void(*func)(TCGv, TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b27114a068..9e81f6e3de 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -410,3 +410,29 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
 GEN_TRANS_SHADD_UW(1)
 GEN_TRANS_SHADD_UW(2)
 GEN_TRANS_SHADD_UW(3)
+
+static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, gen_add_uw);
+}
+
+static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+
+    TCGv source1 = tcg_temp_new();
+    gen_get_gpr(source1, a->rs1);
+
+    if (a->shamt < 32) {
+        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
+    } else {
+        tcg_gen_shli_tl(source1, source1, a->shamt);
+    }
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    return true;
+}
-- 
2.31.1



  parent reply	other threads:[~2021-06-08  0:49 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-08  0:29 [PULL 00/32] riscv-to-apply queue Alistair Francis
2021-06-08  0:29 ` [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Alistair Francis
2021-06-08  0:29 ` [PULL 02/32] hw/riscv: virt: " Alistair Francis
2021-06-08  0:29 ` [PULL 03/32] hw/riscv: Support the official CLINT DT bindings Alistair Francis
2021-06-08  0:29 ` [PULL 04/32] hw/riscv: Support the official PLIC " Alistair Francis
2021-06-08  0:29 ` [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices Alistair Francis
2021-06-08  0:29 ` [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage Alistair Francis
2021-06-08  0:29 ` [PULL 07/32] hw/riscv: Use macros for BIOS image names Alistair Francis
2021-06-08  0:29 ` [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot Alistair Francis
2021-06-08  0:29 ` [PULL 09/32] target/riscv: fix wfi exception behavior Alistair Francis
2021-06-08  0:29 ` [PULL 10/32] docs/system: Move the RISC-V -bios information to removed Alistair Francis
2021-06-08  0:29 ` [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation Alistair Francis
2021-06-08  0:29 ` [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration Alistair Francis
2021-06-08  0:29 ` [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp Alistair Francis
2021-06-08  0:29 ` [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations Alistair Francis
2021-06-08  0:29 ` [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz Alistair Francis
2021-06-08  0:29 ` [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension Alistair Francis
2021-06-08  0:29 ` [PULL 17/32] target/riscv: rvb: count leading/trailing zeros Alistair Francis
2021-06-08  0:29 ` [PULL 18/32] target/riscv: rvb: count bits set Alistair Francis
2021-06-08  0:29 ` [PULL 19/32] target/riscv: rvb: logic-with-negate Alistair Francis
2021-06-08  0:29 ` [PULL 20/32] target/riscv: rvb: pack two words into one register Alistair Francis
2021-06-08  0:29 ` [PULL 21/32] target/riscv: rvb: min/max instructions Alistair Francis
2021-06-08  0:29 ` [PULL 22/32] target/riscv: rvb: sign-extend instructions Alistair Francis
2021-06-08  0:29 ` [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions Alistair Francis
2021-06-08  0:29 ` [PULL 24/32] target/riscv: rvb: single-bit instructions Alistair Francis
2021-06-08  0:29 ` [PULL 25/32] target/riscv: rvb: shift ones Alistair Francis
2021-06-08  0:29 ` [PULL 26/32] target/riscv: rvb: rotate (left/right) Alistair Francis
2021-06-08  0:29 ` [PULL 27/32] target/riscv: rvb: generalized reverse Alistair Francis
2021-06-08  0:29 ` [PULL 28/32] target/riscv: rvb: generalized or-combine Alistair Francis
2021-06-08  0:29 ` [PULL 29/32] target/riscv: rvb: address calculation Alistair Francis
2021-06-08  0:29 ` Alistair Francis [this message]
2021-06-08  0:29 ` [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line Alistair Francis
2021-06-08  0:29 ` [PULL 32/32] target/riscv: rvb: add b-ext version cpu option Alistair Francis
2021-06-08 16:50 ` [PULL 00/32] riscv-to-apply queue Peter Maydell

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