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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 03/32] hw/riscv: Support the official CLINT DT bindings
Date: Tue,  8 Jun 2021 10:29:18 +1000	[thread overview]
Message-ID: <20210608002947.1649775-4-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210608002947.1649775-1-alistair.francis@wdc.com>

From: Bin Meng <bin.meng@windriver.com>

Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 6 +++++-
 hw/riscv/spike.c    | 6 +++++-
 hw/riscv/virt.c     | 6 +++++-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 89cccd7fd5..d3828dc880 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -98,6 +98,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
     static const char * const ethclk_names[2] = { "pclk", "hclk" };
+    static const char * const clint_compat[2] = {
+        "sifive,clint0", "riscv,clint0"
+    };
 
     if (ms->dtb) {
         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
@@ -209,7 +212,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     nodename = g_strdup_printf("/soc/clint@%lx",
         (long)memmap[SIFIVE_U_DEV_CLINT].base);
     qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
+    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
+        (char **)&clint_compat, ARRAY_SIZE(clint_compat));
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_DEV_CLINT].base,
         0x0, memmap[SIFIVE_U_DEV_CLINT].size);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index fe0806a476..4b08816dfa 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -59,6 +59,9 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     uint32_t cpu_phandle, intc_phandle, phandle = 1;
     char *name, *mem_name, *clint_name, *clust_name;
     char *core_name, *cpu_name, *intc_name;
+    static const char * const clint_compat[2] = {
+        "sifive,clint0", "riscv,clint0"
+    };
 
     fdt = s->fdt = create_device_tree(&s->fdt_size);
     if (!fdt) {
@@ -152,7 +155,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             (memmap[SPIKE_CLINT].size * socket);
         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
         qemu_fdt_add_subnode(fdt, clint_name);
-        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
+            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
             0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1e017d1c52..5159e7e020 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -194,6 +194,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     char *name, *clint_name, *plic_name, *clust_name;
     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+    static const char * const clint_compat[2] = {
+        "sifive,clint0", "riscv,clint0"
+    };
 
     if (mc->dtb) {
         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -299,7 +302,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
             (memmap[VIRT_CLINT].size * socket);
         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
         qemu_fdt_add_subnode(fdt, clint_name);
-        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
+            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
             0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
-- 
2.31.1



  parent reply	other threads:[~2021-06-08  0:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-08  0:29 [PULL 00/32] riscv-to-apply queue Alistair Francis
2021-06-08  0:29 ` [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Alistair Francis
2021-06-08  0:29 ` [PULL 02/32] hw/riscv: virt: " Alistair Francis
2021-06-08  0:29 ` Alistair Francis [this message]
2021-06-08  0:29 ` [PULL 04/32] hw/riscv: Support the official PLIC DT bindings Alistair Francis
2021-06-08  0:29 ` [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices Alistair Francis
2021-06-08  0:29 ` [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage Alistair Francis
2021-06-08  0:29 ` [PULL 07/32] hw/riscv: Use macros for BIOS image names Alistair Francis
2021-06-08  0:29 ` [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot Alistair Francis
2021-06-08  0:29 ` [PULL 09/32] target/riscv: fix wfi exception behavior Alistair Francis
2021-06-08  0:29 ` [PULL 10/32] docs/system: Move the RISC-V -bios information to removed Alistair Francis
2021-06-08  0:29 ` [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation Alistair Francis
2021-06-08  0:29 ` [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration Alistair Francis
2021-06-08  0:29 ` [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp Alistair Francis
2021-06-08  0:29 ` [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations Alistair Francis
2021-06-08  0:29 ` [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz Alistair Francis
2021-06-08  0:29 ` [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension Alistair Francis
2021-06-08  0:29 ` [PULL 17/32] target/riscv: rvb: count leading/trailing zeros Alistair Francis
2021-06-08  0:29 ` [PULL 18/32] target/riscv: rvb: count bits set Alistair Francis
2021-06-08  0:29 ` [PULL 19/32] target/riscv: rvb: logic-with-negate Alistair Francis
2021-06-08  0:29 ` [PULL 20/32] target/riscv: rvb: pack two words into one register Alistair Francis
2021-06-08  0:29 ` [PULL 21/32] target/riscv: rvb: min/max instructions Alistair Francis
2021-06-08  0:29 ` [PULL 22/32] target/riscv: rvb: sign-extend instructions Alistair Francis
2021-06-08  0:29 ` [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions Alistair Francis
2021-06-08  0:29 ` [PULL 24/32] target/riscv: rvb: single-bit instructions Alistair Francis
2021-06-08  0:29 ` [PULL 25/32] target/riscv: rvb: shift ones Alistair Francis
2021-06-08  0:29 ` [PULL 26/32] target/riscv: rvb: rotate (left/right) Alistair Francis
2021-06-08  0:29 ` [PULL 27/32] target/riscv: rvb: generalized reverse Alistair Francis
2021-06-08  0:29 ` [PULL 28/32] target/riscv: rvb: generalized or-combine Alistair Francis
2021-06-08  0:29 ` [PULL 29/32] target/riscv: rvb: address calculation Alistair Francis
2021-06-08  0:29 ` [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend Alistair Francis
2021-06-08  0:29 ` [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line Alistair Francis
2021-06-08  0:29 ` [PULL 32/32] target/riscv: rvb: add b-ext version cpu option Alistair Francis
2021-06-08 16:50 ` [PULL 00/32] riscv-to-apply queue Peter Maydell

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