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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org
Subject: [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA
Date: Thu,  8 Jul 2021 21:26:01 -0700	[thread overview]
Message-ID: <20210709042608.883256-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210709042608.883256-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rva.c.inc | 42 +++++++++----------------
 1 file changed, 14 insertions(+), 28 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index ab2ec4f0a5..5bb5bbd09c 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -18,11 +18,11 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
+    TCGv src1 = gpr_src(ctx, a->rs1);
+
     /* Put addr in load_res, data in load_val.  */
-    gen_get_gpr(src1, a->rs1);
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
@@ -33,30 +33,26 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
     tcg_gen_mov_tl(load_res, src1);
     gen_set_gpr(a->rd, load_val);
 
-    tcg_temp_free(src1);
     return true;
 }
 
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
+    TCGv dest = gpr_dst(ctx, a->rd);
+    TCGv src1 = gpr_src(ctx, a->rs1);
+    TCGv src2 = gpr_src(ctx, a->rs2);
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    gen_get_gpr(src1, a->rs1);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
-    gen_get_gpr(src2, a->rs2);
     /*
      * Note that the TCG atomic primitives are SC,
      * so we can ignore AQ/RL along this path.
      */
-    tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
                               ctx->mem_idx, mop);
-    tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
-    gen_set_gpr(a->rd, dat);
+    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
     tcg_gen_br(l2);
 
     gen_set_label(l1);
@@ -65,8 +61,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      * provide the memory barrier implied by AQ/RL.
      */
     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
-    tcg_gen_movi_tl(dat, 1);
-    gen_set_gpr(a->rd, dat);
+    tcg_gen_movi_tl(dest, 1);
 
     gen_set_label(l2);
     /*
@@ -75,9 +70,6 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      */
     tcg_gen_movi_tl(load_res, -1);
 
-    tcg_temp_free(dat);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
     return true;
 }
 
@@ -85,17 +77,11 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
                     MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
+    TCGv dest = gpr_dst(ctx, a->rd);
+    TCGv src1 = gpr_src(ctx, a->rs1);
+    TCGv src2 = gpr_src(ctx, a->rs2);
 
-    gen_get_gpr(src1, a->rs1);
-    gen_get_gpr(src2, a->rs2);
-
-    (*func)(src2, src1, src2, ctx->mem_idx, mop);
-
-    gen_set_gpr(a->rd, src2);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
+    (*func)(dest, src1, src2, ctx->mem_idx, mop);
     return true;
 }
 
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com
Subject: [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA
Date: Thu,  8 Jul 2021 21:26:01 -0700	[thread overview]
Message-ID: <20210709042608.883256-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210709042608.883256-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rva.c.inc | 42 +++++++++----------------
 1 file changed, 14 insertions(+), 28 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index ab2ec4f0a5..5bb5bbd09c 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -18,11 +18,11 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
+    TCGv src1 = gpr_src(ctx, a->rs1);
+
     /* Put addr in load_res, data in load_val.  */
-    gen_get_gpr(src1, a->rs1);
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
@@ -33,30 +33,26 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
     tcg_gen_mov_tl(load_res, src1);
     gen_set_gpr(a->rd, load_val);
 
-    tcg_temp_free(src1);
     return true;
 }
 
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
+    TCGv dest = gpr_dst(ctx, a->rd);
+    TCGv src1 = gpr_src(ctx, a->rs1);
+    TCGv src2 = gpr_src(ctx, a->rs2);
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    gen_get_gpr(src1, a->rs1);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
-    gen_get_gpr(src2, a->rs2);
     /*
      * Note that the TCG atomic primitives are SC,
      * so we can ignore AQ/RL along this path.
      */
-    tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
                               ctx->mem_idx, mop);
-    tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
-    gen_set_gpr(a->rd, dat);
+    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
     tcg_gen_br(l2);
 
     gen_set_label(l1);
@@ -65,8 +61,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      * provide the memory barrier implied by AQ/RL.
      */
     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
-    tcg_gen_movi_tl(dat, 1);
-    gen_set_gpr(a->rd, dat);
+    tcg_gen_movi_tl(dest, 1);
 
     gen_set_label(l2);
     /*
@@ -75,9 +70,6 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      */
     tcg_gen_movi_tl(load_res, -1);
 
-    tcg_temp_free(dat);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
     return true;
 }
 
@@ -85,17 +77,11 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
                     MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
+    TCGv dest = gpr_dst(ctx, a->rd);
+    TCGv src1 = gpr_src(ctx, a->rs1);
+    TCGv src2 = gpr_src(ctx, a->rs2);
 
-    gen_get_gpr(src1, a->rs1);
-    gen_get_gpr(src2, a->rs2);
-
-    (*func)(src2, src1, src2, ctx->mem_idx, mop);
-
-    gen_set_gpr(a->rd, src2);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
+    (*func)(dest, src1, src2, ctx->mem_idx, mop);
     return true;
 }
 
-- 
2.25.1



  parent reply	other threads:[~2021-07-09  4:40 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-09  4:25 [PATCH 00/17] target/riscv: Use tcg_constant_* Richard Henderson
2021-07-09  4:25 ` Richard Henderson
2021-07-09  4:25 ` [PATCH 01/17] " Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-09  5:41   ` Alistair Francis
2021-07-09  5:41     ` Alistair Francis
2021-07-09 16:20   ` Philippe Mathieu-Daudé
2021-07-09 16:20     ` Philippe Mathieu-Daudé
2021-07-09  4:25 ` [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-09  5:45   ` Alistair Francis
2021-07-09  5:45     ` Alistair Francis
2021-07-09  4:25 ` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-13  4:10   ` [PATCH 03/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-13  4:10     ` Alistair Francis
2021-07-09  4:25 ` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-13  4:11   ` Alistair Francis
2021-07-13  4:11     ` Alistair Francis
2021-07-09  4:25 ` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-13  4:12   ` Alistair Francis
2021-07-13  4:12     ` Alistair Francis
2021-07-09  4:25 ` [PATCH 06/17] target/riscv: Use gpr_src in branches Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-13  4:14   ` Alistair Francis
2021-07-13  4:14     ` Alistair Francis
2021-07-09  4:25 ` [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-13  4:18   ` [PATCH 07/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-13  4:18     ` Alistair Francis
2021-07-09  4:25 ` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations Richard Henderson
2021-07-09  4:25   ` Richard Henderson
2021-07-15  4:49   ` Alistair Francis
2021-07-15  4:49     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 09/17] target/riscv: Reorg csr instructions Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-23  5:00   ` Alistair Francis
2021-07-23  5:00     ` Alistair Francis
2021-07-09  4:26 ` Richard Henderson [this message]
2021-07-09  4:26   ` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA Richard Henderson
2021-07-15  4:50   ` Alistair Francis
2021-07-15  4:50     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-15  4:52   ` Alistair Francis
2021-07-15  4:52     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-15  4:58   ` Alistair Francis
2021-07-15  4:58     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-15  5:00   ` Alistair Francis
2021-07-15  5:00     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-23  5:02   ` Alistair Francis
2021-07-23  5:02     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-15  5:02   ` Alistair Francis
2021-07-15  5:02     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-15  5:04   ` Alistair Francis
2021-07-15  5:04     ` Alistair Francis
2021-07-09  4:26 ` [PATCH 17/17] target/riscv: Remove gen_get_gpr Richard Henderson
2021-07-09  4:26   ` Richard Henderson
2021-07-15  5:08   ` Alistair Francis
2021-07-15  5:08     ` Alistair Francis
2021-07-15 11:21 ` [PATCH 00/17] target/riscv: Use tcg_constant_* LIU Zhiwei
2021-07-15 11:21   ` LIU Zhiwei
2021-07-15 16:15   ` Richard Henderson
2021-07-15 16:15     ` Richard Henderson
2021-07-17  3:59     ` LIU Zhiwei
2021-07-17  3:59       ` LIU Zhiwei
2021-07-17 15:41       ` Richard Henderson
2021-07-17 15:41         ` Richard Henderson

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