From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
Date: Thu, 15 Jul 2021 15:02:18 +1000 [thread overview]
Message-ID: <CAKmqyKOoLjJyrTqbKt6AGxak-HNesf1h8b5yOw1yv4et=y-UjQ@mail.gmail.com> (raw)
In-Reply-To: <20210709042608.883256-16-richard.henderson@linaro.org>
On Fri, Jul 9, 2021 at 2:40 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Split out gen_mulh and gen_mulhu and use the common helper.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 16 ++++++++++++++++
> target/riscv/insn_trans/trans_rvm.c.inc | 24 ++----------------------
> 2 files changed, 18 insertions(+), 22 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6ad40e43b0..8ff75a5798 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -235,6 +235,22 @@ static TCGv gpr_dst(DisasContext *ctx, int reg_num)
> return cpu_gpr[reg_num];
> }
>
> +static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
> +{
> + TCGv discard = tcg_temp_new();
> +
> + tcg_gen_muls2_tl(discard, ret, s1, s2);
> + tcg_temp_free(discard);
> +}
> +
> +static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
> +{
> + TCGv discard = tcg_temp_new();
> +
> + tcg_gen_mulu2_tl(discard, ret, s1, s2);
> + tcg_temp_free(discard);
> +}
> +
> static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> {
> TCGv rl = tcg_temp_new();
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
> index 10ecc456fc..34220b824d 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -28,17 +28,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
> static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
> {
> REQUIRE_EXT(ctx, RVM);
> - TCGv source1 = tcg_temp_new();
> - TCGv source2 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> - gen_get_gpr(source2, a->rs2);
> -
> - tcg_gen_muls2_tl(source2, source1, source1, source2);
> -
> - gen_set_gpr(a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> + return gen_arith(ctx, a, gen_mulh);
> }
>
> static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
> @@ -50,17 +40,7 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
> static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
> {
> REQUIRE_EXT(ctx, RVM);
> - TCGv source1 = tcg_temp_new();
> - TCGv source2 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> - gen_get_gpr(source2, a->rs2);
> -
> - tcg_gen_mulu2_tl(source2, source1, source1, source2);
> -
> - gen_set_gpr(a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> + return gen_arith(ctx, a, gen_mulhu);
> }
>
> static bool trans_div(DisasContext *ctx, arg_div *a)
> --
> 2.25.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
Date: Thu, 15 Jul 2021 15:02:18 +1000 [thread overview]
Message-ID: <CAKmqyKOoLjJyrTqbKt6AGxak-HNesf1h8b5yOw1yv4et=y-UjQ@mail.gmail.com> (raw)
In-Reply-To: <20210709042608.883256-16-richard.henderson@linaro.org>
On Fri, Jul 9, 2021 at 2:40 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Split out gen_mulh and gen_mulhu and use the common helper.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 16 ++++++++++++++++
> target/riscv/insn_trans/trans_rvm.c.inc | 24 ++----------------------
> 2 files changed, 18 insertions(+), 22 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6ad40e43b0..8ff75a5798 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -235,6 +235,22 @@ static TCGv gpr_dst(DisasContext *ctx, int reg_num)
> return cpu_gpr[reg_num];
> }
>
> +static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
> +{
> + TCGv discard = tcg_temp_new();
> +
> + tcg_gen_muls2_tl(discard, ret, s1, s2);
> + tcg_temp_free(discard);
> +}
> +
> +static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
> +{
> + TCGv discard = tcg_temp_new();
> +
> + tcg_gen_mulu2_tl(discard, ret, s1, s2);
> + tcg_temp_free(discard);
> +}
> +
> static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> {
> TCGv rl = tcg_temp_new();
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
> index 10ecc456fc..34220b824d 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -28,17 +28,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
> static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
> {
> REQUIRE_EXT(ctx, RVM);
> - TCGv source1 = tcg_temp_new();
> - TCGv source2 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> - gen_get_gpr(source2, a->rs2);
> -
> - tcg_gen_muls2_tl(source2, source1, source1, source2);
> -
> - gen_set_gpr(a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> + return gen_arith(ctx, a, gen_mulh);
> }
>
> static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
> @@ -50,17 +40,7 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
> static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
> {
> REQUIRE_EXT(ctx, RVM);
> - TCGv source1 = tcg_temp_new();
> - TCGv source2 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> - gen_get_gpr(source2, a->rs2);
> -
> - tcg_gen_mulu2_tl(source2, source1, source1, source2);
> -
> - gen_set_gpr(a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> + return gen_arith(ctx, a, gen_mulhu);
> }
>
> static bool trans_div(DisasContext *ctx, arg_div *a)
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-07-15 5:03 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 4:25 [PATCH 00/17] target/riscv: Use tcg_constant_* Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-09 4:25 ` [PATCH 01/17] " Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-09 5:41 ` Alistair Francis
2021-07-09 5:41 ` Alistair Francis
2021-07-09 16:20 ` Philippe Mathieu-Daudé
2021-07-09 16:20 ` Philippe Mathieu-Daudé
2021-07-09 4:25 ` [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-09 5:45 ` Alistair Francis
2021-07-09 5:45 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-13 4:10 ` [PATCH 03/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-13 4:10 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-13 4:11 ` Alistair Francis
2021-07-13 4:11 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-13 4:12 ` Alistair Francis
2021-07-13 4:12 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 06/17] target/riscv: Use gpr_src in branches Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-13 4:14 ` Alistair Francis
2021-07-13 4:14 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-13 4:18 ` [PATCH 07/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-13 4:18 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations Richard Henderson
2021-07-09 4:25 ` Richard Henderson
2021-07-15 4:49 ` Alistair Francis
2021-07-15 4:49 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 09/17] target/riscv: Reorg csr instructions Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-23 5:00 ` Alistair Francis
2021-07-23 5:00 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 4:50 ` Alistair Francis
2021-07-15 4:50 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 4:52 ` Alistair Francis
2021-07-15 4:52 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 4:58 ` Alistair Francis
2021-07-15 4:58 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 5:00 ` Alistair Francis
2021-07-15 5:00 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-23 5:02 ` Alistair Francis
2021-07-23 5:02 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 5:02 ` Alistair Francis [this message]
2021-07-15 5:02 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 5:04 ` Alistair Francis
2021-07-15 5:04 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 17/17] target/riscv: Remove gen_get_gpr Richard Henderson
2021-07-09 4:26 ` Richard Henderson
2021-07-15 5:08 ` Alistair Francis
2021-07-15 5:08 ` Alistair Francis
2021-07-15 11:21 ` [PATCH 00/17] target/riscv: Use tcg_constant_* LIU Zhiwei
2021-07-15 11:21 ` LIU Zhiwei
2021-07-15 16:15 ` Richard Henderson
2021-07-15 16:15 ` Richard Henderson
2021-07-17 3:59 ` LIU Zhiwei
2021-07-17 3:59 ` LIU Zhiwei
2021-07-17 15:41 ` Richard Henderson
2021-07-17 15:41 ` Richard Henderson
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