From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org Subject: [PATCH 06/17] target/riscv: Use gpr_src in branches Date: Thu, 8 Jul 2021 21:25:57 -0700 [thread overview] Message-ID: <20210709042608.883256-7-richard.henderson@linaro.org> (raw) In-Reply-To: <20210709042608.883256-1-richard.henderson@linaro.org> Narrow the scope of t0 in trans_jalr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 6e736c9d0d..a603925637 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -54,24 +54,25 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { - /* no chaining with JALR */ TCGLabel *misaligned = NULL; - TCGv t0 = tcg_temp_new(); - - gen_get_gpr(cpu_pc, a->rs1); - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); + tcg_gen_addi_tl(cpu_pc, gpr_src(ctx, a->rs1), a->imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); if (!has_ext(ctx, RVC)) { + TCGv t0 = tcg_temp_new(); + misaligned = gen_new_label(); tcg_gen_andi_tl(t0, cpu_pc, 0x2); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); + tcg_temp_free(t0); } if (a->rd != 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); } + + /* No chaining with JALR. */ lookup_and_goto_ptr(ctx); if (misaligned) { @@ -80,21 +81,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } ctx->base.is_jmp = DISAS_NORETURN; - tcg_temp_free(t0); return true; } static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l = gen_new_label(); - TCGv source1, source2; - source1 = tcg_temp_new(); - source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); - tcg_gen_brcond_tl(cond, source1, source2, l); + tcg_gen_brcond_tl(cond, src1, src2, l); gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { @@ -105,9 +103,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) } ctx->base.is_jmp = DISAS_NORETURN; - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; } -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com Subject: [PATCH 06/17] target/riscv: Use gpr_src in branches Date: Thu, 8 Jul 2021 21:25:57 -0700 [thread overview] Message-ID: <20210709042608.883256-7-richard.henderson@linaro.org> (raw) In-Reply-To: <20210709042608.883256-1-richard.henderson@linaro.org> Narrow the scope of t0 in trans_jalr. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 6e736c9d0d..a603925637 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -54,24 +54,25 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { - /* no chaining with JALR */ TCGLabel *misaligned = NULL; - TCGv t0 = tcg_temp_new(); - - gen_get_gpr(cpu_pc, a->rs1); - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); + tcg_gen_addi_tl(cpu_pc, gpr_src(ctx, a->rs1), a->imm); tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); if (!has_ext(ctx, RVC)) { + TCGv t0 = tcg_temp_new(); + misaligned = gen_new_label(); tcg_gen_andi_tl(t0, cpu_pc, 0x2); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); + tcg_temp_free(t0); } if (a->rd != 0) { tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); } + + /* No chaining with JALR. */ lookup_and_goto_ptr(ctx); if (misaligned) { @@ -80,21 +81,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } ctx->base.is_jmp = DISAS_NORETURN; - tcg_temp_free(t0); return true; } static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l = gen_new_label(); - TCGv source1, source2; - source1 = tcg_temp_new(); - source2 = tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - gen_get_gpr(source2, a->rs2); + TCGv src1 = gpr_src(ctx, a->rs1); + TCGv src2 = gpr_src(ctx, a->rs2); - tcg_gen_brcond_tl(cond, source1, source2, l); + tcg_gen_brcond_tl(cond, src1, src2, l); gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { @@ -105,9 +103,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) } ctx->base.is_jmp = DISAS_NORETURN; - tcg_temp_free(source1); - tcg_temp_free(source2); - return true; } -- 2.25.1
next prev parent reply other threads:[~2021-07-09 4:40 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-09 4:25 [PATCH 00/17] target/riscv: Use tcg_constant_* Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-09 4:25 ` [PATCH 01/17] " Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-09 5:41 ` Alistair Francis 2021-07-09 5:41 ` Alistair Francis 2021-07-09 16:20 ` Philippe Mathieu-Daudé 2021-07-09 16:20 ` Philippe Mathieu-Daudé 2021-07-09 4:25 ` [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-09 5:45 ` Alistair Francis 2021-07-09 5:45 ` Alistair Francis 2021-07-09 4:25 ` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-13 4:10 ` [PATCH 03/17] target/riscv: Use gpr_{src, dst} " Alistair Francis 2021-07-13 4:10 ` Alistair Francis 2021-07-09 4:25 ` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-13 4:11 ` Alistair Francis 2021-07-13 4:11 ` Alistair Francis 2021-07-09 4:25 ` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-13 4:12 ` Alistair Francis 2021-07-13 4:12 ` Alistair Francis 2021-07-09 4:25 ` Richard Henderson [this message] 2021-07-09 4:25 ` [PATCH 06/17] target/riscv: Use gpr_src in branches Richard Henderson 2021-07-13 4:14 ` Alistair Francis 2021-07-13 4:14 ` Alistair Francis 2021-07-09 4:25 ` [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-13 4:18 ` [PATCH 07/17] target/riscv: Use gpr_{src, dst} " Alistair Francis 2021-07-13 4:18 ` Alistair Francis 2021-07-09 4:25 ` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations Richard Henderson 2021-07-09 4:25 ` Richard Henderson 2021-07-15 4:49 ` Alistair Francis 2021-07-15 4:49 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 09/17] target/riscv: Reorg csr instructions Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-23 5:00 ` Alistair Francis 2021-07-23 5:00 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 4:50 ` Alistair Francis 2021-07-15 4:50 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 4:52 ` Alistair Francis 2021-07-15 4:52 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 4:58 ` Alistair Francis 2021-07-15 4:58 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 5:00 ` Alistair Francis 2021-07-15 5:00 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-23 5:02 ` Alistair Francis 2021-07-23 5:02 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 5:02 ` Alistair Francis 2021-07-15 5:02 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 5:04 ` Alistair Francis 2021-07-15 5:04 ` Alistair Francis 2021-07-09 4:26 ` [PATCH 17/17] target/riscv: Remove gen_get_gpr Richard Henderson 2021-07-09 4:26 ` Richard Henderson 2021-07-15 5:08 ` Alistair Francis 2021-07-15 5:08 ` Alistair Francis 2021-07-15 11:21 ` [PATCH 00/17] target/riscv: Use tcg_constant_* LIU Zhiwei 2021-07-15 11:21 ` LIU Zhiwei 2021-07-15 16:15 ` Richard Henderson 2021-07-15 16:15 ` Richard Henderson 2021-07-17 3:59 ` LIU Zhiwei 2021-07-17 3:59 ` LIU Zhiwei 2021-07-17 15:41 ` Richard Henderson 2021-07-17 15:41 ` Richard Henderson
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