* [PATCH 2/4] drm/amd/display: Update bounding box states (v2)
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
@ 2021-08-26 1:10 ` Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 3/4] drm/amd/display: Remove duplicate dml init Aurabindo Pillai
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 1:10 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, nicholas.kazlauskas, alexander.deucher,
aurabindo.pillai, Jerry (Fangzhi) Zuo, stable
From: "Jerry (Fangzhi) Zuo" <Jerry.Zuo@amd.com>
[Why]
Drop hardcoded dispclk, dppclk, phyclk
[How]
Read the corresponding values from clock table entries already populated.
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: stable@vger.kernel.org
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 41 ++++++++++++++-----
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 43ac6f42dd80..3d2443328345 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2398,16 +2398,37 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
if (bw_params->clk_table.entries[0].memclk_mhz) {
+ int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
+
+ for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
+ if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
+ max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+ if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
+ max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
+ if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
+ max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
+ if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
+ max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
+ }
+
+ if (!max_dcfclk_mhz)
+ max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
+ if (!max_dispclk_mhz)
+ max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;
+ if (!max_dppclk_mhz)
+ max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;
+ if (!max_phyclk_mhz)
+ max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;
- if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
- dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
+ dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
num_dcfclk_sta_targets++;
- } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
+ } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
for (i = 0; i < num_dcfclk_sta_targets; i++) {
- if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
- dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
+ if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
+ dcfclk_sta_targets[i] = max_dcfclk_mhz;
break;
}
}
@@ -2447,7 +2468,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} else {
- if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
+ if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else {
@@ -2462,7 +2483,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
}
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
- optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
+ optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
@@ -2475,9 +2496,9 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
/* Fill all states with max values of all other clocks */
- dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
- dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz;
- dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz;
+ dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
+ dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
+ dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
/* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] drm/amd/display: Remove duplicate dml init
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Aurabindo Pillai
@ 2021-08-26 1:10 ` Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 4/4] drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box Aurabindo Pillai
2021-08-26 2:00 ` Alex Deucher
3 siblings, 0 replies; 7+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 1:10 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, nicholas.kazlauskas, alexander.deucher, aurabindo.pillai
[Why & How]
DML is initialized again unnecessarily after its done conditionally.
Remove the duplicate initialization
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 3d2443328345..d090cb916767 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2511,11 +2511,6 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
if (dc->current_state)
dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
}
-
- /* re-init DML with updated bb */
- dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
- if (dc->current_state)
- dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
}
static const struct resource_funcs dcn30_res_pool_funcs = {
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 2/4] drm/amd/display: Update bounding box states (v2) Aurabindo Pillai
2021-08-26 1:10 ` [PATCH 3/4] drm/amd/display: Remove duplicate dml init Aurabindo Pillai
@ 2021-08-26 1:10 ` Aurabindo Pillai
2021-08-26 2:00 ` Alex Deucher
3 siblings, 0 replies; 7+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 1:10 UTC (permalink / raw)
To: amd-gfx
Cc: Harry.Wentland, nicholas.kazlauskas, alexander.deucher,
aurabindo.pillai, Daniel Wheeler
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
This is a global parameter, not a per pipe parameter and it's useful
for experimenting with the prefetch schedule to be adjustable from
the SOC bb.
[How]
Add a parameter to the SOC bb, default is the existing policy for
all DCN. Fill it in when filling SOC bb parameters.
Revert the policy to use MinDCFClk at the same time since that's not
going to give us P-State in most cases on the spreadsheet.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
.../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 7 +++++--
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 ++--
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index d090cb916767..2feffe75ca62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -92,7 +92,7 @@
#define DC_LOGGER_INIT(logger)
struct _vcs_dpi_ip_params_st dcn3_0_ip = {
- .use_min_dcfclk = 1,
+ .use_min_dcfclk = 0,
.clamp_min_dcfclk = 0,
.odm_capable = 1,
.gpuvm_enable = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index e1a961a62add..e3d9f1decdfc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3644,8 +3644,7 @@ static double TruncToValidBPP(
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
{
struct vba_vars_st *v = &mode_lib->vba;
- int MinPrefetchMode = 0;
- int MaxPrefetchMode = 2;
+ int MinPrefetchMode, MaxPrefetchMode;
int i;
unsigned int j, k, m;
bool EnoughWritebackUnits = true;
@@ -3657,6 +3656,10 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
+ CalculateMinAndMaxPrefetchMode(
+ mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
+ &MinPrefetchMode, &MaxPrefetchMode);
+
/*Scale Ratio, taps Support Check*/
v->ScaleRatioAndTapsSupport = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 73f5be26abc4..0fad15020c74 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -244,6 +244,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
mode_lib->vba.DummyPStateCheck;
mode_lib->vba.AllowDramClockChangeOneDisplayVactive = soc->allow_dram_clock_one_display_vactive;
+ mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank =
+ soc->allow_dram_self_refresh_or_dram_clock_change_in_vblank;
mode_lib->vba.Downspreading = soc->downspread_percent;
mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new!
@@ -733,8 +735,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
mode_lib->vba.OverrideHostVMPageTableLevels;
}
- mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank = dm_try_to_allow_self_refresh_and_mclk_switch;
-
if (mode_lib->vba.OverrideGPUVMPageTableLevels)
mode_lib->vba.GPUVMMaxPageTableLevels = mode_lib->vba.OverrideGPUVMPageTableLevels;
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
2021-08-26 1:09 [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states Aurabindo Pillai
@ 2021-08-26 2:00 ` Alex Deucher
2021-08-26 1:10 ` [PATCH 3/4] drm/amd/display: Remove duplicate dml init Aurabindo Pillai
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2021-08-26 2:00 UTC (permalink / raw)
To: Aurabindo Pillai
Cc: amd-gfx list, Wentland, Harry, Kazlauskas, Nicholas, Deucher,
Alexander, for 3.8
On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
<aurabindo.pillai@amd.com> wrote:
>
> [Why & How]
> The DCN3 SoC parameter num_states was calculated but not saved into the
> object.
>
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Cc: stable@vger.kernel.org
Please add:
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
to the series. With that fixed, series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> index 1333f0541f1b..43ac6f42dd80 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
> }
>
> + dcn3_0_soc.num_states = num_states;
> for (i = 0; i < dcn3_0_soc.num_states; i++) {
> dcn3_0_soc.clock_limits[i].state = i;
> dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
@ 2021-08-26 2:00 ` Alex Deucher
0 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2021-08-26 2:00 UTC (permalink / raw)
To: Aurabindo Pillai
Cc: amd-gfx list, Wentland, Harry, Kazlauskas, Nicholas, Deucher,
Alexander, for 3.8
On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
<aurabindo.pillai@amd.com> wrote:
>
> [Why & How]
> The DCN3 SoC parameter num_states was calculated but not saved into the
> object.
>
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Cc: stable@vger.kernel.org
Please add:
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403
to the series. With that fixed, series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> index 1333f0541f1b..43ac6f42dd80 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
> @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
> }
>
> + dcn3_0_soc.num_states = num_states;
> for (i = 0; i < dcn3_0_soc.num_states; i++) {
> dcn3_0_soc.clock_limits[i].state = i;
> dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] drm/amd/display: Update number of DCN3 clock states
2021-08-26 2:00 ` Alex Deucher
(?)
@ 2021-08-26 13:34 ` Aurabindo Pillai
-1 siblings, 0 replies; 7+ messages in thread
From: Aurabindo Pillai @ 2021-08-26 13:34 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx list, Wentland, Harry, Kazlauskas, Nicholas, Deucher,
Alexander, for 3.8
Bug info added and applied, thanks!
On 8/25/21 10:00 PM, Alex Deucher wrote:
> On Wed, Aug 25, 2021 at 9:10 PM Aurabindo Pillai
> <aurabindo.pillai@amd.com> wrote:
>>
>> [Why & How]
>> The DCN3 SoC parameter num_states was calculated but not saved into the
>> object.
>>
>> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
>> Cc: stable@vger.kernel.org
>
> Please add:
> Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1403&data=04%7C01%7Caurabindo.pillai%40amd.com%7C13083d4cd17f491b251608d968355aa9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637655400644887757%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=5OBOO0C%2FszESMd5QEjmRKKRsOM4KiMKFNWz6IdLOipM%3D&reserved=0
> to the series. With that fixed, series is:
> Acked-by: Alex Deucher <alexander.deucher@amd.com>zz
>
>> ---
>> drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> index 1333f0541f1b..43ac6f42dd80 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
>> @@ -2467,6 +2467,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
>> dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
>> }
>>
>> + dcn3_0_soc.num_states = num_states;
>> for (i = 0; i < dcn3_0_soc.num_states; i++) {
>> dcn3_0_soc.clock_limits[i].state = i;
>> dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
>> --
>> 2.30.2
>>
^ permalink raw reply [flat|nested] 7+ messages in thread