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* [PATCH 0/1] hw/arm/aspeed: Allow machine to set serial_hd(0)
@ 2021-08-31 23:31 pdel
  2021-08-31 23:31 ` [PATCH 1/1] " pdel
  2021-09-01  6:44 ` [PATCH 0/1] " Cédric Le Goater
  0 siblings, 2 replies; 6+ messages in thread
From: pdel @ 2021-08-31 23:31 UTC (permalink / raw)
  Cc: clg, qemu-devel, qemu-arm, patrick, andrew, f4bug, Peter Delevoryas

From: Peter Delevoryas <pdel@fb.com>

This is a follow-up to a discussion in a previous series I sent:

https://lore.kernel.org/qemu-devel/20210827210417.4022054-1-pdel@fb.com/

I tried to add a new machine type called Fuji that required the ability
to specify the UART connected to the first serial device on the command
line (serial_hd(0)).

After some discussion, we concluded that we could add a serial_dev
option to the machine class and the SoC to support this:

https://lore.kernel.org/qemu-devel/a802ecb1-aa49-fd4c-5bd2-2bb19af56ac9@kaod.org/

I didn't follow Cedric's advice _exactly_, so let me know if you have
suggestions. I used "uint32_t serial_hd0", because I think it more
clearly indicates that this is the device to connect to the first serial
device, serial_hd(0).

Also, I didn't know how to transfer data from the machine class to the
device state, so I just added the attribute to the machine class and
used 'qdev_get_machine' to within aspeed_soc_realize() based on some
code I found in hw/ppc/spapr_cpu_core.c. I expect that I'm missing
something, I've just been having some trouble figuring out the QEMU
object model.

If this patch is accepted, I can follow-up with another patch adding the
fuji machine type with "serial_hd0 = ASPEED_DEV_UART1".

Thanks,
Peter

Peter Delevoryas (1):
  hw/arm/aspeed: Allow machine to set serial_hd(0)

 hw/arm/aspeed.c         |  1 +
 hw/arm/aspeed_ast2600.c | 11 +++++++----
 hw/arm/aspeed_soc.c     |  9 ++++++---
 include/hw/arm/aspeed.h |  1 +
 4 files changed, 15 insertions(+), 7 deletions(-)

-- 
2.30.2



^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/1] hw/arm/aspeed: Allow machine to set serial_hd(0)
  2021-08-31 23:31 [PATCH 0/1] hw/arm/aspeed: Allow machine to set serial_hd(0) pdel
@ 2021-08-31 23:31 ` pdel
  2021-09-01  2:30   ` Patrick Williams
  2021-09-01  6:34   ` Cédric Le Goater
  2021-09-01  6:44 ` [PATCH 0/1] " Cédric Le Goater
  1 sibling, 2 replies; 6+ messages in thread
From: pdel @ 2021-08-31 23:31 UTC (permalink / raw)
  Cc: clg, qemu-devel, qemu-arm, patrick, andrew, f4bug, Peter Delevoryas

From: Peter Delevoryas <pdel@fb.com>

When you run QEMU with an Aspeed machine and a single serial device
using stdio like this:

    qemu -machine ast2600-evb -drive ... -serial stdio

The guest OS can read and write to the UART5 registers at 0x1E784000 and
it will receive from stdin and write to stdout. The Aspeed SoC's have a
lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
the board design, may be using any of them as the serial console. (See
"stdout-path" in a DTS to check which one is chosen).

Most boards, including all of those currently defined in
hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
some flexibility for different boards without requiring users to change
their command-line invocation of QEMU.

I tested this doesn't break existing code by booting an AST2500 OpenBMC
image and an AST2600 OpenBMC image, each using UART5 as the console.

Then I tested switching the default to UART1 and booting an AST2600
OpenBMC image that uses UART1, and that worked too.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
 hw/arm/aspeed.c         |  1 +
 hw/arm/aspeed_ast2600.c | 11 +++++++----
 hw/arm/aspeed_soc.c     |  9 ++++++---
 include/hw/arm/aspeed.h |  1 +
 4 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 9d43e26c51..74379907ff 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -804,6 +804,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
     mc->no_parallel = 1;
     mc->default_ram_id = "ram";
     amc->macs_mask = ASPEED_MAC0_ON;
+    amc->serial_hd0 = ASPEED_DEV_UART5;
 
     aspeed_machine_class_props_init(oc);
 }
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index e3013128c6..361a456214 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -10,6 +10,7 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/misc/unimp.h"
+#include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/char/serial.h"
 #include "qemu/module.h"
@@ -231,6 +232,8 @@ static uint64_t aspeed_calc_affinity(int cpu)
 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 {
     int i;
+    AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
+    AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
     AspeedSoCState *s = ASPEED_SOC(dev);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     Error *err = NULL;
@@ -322,10 +325,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
     }
 
-    /* UART - attach an 8250 to the IO space as our UART5 */
-    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
-                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
-                   38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+    /* Wire up the first serial device, usually either UART5 or UART1 */
+    serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
+                   aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
+                   serial_hd(0), DEVICE_LITTLE_ENDIAN);
 
     /* I2C */
     object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 3ad6c56fa9..77422bbeb1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -13,6 +13,7 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/misc/unimp.h"
+#include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/char/serial.h"
 #include "qemu/module.h"
@@ -221,6 +222,8 @@ static void aspeed_soc_init(Object *obj)
 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 {
     int i;
+    AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
+    AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
     AspeedSoCState *s = ASPEED_SOC(dev);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     Error *err = NULL;
@@ -287,9 +290,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
     }
 
-    /* UART - attach an 8250 to the IO space as our UART5 */
-    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
-                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400,
+    /* Wire up the first serial device, usually either UART5 or UART1 */
+    serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
+                   aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
                    serial_hd(0), DEVICE_LITTLE_ENDIAN);
 
     /* I2C */
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index c9747b15fc..bc0f27885a 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -38,6 +38,7 @@ struct AspeedMachineClass {
     uint32_t num_cs;
     uint32_t macs_mask;
     void (*i2c_init)(AspeedMachineState *bmc);
+    uint32_t serial_hd0;
 };
 
 
-- 
2.30.2



^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/1] hw/arm/aspeed: Allow machine to set serial_hd(0)
  2021-08-31 23:31 ` [PATCH 1/1] " pdel
@ 2021-09-01  2:30   ` Patrick Williams
  2021-09-01  6:34   ` Cédric Le Goater
  1 sibling, 0 replies; 6+ messages in thread
From: Patrick Williams @ 2021-09-01  2:30 UTC (permalink / raw)
  To: pdel; +Cc: andrew, f4bug, qemu-arm, clg, qemu-devel

[-- Attachment #1: Type: text/plain, Size: 1515 bytes --]

On Tue, Aug 31, 2021 at 04:31:40PM -0700, pdel@fb.com wrote:
> From: Peter Delevoryas <pdel@fb.com>
> 
> When you run QEMU with an Aspeed machine and a single serial device
> using stdio like this:
> 
>     qemu -machine ast2600-evb -drive ... -serial stdio
> 
> The guest OS can read and write to the UART5 registers at 0x1E784000 and
> it will receive from stdin and write to stdout. The Aspeed SoC's have a
> lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
> the board design, may be using any of them as the serial console. (See
> "stdout-path" in a DTS to check which one is chosen).
> 
> Most boards, including all of those currently defined in
> hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
> some flexibility for different boards without requiring users to change
> their command-line invocation of QEMU.
> 
> I tested this doesn't break existing code by booting an AST2500 OpenBMC
> image and an AST2600 OpenBMC image, each using UART5 as the console.
> 
> Then I tested switching the default to UART1 and booting an AST2600
> OpenBMC image that uses UART1, and that worked too.
> 
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
> ---
>  hw/arm/aspeed.c         |  1 +
>  hw/arm/aspeed_ast2600.c | 11 +++++++----
>  hw/arm/aspeed_soc.c     |  9 ++++++---
>  include/hw/arm/aspeed.h |  1 +
>  4 files changed, 15 insertions(+), 7 deletions(-)
> 

Reviewed-by: Patrick Williams <patrick@stwcx.xyz>

-- 
Patrick Williams

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/1] hw/arm/aspeed: Allow machine to set serial_hd(0)
  2021-08-31 23:31 ` [PATCH 1/1] " pdel
  2021-09-01  2:30   ` Patrick Williams
@ 2021-09-01  6:34   ` Cédric Le Goater
  2021-09-01 14:05     ` Peter Delevoryas
  1 sibling, 1 reply; 6+ messages in thread
From: Cédric Le Goater @ 2021-09-01  6:34 UTC (permalink / raw)
  To: pdel
  Cc: Peter Maydell, andrew, qemu-devel, f4bug, patrick, qemu-arm,
	Joel Stanley

Adding Peter Maydell and Joel.

On 9/1/21 1:31 AM, pdel@fb.com wrote:
> From: Peter Delevoryas <pdel@fb.com>
> 
> When you run QEMU with an Aspeed machine and a single serial device
> using stdio like this:
> 
>     qemu -machine ast2600-evb -drive ... -serial stdio
> 
> The guest OS can read and write to the UART5 registers at 0x1E784000 and
> it will receive from stdin and write to stdout. The Aspeed SoC's have a
> lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
> the board design, may be using any of them as the serial console. (See
> "stdout-path" in a DTS to check which one is chosen).
> 
> Most boards, including all of those currently defined in
> hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
> some flexibility for different boards without requiring users to change
> their command-line invocation of QEMU.
> 
> I tested this doesn't break existing code by booting an AST2500 OpenBMC
> image and an AST2600 OpenBMC image, each using UART5 as the console.
> 
> Then I tested switching the default to UART1 and booting an AST2600
> OpenBMC image that uses UART1, and that worked too.
> 
> Signed-off-by: Peter Delevoryas <pdel@fb.com>

Some comments below, 

> ---
>  hw/arm/aspeed.c         |  1 +
>  hw/arm/aspeed_ast2600.c | 11 +++++++----
>  hw/arm/aspeed_soc.c     |  9 ++++++---
>  include/hw/arm/aspeed.h |  1 +
>  4 files changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 9d43e26c51..74379907ff 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -804,6 +804,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
>      mc->no_parallel = 1;
>      mc->default_ram_id = "ram";
>      amc->macs_mask = ASPEED_MAC0_ON;
> +    amc->serial_hd0 = ASPEED_DEV_UART5;
>  
>      aspeed_machine_class_props_init(oc);
>  }
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index e3013128c6..361a456214 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -10,6 +10,7 @@
>  #include "qemu/osdep.h"
>  #include "qapi/error.h"
>  #include "hw/misc/unimp.h"
> +#include "hw/arm/aspeed.h"
>  #include "hw/arm/aspeed_soc.h"
>  #include "hw/char/serial.h"
>  #include "qemu/module.h"
> @@ -231,6 +232,8 @@ static uint64_t aspeed_calc_affinity(int cpu)
>  static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>  {
>      int i;
> +    AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
> +    AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);

This is reaching into the machine from the SoC which is not good
practice.

What you should do is add an attribute in AspeedSoCState and a 
property in aspeed_soc_properties[]. This property would be set 
in aspeed_machine_init() before realizing the soc object. Look 
at "dram" for an example.

Then, in the aspeed_soc_*_realize routines, you would use the 
attribute to initialize the default serial device.

I don't really know what to call this attribute and property.
How about uart_default and "uart-default" ? 

Thanks,

C.

>      AspeedSoCState *s = ASPEED_SOC(dev);
>      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>      Error *err = NULL;
> @@ -322,10 +325,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>          sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
>      }
>  
> -    /* UART - attach an 8250 to the IO space as our UART5 */
> -    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
> -                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
> -                   38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +    /* Wire up the first serial device, usually either UART5 or UART1 */
> +    serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
> +                   aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
> +                   serial_hd(0), DEVICE_LITTLE_ENDIAN);
>  
>      /* I2C */
>      object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 3ad6c56fa9..77422bbeb1 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -13,6 +13,7 @@
>  #include "qemu/osdep.h"
>  #include "qapi/error.h"
>  #include "hw/misc/unimp.h"
> +#include "hw/arm/aspeed.h"
>  #include "hw/arm/aspeed_soc.h"
>  #include "hw/char/serial.h"
>  #include "qemu/module.h"
> @@ -221,6 +222,8 @@ static void aspeed_soc_init(Object *obj)
>  static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>  {
>      int i;
> +    AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
> +    AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
>      AspeedSoCState *s = ASPEED_SOC(dev);
>      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>      Error *err = NULL;
> @@ -287,9 +290,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>          sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
>      }
>  
> -    /* UART - attach an 8250 to the IO space as our UART5 */
> -    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
> -                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400,
> +    /* Wire up the first serial device, usually either UART5 or UART1 */
> +    serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
> +                   aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
>                     serial_hd(0), DEVICE_LITTLE_ENDIAN);
>  
>      /* I2C */
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index c9747b15fc..bc0f27885a 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -38,6 +38,7 @@ struct AspeedMachineClass {
>      uint32_t num_cs;
>      uint32_t macs_mask;
>      void (*i2c_init)(AspeedMachineState *bmc);
> +    uint32_t serial_hd0;
>  };
>  
>  
> 



^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 0/1] hw/arm/aspeed: Allow machine to set serial_hd(0)
  2021-08-31 23:31 [PATCH 0/1] hw/arm/aspeed: Allow machine to set serial_hd(0) pdel
  2021-08-31 23:31 ` [PATCH 1/1] " pdel
@ 2021-09-01  6:44 ` Cédric Le Goater
  1 sibling, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2021-09-01  6:44 UTC (permalink / raw)
  To: pdel
  Cc: Peter Maydell, andrew, qemu-devel, f4bug, patrick, qemu-arm,
	Joel Stanley

On 9/1/21 1:31 AM, pdel@fb.com wrote:
> From: Peter Delevoryas <pdel@fb.com>
> 
> This is a follow-up to a discussion in a previous series I sent:
> 
> https://lore.kernel.org/qemu-devel/20210827210417.4022054-1-pdel@fb.com/
> 
> I tried to add a new machine type called Fuji that required the ability
> to specify the UART connected to the first serial device on the command
> line (serial_hd(0)).
> 
> After some discussion, we concluded that we could add a serial_dev
> option to the machine class and the SoC to support this:
> 
> https://lore.kernel.org/qemu-devel/a802ecb1-aa49-fd4c-5bd2-2bb19af56ac9@kaod.org/
> 
> I didn't follow Cedric's advice _exactly_, so let me know if you have
> suggestions. I used "uint32_t serial_hd0", because I think it more
> clearly indicates that this is the device to connect to the first serial
> device, serial_hd(0).

I don't have a strong opinion on the name but it is part of the user
API and can be set from the command line  : 

  -global driver=ast2600-a3,property=serial-hd0,value=5

I would prefer something like "uart-default" which makes more sense.

> Also, I didn't know how to transfer data from the machine class to the
> device state, so I just added the attribute to the machine class and
> used 'qdev_get_machine' to within aspeed_soc_realize() based on some
> code I found in hw/ppc/spapr_cpu_core.c. 

This is called from the reset execution path which is a bit special.
The use of qdev_get_machine() should be avoided when possible. 

> I expect that I'm missing
> something, I've just been having some trouble figuring out the QEMU
> object model.

Look at the "dram" property of the SoC.

Thanks,

C. 

> If this patch is accepted, I can follow-up with another patch adding the
> fuji machine type with "serial_hd0 = ASPEED_DEV_UART1".
> 
> Thanks,
> Peter
> 
> Peter Delevoryas (1):
>   hw/arm/aspeed: Allow machine to set serial_hd(0)
> 
>  hw/arm/aspeed.c         |  1 +
>  hw/arm/aspeed_ast2600.c | 11 +++++++----
>  hw/arm/aspeed_soc.c     |  9 ++++++---
>  include/hw/arm/aspeed.h |  1 +
>  4 files changed, 15 insertions(+), 7 deletions(-)
> 



^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/1] hw/arm/aspeed: Allow machine to set serial_hd(0)
  2021-09-01  6:34   ` Cédric Le Goater
@ 2021-09-01 14:05     ` Peter Delevoryas
  0 siblings, 0 replies; 6+ messages in thread
From: Peter Delevoryas @ 2021-09-01 14:05 UTC (permalink / raw)
  To: Cédric Le Goater
  Cc: Cameron Esfahani via, qemu-arm, patrick, andrew, f4bug,
	Peter Maydell, Joel Stanley



> On Aug 31, 2021, at 11:34 PM, Cédric Le Goater <clg@kaod.org> wrote:
> 
> Adding Peter Maydell and Joel.
> 
> On 9/1/21 1:31 AM, pdel@fb.com wrote:
>> From: Peter Delevoryas <pdel@fb.com>
>> 
>> When you run QEMU with an Aspeed machine and a single serial device
>> using stdio like this:
>> 
>>    qemu -machine ast2600-evb -drive ... -serial stdio
>> 
>> The guest OS can read and write to the UART5 registers at 0x1E784000 and
>> it will receive from stdin and write to stdout. The Aspeed SoC's have a
>> lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
>> the board design, may be using any of them as the serial console. (See
>> "stdout-path" in a DTS to check which one is chosen).
>> 
>> Most boards, including all of those currently defined in
>> hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
>> some flexibility for different boards without requiring users to change
>> their command-line invocation of QEMU.
>> 
>> I tested this doesn't break existing code by booting an AST2500 OpenBMC
>> image and an AST2600 OpenBMC image, each using UART5 as the console.
>> 
>> Then I tested switching the default to UART1 and booting an AST2600
>> OpenBMC image that uses UART1, and that worked too.
>> 
>> Signed-off-by: Peter Delevoryas <pdel@fb.com>
> 
> Some comments below, 
> 
>> ---
>> hw/arm/aspeed.c         |  1 +
>> hw/arm/aspeed_ast2600.c | 11 +++++++----
>> hw/arm/aspeed_soc.c     |  9 ++++++---
>> include/hw/arm/aspeed.h |  1 +
>> 4 files changed, 15 insertions(+), 7 deletions(-)
>> 
>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
>> index 9d43e26c51..74379907ff 100644
>> --- a/hw/arm/aspeed.c
>> +++ b/hw/arm/aspeed.c
>> @@ -804,6 +804,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
>>     mc->no_parallel = 1;
>>     mc->default_ram_id = "ram";
>>     amc->macs_mask = ASPEED_MAC0_ON;
>> +    amc->serial_hd0 = ASPEED_DEV_UART5;
>> 
>>     aspeed_machine_class_props_init(oc);
>> }
>> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
>> index e3013128c6..361a456214 100644
>> --- a/hw/arm/aspeed_ast2600.c
>> +++ b/hw/arm/aspeed_ast2600.c
>> @@ -10,6 +10,7 @@
>> #include "qemu/osdep.h"
>> #include "qapi/error.h"
>> #include "hw/misc/unimp.h"
>> +#include "hw/arm/aspeed.h"
>> #include "hw/arm/aspeed_soc.h"
>> #include "hw/char/serial.h"
>> #include "qemu/module.h"
>> @@ -231,6 +232,8 @@ static uint64_t aspeed_calc_affinity(int cpu)
>> static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>> {
>>     int i;
>> +    AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
>> +    AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
> 
> This is reaching into the machine from the SoC which is not good
> practice.
> 
> What you should do is add an attribute in AspeedSoCState and a 
> property in aspeed_soc_properties[]. This property would be set 
> in aspeed_machine_init() before realizing the soc object. Look 
> at "dram" for an example.

Ohhhh I see, thanks for explaining, I’ll fix this.

> 
> Then, in the aspeed_soc_*_realize routines, you would use the 
> attribute to initialize the default serial device.
> 
> I don't really know what to call this attribute and property.
> How about uart_default and "uart-default" ? 

Oh ok, yeah I’ll change it to uart_default and “uart-default”.

> 
> Thanks,
> 
> C.
> 
>>     AspeedSoCState *s = ASPEED_SOC(dev);
>>     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>>     Error *err = NULL;
>> @@ -322,10 +325,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>>         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
>>     }
>> 
>> -    /* UART - attach an 8250 to the IO space as our UART5 */
>> -    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
>> -                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
>> -                   38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
>> +    /* Wire up the first serial device, usually either UART5 or UART1 */
>> +    serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
>> +                   aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
>> +                   serial_hd(0), DEVICE_LITTLE_ENDIAN);
>> 
>>     /* I2C */
>>     object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
>> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
>> index 3ad6c56fa9..77422bbeb1 100644
>> --- a/hw/arm/aspeed_soc.c
>> +++ b/hw/arm/aspeed_soc.c
>> @@ -13,6 +13,7 @@
>> #include "qemu/osdep.h"
>> #include "qapi/error.h"
>> #include "hw/misc/unimp.h"
>> +#include "hw/arm/aspeed.h"
>> #include "hw/arm/aspeed_soc.h"
>> #include "hw/char/serial.h"
>> #include "qemu/module.h"
>> @@ -221,6 +222,8 @@ static void aspeed_soc_init(Object *obj)
>> static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>> {
>>     int i;
>> +    AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
>> +    AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
>>     AspeedSoCState *s = ASPEED_SOC(dev);
>>     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>>     Error *err = NULL;
>> @@ -287,9 +290,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>>         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
>>     }
>> 
>> -    /* UART - attach an 8250 to the IO space as our UART5 */
>> -    serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
>> -                   aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400,
>> +    /* Wire up the first serial device, usually either UART5 or UART1 */
>> +    serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
>> +                   aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
>>                    serial_hd(0), DEVICE_LITTLE_ENDIAN);
>> 
>>     /* I2C */
>> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
>> index c9747b15fc..bc0f27885a 100644
>> --- a/include/hw/arm/aspeed.h
>> +++ b/include/hw/arm/aspeed.h
>> @@ -38,6 +38,7 @@ struct AspeedMachineClass {
>>     uint32_t num_cs;
>>     uint32_t macs_mask;
>>     void (*i2c_init)(AspeedMachineState *bmc);
>> +    uint32_t serial_hd0;
>> };


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-09-01 14:07 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-31 23:31 [PATCH 0/1] hw/arm/aspeed: Allow machine to set serial_hd(0) pdel
2021-08-31 23:31 ` [PATCH 1/1] " pdel
2021-09-01  2:30   ` Patrick Williams
2021-09-01  6:34   ` Cédric Le Goater
2021-09-01 14:05     ` Peter Delevoryas
2021-09-01  6:44 ` [PATCH 0/1] " Cédric Le Goater

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