All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Max Filippov" <jcmvbkbc@gmail.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Warner Losh" <imp@bsdimp.com>, "Marek Vasut" <marex@denx.de>,
	"Yoshinori Sato" <ysato@users.sourceforge.jp>,
	qemu-ppc@nongnu.org, "Artyom Tarasenko" <atar4qemu@gmail.com>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Eduardo Habkost" <ehabkost@redhat.com>,
	"Kyle Evans" <kevans@freebsd.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Greg Kurz" <groug@kaod.org>,
	qemu-arm@nongnu.org, "Michael Rolnik" <mrolnik@gmail.com>,
	"Stafford Horne" <shorne@gmail.com>,
	"David Gibson" <david@gibson.dropbear.id.au>,
	qemu-riscv@nongnu.org, "Chris Wulff" <crwulff@gmail.com>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 19/24] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
Date: Thu,  2 Sep 2021 17:17:10 +0200	[thread overview]
Message-ID: <20210902151715.383678-20-f4bug@amsat.org> (raw)
In-Reply-To: <20210902151715.383678-1-f4bug@amsat.org>

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/sh4/cpu.h    | 4 ++--
 target/sh4/cpu.c    | 2 +-
 target/sh4/helper.c | 9 ++-------
 3 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 01c43440822..017a7702140 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -204,8 +204,6 @@ struct SuperHCPU {
 };
 
 
-void superh_cpu_do_interrupt(CPUState *cpu);
-bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -223,6 +221,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
 void sh4_cpu_list(void);
 #if !defined(CONFIG_USER_ONLY)
+void superh_cpu_do_interrupt(CPUState *cpu);
+bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
                                        hwaddr addr);
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 83269229421..2047742d03c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -236,10 +236,10 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
 static const struct TCGCPUOps superh_tcg_ops = {
     .initialize = sh4_translate_init,
     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
-    .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .tlb_fill = superh_cpu_tlb_fill,
 
 #ifndef CONFIG_USER_ONLY
+    .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .do_interrupt = superh_cpu_do_interrupt,
     .do_unaligned_access = superh_cpu_do_unaligned_access,
     .io_recompile_replay_branch = superh_io_recompile_replay_branch,
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 2d622081e85..53cb9c3b631 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -45,11 +45,6 @@
 
 #if defined(CONFIG_USER_ONLY)
 
-void superh_cpu_do_interrupt(CPUState *cs)
-{
-    cs->exception_index = -1;
-}
-
 int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
 {
     /* For user mode, only U0 area is cacheable. */
@@ -784,8 +779,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
     return 0;
 }
 
-#endif
-
 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
     if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -803,6 +796,8 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     return false;
 }
 
+#endif /* !CONFIG_USER_ONLY */
+
 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                          MMUAccessType access_type, int mmu_idx,
                          bool probe, uintptr_t retaddr)
-- 
2.31.1



WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Yoshinori Sato" <ysato@users.sourceforge.jp>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	qemu-arm@nongnu.org, "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Max Filippov" <jcmvbkbc@gmail.com>,
	"Warner Losh" <imp@bsdimp.com>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"Stafford Horne" <shorne@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Chris Wulff" <crwulff@gmail.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"David Gibson" <david@gibson.dropbear.id.au>,
	"Kyle Evans" <kevans@freebsd.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Eduardo Habkost" <ehabkost@redhat.com>,
	"Marek Vasut" <marex@denx.de>,
	"Artyom Tarasenko" <atar4qemu@gmail.com>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Greg Kurz" <groug@kaod.org>,
	qemu-riscv@nongnu.org, "Laurent Vivier" <laurent@vivier.eu>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-ppc@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PATCH 19/24] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
Date: Thu,  2 Sep 2021 17:17:10 +0200	[thread overview]
Message-ID: <20210902151715.383678-20-f4bug@amsat.org> (raw)
In-Reply-To: <20210902151715.383678-1-f4bug@amsat.org>

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/sh4/cpu.h    | 4 ++--
 target/sh4/cpu.c    | 2 +-
 target/sh4/helper.c | 9 ++-------
 3 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 01c43440822..017a7702140 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -204,8 +204,6 @@ struct SuperHCPU {
 };
 
 
-void superh_cpu_do_interrupt(CPUState *cpu);
-bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -223,6 +221,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
 void sh4_cpu_list(void);
 #if !defined(CONFIG_USER_ONLY)
+void superh_cpu_do_interrupt(CPUState *cpu);
+bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
                                        hwaddr addr);
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 83269229421..2047742d03c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -236,10 +236,10 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
 static const struct TCGCPUOps superh_tcg_ops = {
     .initialize = sh4_translate_init,
     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
-    .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .tlb_fill = superh_cpu_tlb_fill,
 
 #ifndef CONFIG_USER_ONLY
+    .cpu_exec_interrupt = superh_cpu_exec_interrupt,
     .do_interrupt = superh_cpu_do_interrupt,
     .do_unaligned_access = superh_cpu_do_unaligned_access,
     .io_recompile_replay_branch = superh_io_recompile_replay_branch,
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 2d622081e85..53cb9c3b631 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -45,11 +45,6 @@
 
 #if defined(CONFIG_USER_ONLY)
 
-void superh_cpu_do_interrupt(CPUState *cs)
-{
-    cs->exception_index = -1;
-}
-
 int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr)
 {
     /* For user mode, only U0 area is cacheable. */
@@ -784,8 +779,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
     return 0;
 }
 
-#endif
-
 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
     if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -803,6 +796,8 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     return false;
 }
 
+#endif /* !CONFIG_USER_ONLY */
+
 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                          MMUAccessType access_type, int mmu_idx,
                          bool probe, uintptr_t retaddr)
-- 
2.31.1



  parent reply	other threads:[~2021-09-02 15:44 UTC|newest]

Thread overview: 152+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 15:16 [PATCH 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-02 15:16 ` Philippe Mathieu-Daudé
2021-09-02 15:16 ` [PATCH 01/24] target/xtensa: Restrict do_transaction_failed() " Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:09   ` Warner Losh
2021-09-02 20:09     ` Warner Losh
2021-09-03 18:54   ` Richard Henderson
2021-09-03 18:54     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:10   ` Warner Losh
2021-09-02 20:10     ` Warner Losh
2021-09-03 18:58   ` Richard Henderson
2021-09-03 18:58     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:10   ` Warner Losh
2021-09-02 20:10     ` Warner Losh
2021-09-03 19:00   ` Richard Henderson
2021-09-03 19:00     ` Richard Henderson
2021-09-02 15:16 ` [RFC PATCH 04/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_exception Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:14   ` Warner Losh
2021-09-02 20:14     ` Warner Losh
2021-09-03 19:07   ` Richard Henderson
2021-09-03 19:07     ` Richard Henderson
2021-09-04 23:26     ` Philippe Mathieu-Daudé
2021-09-04 23:26       ` Philippe Mathieu-Daudé
2021-09-02 15:16 ` [PATCH 05/24] accel/tcg: Assert most of cpu_handle_interrupt() is sysemu-specific Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-03 19:08   ` Richard Henderson
2021-09-03 19:08     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:15   ` Warner Losh
2021-09-02 20:15     ` Warner Losh
2021-09-03 19:09   ` Richard Henderson
2021-09-03 19:09     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 07/24] target/arm: " Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:16   ` Warner Losh
2021-09-02 20:16     ` Warner Losh
2021-09-03 19:10   ` Richard Henderson
2021-09-03 19:10     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 08/24] target/avr: " Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:16   ` Warner Losh
2021-09-02 20:16     ` Warner Losh
2021-09-03 19:12   ` Richard Henderson
2021-09-03 19:12     ` Richard Henderson
2021-09-03 20:47     ` Philippe Mathieu-Daudé
2021-09-03 20:47       ` Philippe Mathieu-Daudé
2021-09-03 20:50       ` Richard Henderson
2021-09-03 20:50         ` Richard Henderson
2021-09-02 15:17 ` [PATCH 09/24] target/cris: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:17   ` Warner Losh
2021-09-02 20:17     ` Warner Losh
2021-09-03 19:12   ` Richard Henderson
2021-09-03 19:12     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 10/24] target/hppa: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:17   ` Warner Losh
2021-09-02 20:17     ` Warner Losh
2021-09-03 19:14   ` Richard Henderson
2021-09-03 19:14     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 11/24] target/i386: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:18   ` Warner Losh
2021-09-02 20:18     ` Warner Losh
2021-09-03 19:15   ` Richard Henderson
2021-09-03 19:15     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 12/24] target/m68k: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:19   ` Warner Losh
2021-09-02 20:19     ` Warner Losh
2021-09-03 19:16   ` Richard Henderson
2021-09-03 19:16     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 13/24] target/microblaze: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:20   ` Warner Losh
2021-09-02 20:20     ` Warner Losh
2021-09-03 19:16   ` Richard Henderson
2021-09-03 19:16     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 14/24] target/mips: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:21   ` Warner Losh
2021-09-02 20:21     ` Warner Losh
2021-09-03 19:17   ` Richard Henderson
2021-09-03 19:17     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 15/24] target/nios2: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:22   ` Warner Losh
2021-09-02 20:22     ` Warner Losh
2021-09-03 19:17   ` Richard Henderson
2021-09-03 19:17     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 16/24] target/openrisc: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:24   ` Warner Losh
2021-09-02 20:24     ` Warner Losh
2021-09-04 23:40     ` Philippe Mathieu-Daudé
2021-09-04 23:40       ` Philippe Mathieu-Daudé
2021-09-03 19:18   ` Richard Henderson
2021-09-03 19:18     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 17/24] target/ppc: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:24   ` Warner Losh
2021-09-02 20:24     ` Warner Losh
2021-09-03  0:48   ` David Gibson
2021-09-03  0:48     ` David Gibson
2021-09-03 19:19   ` Richard Henderson
2021-09-03 19:19     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 18/24] target/riscv: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:25   ` Warner Losh
2021-09-02 20:25     ` Warner Losh
2021-09-03 19:21   ` Richard Henderson
2021-09-03 19:21     ` Richard Henderson
2021-09-02 15:17 ` Philippe Mathieu-Daudé [this message]
2021-09-02 15:17   ` [PATCH 19/24] target/sh4: " Philippe Mathieu-Daudé
2021-09-02 20:25   ` Warner Losh
2021-09-02 20:25     ` Warner Losh
2021-09-03 19:22   ` Richard Henderson
2021-09-03 19:22     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 20/24] target/sparc: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:26   ` Warner Losh
2021-09-02 20:26     ` Warner Losh
2021-09-03 19:22   ` Richard Henderson
2021-09-03 19:22     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 21/24] target/rx: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:26   ` Warner Losh
2021-09-02 20:26     ` Warner Losh
2021-09-03 19:23   ` Richard Henderson
2021-09-03 19:23     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 22/24] target/xtensa: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:26   ` Warner Losh
2021-09-02 20:26     ` Warner Losh
2021-09-03 19:24   ` Richard Henderson
2021-09-03 19:24     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-03 19:26   ` Richard Henderson
2021-09-03 19:26     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:27   ` Warner Losh
2021-09-02 20:27     ` Warner Losh
2021-09-03 19:27   ` Richard Henderson
2021-09-03 19:27     ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210902151715.383678-20-f4bug@amsat.org \
    --to=f4bug@amsat.org \
    --cc=aleksandar.rikalo@syrmia.com \
    --cc=alistair.francis@wdc.com \
    --cc=atar4qemu@gmail.com \
    --cc=aurelien@aurel32.net \
    --cc=bin.meng@windriver.com \
    --cc=crwulff@gmail.com \
    --cc=david@gibson.dropbear.id.au \
    --cc=edgar.iglesias@gmail.com \
    --cc=ehabkost@redhat.com \
    --cc=groug@kaod.org \
    --cc=imp@bsdimp.com \
    --cc=jcmvbkbc@gmail.com \
    --cc=kevans@freebsd.org \
    --cc=laurent@vivier.eu \
    --cc=marex@denx.de \
    --cc=mark.cave-ayland@ilande.co.uk \
    --cc=mrolnik@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=shorne@gmail.com \
    --cc=ysato@users.sourceforge.jp \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.