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From: Warner Losh <imp@bsdimp.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Bin Meng <bin.meng@windriver.com>,
	Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Max Filippov <jcmvbkbc@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	Marek Vasut <marex@denx.de>,
	Yoshinori Sato <ysato@users.sourceforge.jp>,
	qemu-ppc <qemu-ppc@nongnu.org>,
	Artyom Tarasenko <atar4qemu@gmail.com>,
	Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Kyle Evans <kevans@freebsd.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Greg Kurz <groug@kaod.org>, qemu-arm <qemu-arm@nongnu.org>,
	Michael Rolnik <mrolnik@gmail.com>,
	Stafford Horne <shorne@gmail.com>,
	David Gibson <david@gibson.dropbear.id.au>,
	qemu-riscv@nongnu.org, Chris Wulff <crwulff@gmail.com>,
	Laurent Vivier <laurent@vivier.eu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH 01/24] target/xtensa: Restrict do_transaction_failed() to sysemu
Date: Thu, 2 Sep 2021 14:09:42 -0600	[thread overview]
Message-ID: <CANCZdfrHrQQkiXmBc62X0b36n726iDCwvLfYXQrker7knhhD0g@mail.gmail.com> (raw)
In-Reply-To: <20210902151715.383678-2-f4bug@amsat.org>

[-- Attachment #1: Type: text/plain, Size: 1464 bytes --]

On Thu, Sep 2, 2021 at 9:17 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:

> The do_transaction_failed() is restricted to system emulation since
> commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops").
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>

Reviewed-by: Warner Losh <imp@bsdimp.com>


> ---
>  target/xtensa/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 2345cb59c79..1e0cb1535ca 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -568,10 +568,12 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr
> address, int size,
>                           bool probe, uintptr_t retaddr);
>  void xtensa_cpu_do_interrupt(CPUState *cpu);
>  bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
> +#ifndef CONFIG_USER_ONLY
>  void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> vaddr addr,
>                                        unsigned size, MMUAccessType
> access_type,
>                                        int mmu_idx, MemTxAttrs attrs,
>                                        MemTxResult response, uintptr_t
> retaddr);
> +#endif /* !CONFIG_USER_ONLY */
>  void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
>  hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
>  void xtensa_count_regs(const XtensaConfig *config,
> --
> 2.31.1
>
>

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WARNING: multiple messages have this Message-ID (diff)
From: Warner Losh <imp@bsdimp.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	Yoshinori Sato <ysato@users.sourceforge.jp>,
	 Jiaxun Yang <jiaxun.yang@flygoat.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Max Filippov <jcmvbkbc@gmail.com>,
	 Michael Rolnik <mrolnik@gmail.com>,
	Stafford Horne <shorne@gmail.com>,
	 Paolo Bonzini <pbonzini@redhat.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	 Bin Meng <bin.meng@windriver.com>,
	Chris Wulff <crwulff@gmail.com>,
	 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	David Gibson <david@gibson.dropbear.id.au>,
	 Kyle Evans <kevans@freebsd.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	 Aurelien Jarno <aurelien@aurel32.net>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Marek Vasut <marex@denx.de>,
	Artyom Tarasenko <atar4qemu@gmail.com>,
	Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	 Greg Kurz <groug@kaod.org>,
	qemu-riscv@nongnu.org, Laurent Vivier <laurent@vivier.eu>,
	qemu-ppc <qemu-ppc@nongnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	 Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH 01/24] target/xtensa: Restrict do_transaction_failed() to sysemu
Date: Thu, 2 Sep 2021 14:09:42 -0600	[thread overview]
Message-ID: <CANCZdfrHrQQkiXmBc62X0b36n726iDCwvLfYXQrker7knhhD0g@mail.gmail.com> (raw)
In-Reply-To: <20210902151715.383678-2-f4bug@amsat.org>

[-- Attachment #1: Type: text/plain, Size: 1464 bytes --]

On Thu, Sep 2, 2021 at 9:17 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:

> The do_transaction_failed() is restricted to system emulation since
> commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops").
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>

Reviewed-by: Warner Losh <imp@bsdimp.com>


> ---
>  target/xtensa/cpu.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 2345cb59c79..1e0cb1535ca 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -568,10 +568,12 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr
> address, int size,
>                           bool probe, uintptr_t retaddr);
>  void xtensa_cpu_do_interrupt(CPUState *cpu);
>  bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
> +#ifndef CONFIG_USER_ONLY
>  void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> vaddr addr,
>                                        unsigned size, MMUAccessType
> access_type,
>                                        int mmu_idx, MemTxAttrs attrs,
>                                        MemTxResult response, uintptr_t
> retaddr);
> +#endif /* !CONFIG_USER_ONLY */
>  void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
>  hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
>  void xtensa_count_regs(const XtensaConfig *config,
> --
> 2.31.1
>
>

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  reply	other threads:[~2021-09-02 20:11 UTC|newest]

Thread overview: 152+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 15:16 [PATCH 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-02 15:16 ` Philippe Mathieu-Daudé
2021-09-02 15:16 ` [PATCH 01/24] target/xtensa: Restrict do_transaction_failed() " Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:09   ` Warner Losh [this message]
2021-09-02 20:09     ` Warner Losh
2021-09-03 18:54   ` Richard Henderson
2021-09-03 18:54     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:10   ` Warner Losh
2021-09-02 20:10     ` Warner Losh
2021-09-03 18:58   ` Richard Henderson
2021-09-03 18:58     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:10   ` Warner Losh
2021-09-02 20:10     ` Warner Losh
2021-09-03 19:00   ` Richard Henderson
2021-09-03 19:00     ` Richard Henderson
2021-09-02 15:16 ` [RFC PATCH 04/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_exception Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:14   ` Warner Losh
2021-09-02 20:14     ` Warner Losh
2021-09-03 19:07   ` Richard Henderson
2021-09-03 19:07     ` Richard Henderson
2021-09-04 23:26     ` Philippe Mathieu-Daudé
2021-09-04 23:26       ` Philippe Mathieu-Daudé
2021-09-02 15:16 ` [PATCH 05/24] accel/tcg: Assert most of cpu_handle_interrupt() is sysemu-specific Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-03 19:08   ` Richard Henderson
2021-09-03 19:08     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:15   ` Warner Losh
2021-09-02 20:15     ` Warner Losh
2021-09-03 19:09   ` Richard Henderson
2021-09-03 19:09     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 07/24] target/arm: " Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:16   ` Warner Losh
2021-09-02 20:16     ` Warner Losh
2021-09-03 19:10   ` Richard Henderson
2021-09-03 19:10     ` Richard Henderson
2021-09-02 15:16 ` [PATCH 08/24] target/avr: " Philippe Mathieu-Daudé
2021-09-02 15:16   ` Philippe Mathieu-Daudé
2021-09-02 20:16   ` Warner Losh
2021-09-02 20:16     ` Warner Losh
2021-09-03 19:12   ` Richard Henderson
2021-09-03 19:12     ` Richard Henderson
2021-09-03 20:47     ` Philippe Mathieu-Daudé
2021-09-03 20:47       ` Philippe Mathieu-Daudé
2021-09-03 20:50       ` Richard Henderson
2021-09-03 20:50         ` Richard Henderson
2021-09-02 15:17 ` [PATCH 09/24] target/cris: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:17   ` Warner Losh
2021-09-02 20:17     ` Warner Losh
2021-09-03 19:12   ` Richard Henderson
2021-09-03 19:12     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 10/24] target/hppa: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:17   ` Warner Losh
2021-09-02 20:17     ` Warner Losh
2021-09-03 19:14   ` Richard Henderson
2021-09-03 19:14     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 11/24] target/i386: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:18   ` Warner Losh
2021-09-02 20:18     ` Warner Losh
2021-09-03 19:15   ` Richard Henderson
2021-09-03 19:15     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 12/24] target/m68k: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:19   ` Warner Losh
2021-09-02 20:19     ` Warner Losh
2021-09-03 19:16   ` Richard Henderson
2021-09-03 19:16     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 13/24] target/microblaze: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:20   ` Warner Losh
2021-09-02 20:20     ` Warner Losh
2021-09-03 19:16   ` Richard Henderson
2021-09-03 19:16     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 14/24] target/mips: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:21   ` Warner Losh
2021-09-02 20:21     ` Warner Losh
2021-09-03 19:17   ` Richard Henderson
2021-09-03 19:17     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 15/24] target/nios2: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:22   ` Warner Losh
2021-09-02 20:22     ` Warner Losh
2021-09-03 19:17   ` Richard Henderson
2021-09-03 19:17     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 16/24] target/openrisc: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:24   ` Warner Losh
2021-09-02 20:24     ` Warner Losh
2021-09-04 23:40     ` Philippe Mathieu-Daudé
2021-09-04 23:40       ` Philippe Mathieu-Daudé
2021-09-03 19:18   ` Richard Henderson
2021-09-03 19:18     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 17/24] target/ppc: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:24   ` Warner Losh
2021-09-02 20:24     ` Warner Losh
2021-09-03  0:48   ` David Gibson
2021-09-03  0:48     ` David Gibson
2021-09-03 19:19   ` Richard Henderson
2021-09-03 19:19     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 18/24] target/riscv: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:25   ` Warner Losh
2021-09-02 20:25     ` Warner Losh
2021-09-03 19:21   ` Richard Henderson
2021-09-03 19:21     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 19/24] target/sh4: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:25   ` Warner Losh
2021-09-02 20:25     ` Warner Losh
2021-09-03 19:22   ` Richard Henderson
2021-09-03 19:22     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 20/24] target/sparc: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:26   ` Warner Losh
2021-09-02 20:26     ` Warner Losh
2021-09-03 19:22   ` Richard Henderson
2021-09-03 19:22     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 21/24] target/rx: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:26   ` Warner Losh
2021-09-02 20:26     ` Warner Losh
2021-09-03 19:23   ` Richard Henderson
2021-09-03 19:23     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 22/24] target/xtensa: " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:26   ` Warner Losh
2021-09-02 20:26     ` Warner Losh
2021-09-03 19:24   ` Richard Henderson
2021-09-03 19:24     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-03 19:26   ` Richard Henderson
2021-09-03 19:26     ` Richard Henderson
2021-09-02 15:17 ` [PATCH 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
2021-09-02 15:17   ` Philippe Mathieu-Daudé
2021-09-02 20:27   ` Warner Losh
2021-09-02 20:27     ` Warner Losh
2021-09-03 19:27   ` Richard Henderson
2021-09-03 19:27     ` Richard Henderson

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