[Intel-gfx] [PATCH V4 0/6] drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Intel-gfx] [PATCH V4 0/6] drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Ayaz A Siddiqui]

Gen >= 12 onwards MOCS table doesn't have a setting for PTE
so I915_MOCS_PTE is not a valid index and it will have different
MOCS values are based on the platform.

To detect these kinds of misprogramming, all the unspecified and
reserved MOCS indexes are set to WB_L3. TGL/RKL unspecified MOCS
indexes are pointing to L3 UC are kept intact to avoid API break.

This series also contains patches to program BLIT_CCTL and
CMD_CCTL registers to UC.
Since we are quite late to update MOCS table for TGL so added
a new MOCS table for ADL family.

V2:
  1. Added CMD_CCTL to GUC regset list so that it can be restored
     after engine reset.
  2. Checkpatch warning removal.

V3:
 1. Changed implementation to have a framework only.
 2. Added register type for proper application.
 3. moved CMD_CCTL programming to a separate patch.
 4. Added L3CC initialization during gt reset so that MOCS indexes are
    set before GuC initialization.
 5. Removed Renderer check for L3CC verification in selftest.

V4:
 1. Moved register programming in Workaorund section as fake workaround.
 2. Removed seperate ADL mocs table, new logic is to set unused index as
 L3_WB for gen12 platform except TGL/RKL.  

Ayaz A Siddiqui (5):
  drm/i915/gt: Add support of mocs propagation
  drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
  drm/i915/gt: Set BLIT_CCTL reg to un-cached
  drm/i915/gt: Initialize unused MOCS entries with device specific
    values
  drm/i915/selftest: Remove Renderer class check for l3cc table read

Sreedhar Telukuntla (1):
  drm/i915/gt: Initialize L3CC table in mocs init

 drivers/gpu/drm/i915/gt/intel_gt.c          |  2 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |  4 ++
 drivers/gpu/drm/i915/gt/intel_mocs.c        | 72 ++++++++++++++-------
 drivers/gpu/drm/i915/gt/intel_mocs.h        |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 69 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/selftest_mocs.c     |  4 +-
 drivers/gpu/drm/i915/i915_reg.h             | 26 ++++++++
 7 files changed, 152 insertions(+), 26 deletions(-)

-- 
2.26.2

[Intel-gfx] [PATCH V4 1/6] drm/i915/gt: Add support of mocs propagation

[Ayaz A Siddiqui]

Now there are lots of Command and registers that require mocs index
programming.
So propagating mocs_index from mocs to gt so that it can be
used directly without having platform-specific checks.

Cc: CQ Tang<cq.tang@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       |  2 ++
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 ++++
 drivers/gpu/drm/i915/gt/intel_mocs.c     | 13 +++++++++++++
 drivers/gpu/drm/i915/gt/intel_mocs.h     |  1 +
 4 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62d40c9866427..2aeaae036a6f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -682,6 +682,8 @@ int intel_gt_init(struct intel_gt *gt)
 		goto err_pm;
 	}
 
+	set_mocs_index(gt);
+
 	err = intel_engines_init(gt);
 	if (err)
 		goto err_engines;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a81e21bf1bd1a..88601a2d2c229 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -192,6 +192,10 @@ struct intel_gt {
 
 		unsigned long mslice_mask;
 	} info;
+
+	struct i915_mocs_index_gt {
+		u8 uc_index;
+	} mocs;
 };
 
 enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 582c4423b95d6..7ccac15d9a331 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
 	unsigned int size;
 	unsigned int n_entries;
 	const struct drm_i915_mocs_entry *table;
+	u8 uc_index;
 };
 
 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
@@ -340,14 +341,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
 	unsigned int flags;
 
+	memset(table, 0, sizeof(struct drm_i915_mocs_table));
+
 	if (IS_DG1(i915)) {
 		table->size = ARRAY_SIZE(dg1_mocs_table);
 		table->table = dg1_mocs_table;
+		table->uc_index = 1;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tgl_mocs_table);
 		table->table = tgl_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+		table->uc_index = 3;
 	} else if (GRAPHICS_VER(i915) == 11) {
 		table->size  = ARRAY_SIZE(icl_mocs_table);
 		table->table = icl_mocs_table;
@@ -504,6 +509,14 @@ static u32 global_mocs_offset(void)
 	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
 }
 
+void set_mocs_index(struct intel_gt *gt)
+{
+	struct drm_i915_mocs_table table;
+
+	get_mocs_settings(gt->i915, &table);
+	gt->mocs.uc_index = table.uc_index;
+}
+
 void intel_mocs_init(struct intel_gt *gt)
 {
 	struct drm_i915_mocs_table table;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index d83274f5163bd..8a09d64b115f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -36,5 +36,6 @@ struct intel_gt;
 
 void intel_mocs_init(struct intel_gt *gt);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
+void set_mocs_index(struct intel_gt *gt);
 
 #endif
-- 
2.26.2

Re: [Intel-gfx] [PATCH V4 1/6] drm/i915/gt: Add support of mocs propagation

[Matt Roper]

On Fri, Sep 03, 2021 at 12:26:30AM +0530, Ayaz A Siddiqui wrote:
> Now there are lots of Command and registers that require mocs index
> programming.
> So propagating mocs_index from mocs to gt so that it can be
> used directly without having platform-specific checks.
> 
> Cc: CQ Tang<cq.tang@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c       |  2 ++
>  drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 ++++
>  drivers/gpu/drm/i915/gt/intel_mocs.c     | 13 +++++++++++++
>  drivers/gpu/drm/i915/gt/intel_mocs.h     |  1 +
>  4 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 62d40c9866427..2aeaae036a6f8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -682,6 +682,8 @@ int intel_gt_init(struct intel_gt *gt)
>  		goto err_pm;
>  	}
>  
> +	set_mocs_index(gt);
> +
>  	err = intel_engines_init(gt);
>  	if (err)
>  		goto err_engines;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a81e21bf1bd1a..88601a2d2c229 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -192,6 +192,10 @@ struct intel_gt {
>  
>  		unsigned long mslice_mask;
>  	} info;
> +
> +	struct i915_mocs_index_gt {

I think I mentioned it on the v3 review too, but you can drop the
'i915_mocs_index_gt' name here since we don't reference it anywhere else
in the code that I can see.  Just using an anonymous structure would be
fine.

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +		u8 uc_index;
> +	} mocs;
>  };
>  
>  enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 582c4423b95d6..7ccac15d9a331 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
>  	unsigned int size;
>  	unsigned int n_entries;
>  	const struct drm_i915_mocs_entry *table;
> +	u8 uc_index;
>  };
>  
>  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> @@ -340,14 +341,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  {
>  	unsigned int flags;
>  
> +	memset(table, 0, sizeof(struct drm_i915_mocs_table));
> +
>  	if (IS_DG1(i915)) {
>  		table->size = ARRAY_SIZE(dg1_mocs_table);
>  		table->table = dg1_mocs_table;
> +		table->uc_index = 1;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  	} else if (GRAPHICS_VER(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tgl_mocs_table);
>  		table->table = tgl_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> +		table->uc_index = 3;
>  	} else if (GRAPHICS_VER(i915) == 11) {
>  		table->size  = ARRAY_SIZE(icl_mocs_table);
>  		table->table = icl_mocs_table;
> @@ -504,6 +509,14 @@ static u32 global_mocs_offset(void)
>  	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
>  }
>  
> +void set_mocs_index(struct intel_gt *gt)
> +{
> +	struct drm_i915_mocs_table table;
> +
> +	get_mocs_settings(gt->i915, &table);
> +	gt->mocs.uc_index = table.uc_index;
> +}
> +
>  void intel_mocs_init(struct intel_gt *gt)
>  {
>  	struct drm_i915_mocs_table table;
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index d83274f5163bd..8a09d64b115f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -36,5 +36,6 @@ struct intel_gt;
>  
>  void intel_mocs_init(struct intel_gt *gt);
>  void intel_mocs_init_engine(struct intel_engine_cs *engine);
> +void set_mocs_index(struct intel_gt *gt);
>  
>  #endif
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

[Ayaz A Siddiqui]

Cache-control registers for Command Stream(CMD_CCTL) are used
to set catchability for memory writes and reads outputted by
Command Streamers on Gen12 onward platforms.

These registers need to point un-cached(UC) MOCS index.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h             | 17 ++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 94e1937f8d296..38c66765ff94c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
 				   i915_mmio_reg_offset(RING_NOPID(base)));
 }
 
+/*
+ * engine_fake_wa_init(), a place holder to program the registers
+ * which are not part of a workaround.
+ * Adding programming of those register inside workaround will
+ * allow utilizing wa framework to proper application and verification.
+ */
+static void
+engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
+{
+	u8 mocs;
+
+	if (GRAPHICS_VER(engine->i915) >= 12) {
+	/*
+	 * RING_CMD_CCTL are need to be programed to un-cached
+	 * for memory writes and reads outputted by Command
+	 * Streamers on Gen12 onward platforms.
+	 */
+		mocs = engine->gt->mocs.uc_index;
+		wa_masked_field_set(wal,
+				    RING_CMD_CCTL(engine->mmio_base),
+				    CMD_CCTL_MOCS_MASK,
+				    CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
+	}
+}
 static void
 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
@@ -2080,6 +2104,8 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
 	if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
 		return;
 
+	engine_fake_wa_init(engine, wal);
+
 	if (engine->class == RENDER_CLASS)
 		rcs_engine_wa_init(engine, wal);
 	else
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d4cf1e203ab7..92fda75751eef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2551,6 +2551,23 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
 #define RING_ID(base)		_MMIO((base) + 0x8c)
 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
+
+#define RING_CMD_CCTL(base)	_MMIO((base) + 0xc4)
+/*
+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
+ * The lsb of each can be considered a separate enabling bit for encryption.
+ * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
+ * 15:14 == Reserved => 31:30 are set to 0.
+ */
+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
+#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
+			    CMD_CCTL_READ_OVERRIDE_MASK)
+#define CMD_CCTL_MOCS_OVERRIDE(write, read)				      \
+		(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
+		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

[Matt Roper]

On Fri, Sep 03, 2021 at 12:26:31AM +0530, Ayaz A Siddiqui wrote:
> Cache-control registers for Command Stream(CMD_CCTL) are used
> to set catchability for memory writes and reads outputted by
> Command Streamers on Gen12 onward platforms.
> 
> These registers need to point un-cached(UC) MOCS index.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 17 ++++++++++++++
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 94e1937f8d296..38c66765ff94c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
>  				   i915_mmio_reg_offset(RING_NOPID(base)));
>  }
>  
> +/*
> + * engine_fake_wa_init(), a place holder to program the registers
> + * which are not part of a workaround.

I'd say "...are not part of an official workaround defined by the
hardware team."

> + * Adding programming of those register inside workaround will
> + * allow utilizing wa framework to proper application and verification.
> + */
> +static void
> +engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> +{
> +	u8 mocs;
> +
> +	if (GRAPHICS_VER(engine->i915) >= 12) {
> +	/*
> +	 * RING_CMD_CCTL are need to be programed to un-cached
> +	 * for memory writes and reads outputted by Command
> +	 * Streamers on Gen12 onward platforms.
> +	 */
> +		mocs = engine->gt->mocs.uc_index;

The comment's indentation here looks a bit strange.  It should either be
indented the same amount as the line below it, or it should be moved
above the 'if.'

I think we do have a few other fake workarounds that we can move over to
here eventually (e.g., FtrPerCtxtPreemptionGranularityControl), but we
can track those down and move them over in followup patches.

Aside from the two minor comment tweaks,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +		wa_masked_field_set(wal,
> +				    RING_CMD_CCTL(engine->mmio_base),
> +				    CMD_CCTL_MOCS_MASK,
> +				    CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
> +	}
> +}
>  static void
>  rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
> @@ -2080,6 +2104,8 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
>  	if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
>  		return;
>  
> +	engine_fake_wa_init(engine, wal);
> +
>  	if (engine->class == RENDER_CLASS)
>  		rcs_engine_wa_init(engine, wal);
>  	else
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8d4cf1e203ab7..92fda75751eef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2551,6 +2551,23 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
>  #define RING_ID(base)		_MMIO((base) + 0x8c)
>  #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
> +
> +#define RING_CMD_CCTL(base)	_MMIO((base) + 0xc4)
> +/*
> + * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
> + * The lsb of each can be considered a separate enabling bit for encryption.
> + * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
> + * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
> + * 15:14 == Reserved => 31:30 are set to 0.
> + */
> +#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
> +#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
> +#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
> +			    CMD_CCTL_READ_OVERRIDE_MASK)
> +#define CMD_CCTL_MOCS_OVERRIDE(write, read)				      \
> +		(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
> +		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
> +
>  #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
>  #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
>  #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

[Lucas De Marchi]

On Fri, Sep 03, 2021 at 12:26:31AM +0530, Ayaz A Siddiqui wrote:
>Cache-control registers for Command Stream(CMD_CCTL) are used
>to set catchability for memory writes and reads outputted by
>Command Streamers on Gen12 onward platforms.
>
>These registers need to point un-cached(UC) MOCS index.
>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h             | 17 ++++++++++++++
> 2 files changed, 43 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 94e1937f8d296..38c66765ff94c 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> 				   i915_mmio_reg_offset(RING_NOPID(base)));
> }
>
>+/*
>+ * engine_fake_wa_init(), a place holder to program the registers
>+ * which are not part of a workaround.
>+ * Adding programming of those register inside workaround will
>+ * allow utilizing wa framework to proper application and verification.
>+ */
>+static void
>+engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>+{
>+	u8 mocs;
>+
>+	if (GRAPHICS_VER(engine->i915) >= 12) {

this is including TGL. Shouldn't TGL be the exception here?

Lucas De Marchi

Re: [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

[Matt Roper]

On Thu, Sep 02, 2021 at 03:59:44PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 03, 2021 at 12:26:31AM +0530, Ayaz A Siddiqui wrote:
> > Cache-control registers for Command Stream(CMD_CCTL) are used
> > to set catchability for memory writes and reads outputted by
> > Command Streamers on Gen12 onward platforms.
> > 
> > These registers need to point un-cached(UC) MOCS index.
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h             | 17 ++++++++++++++
> > 2 files changed, 43 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 94e1937f8d296..38c66765ff94c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> > 				   i915_mmio_reg_offset(RING_NOPID(base)));
> > }
> > 
> > +/*
> > + * engine_fake_wa_init(), a place holder to program the registers
> > + * which are not part of a workaround.
> > + * Adding programming of those register inside workaround will
> > + * allow utilizing wa framework to proper application and verification.
> > + */
> > +static void
> > +engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > +{
> > +	u8 mocs;
> > +
> > +	if (GRAPHICS_VER(engine->i915) >= 12) {
> 
> this is including TGL. Shouldn't TGL be the exception here?

Until now we haven't been programming CMD_CCTL, so it's basically been
pointing at entry 0.  On TGL/RKL, undefined entry 0 is treated as UC.
Now that we start setting CMD_CCTL here, it will switch to point at
entry 3, which is explicitly UC, so the behavior shouldn't change, but
the code should be more obvious.

The place where TGL/RKL need an exception is how to setup undefined
table entries (which may be used by userspace; we're not going to point
CMD_CCTL or BLIT_CCTL at any of those now).  In general those undefined
entries should be treated as L3, but for ABI reasons we need to keep
them as UC on TGL/RKL.


Matt

> 
> Lucas De Marchi

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V4 3/6] drm/i915/gt: Set BLIT_CCTL reg to un-cached

[Ayaz A Siddiqui]

Blitter commands which do not have MOCS fields rely on
cacheability of BlitterCacheControlRegister which was mapped
to index 0 by default.Once we changed the MOCS value of
index 0 to L3 WB, tests like gem_linear_blits started failing
due to a change in cacheability from UC to WB.

Program and place the BlitterCacheControlRegister in
build_aux_regs().

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h             |  9 +++++
 2 files changed, 50 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 38c66765ff94c..04fc977ec27fc 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -675,6 +675,41 @@ static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
 	wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
 }
 
+static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine,
+				   struct i915_wa_list *wal)
+{
+	u8 mocs;
+
+	if (engine->class == COPY_ENGINE_CLASS) {
+	/*
+	 * Some blitter commands do not have a field for MOCS, those
+	 * commands will use MOCS index pointed by BLIT_CCTL.
+	 * BLIT_CCTL registers are needed to be programmed to un-cached.
+	 */
+		mocs = engine->gt->mocs.uc_index;
+		wa_masked_field_set(wal,
+				    BLIT_CCTL(engine->mmio_base),
+				    BLIT_CCTL_MASK,
+				    BLIT_CCTL_MOCS(mocs, mocs));
+	}
+}
+
+/*
+ * gen12_ctx_gt_fake_wa_init() aren't programming actual workarounds,
+ * but it programming general context registers.
+ * Adding those context register programming in context workaround
+ * allow us to use the wa framework for proper application and validation.
+ */
+static void
+gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine,
+			  struct i915_wa_list *wal)
+{
+	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+		fakewa_disable_nestedbb_mode(engine, wal);
+
+	gen12_ctx_gt_mocs_init(engine, wal);
+}
+
 static void
 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 			   struct i915_wa_list *wal,
@@ -685,8 +720,12 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 	wa_init_start(wal, name, engine->name);
 
 	/* Applies to all engines */
-	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
-		fakewa_disable_nestedbb_mode(engine, wal);
+	/*
+	 * Fake workarounds are not the actual workaround but
+	 * programming of context registers using workaround framework.
+	 */
+	if (GRAPHICS_VER(i915) >= 12)
+		gen12_ctx_gt_fake_wa_init(engine, wal);
 
 	if (engine->class != RENDER_CLASS)
 		goto done;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92fda75751eef..99cb9321adac9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2568,6 +2568,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 		(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
 		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
 
+#define BLIT_CCTL(base) _MMIO((base) + 0x204)
+#define   BLIT_CCTL_DST_MOCS_MASK       REG_GENMASK(14, 8)
+#define   BLIT_CCTL_SRC_MOCS_MASK       REG_GENMASK(6, 0)
+#define   BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
+			  BLIT_CCTL_SRC_MOCS_MASK)
+#define   BLIT_CCTL_MOCS(dst, src)				       \
+		(REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
+		 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
+
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V4 3/6] drm/i915/gt: Set BLIT_CCTL reg to un-cached

[Matt Roper]

On Fri, Sep 03, 2021 at 12:26:32AM +0530, Ayaz A Siddiqui wrote:
> Blitter commands which do not have MOCS fields rely on
> cacheability of BlitterCacheControlRegister which was mapped
> to index 0 by default.Once we changed the MOCS value of
> index 0 to L3 WB, tests like gem_linear_blits started failing
> due to a change in cacheability from UC to WB.
> 
> Program and place the BlitterCacheControlRegister in
> build_aux_regs().
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h             |  9 +++++
>  2 files changed, 50 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 38c66765ff94c..04fc977ec27fc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -675,6 +675,41 @@ static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
>  	wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
>  }
>  
> +static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine,
> +				   struct i915_wa_list *wal)
> +{
> +	u8 mocs;
> +
> +	if (engine->class == COPY_ENGINE_CLASS) {
> +	/*
> +	 * Some blitter commands do not have a field for MOCS, those
> +	 * commands will use MOCS index pointed by BLIT_CCTL.
> +	 * BLIT_CCTL registers are needed to be programmed to un-cached.
> +	 */
> +		mocs = engine->gt->mocs.uc_index;

As on the previous patch, the indentation of the comment here is unusual.

> +		wa_masked_field_set(wal,

Unlike CMD_CCTL, BLIT_CCTL is _not_ a masked register so we don't want
to use wa_masked_field_set.  Instead this should be a wa_write_clr_set.

> +				    BLIT_CCTL(engine->mmio_base),
> +				    BLIT_CCTL_MASK,
> +				    BLIT_CCTL_MOCS(mocs, mocs));
> +	}
> +}
> +
> +/*
> + * gen12_ctx_gt_fake_wa_init() aren't programming actual workarounds,
> + * but it programming general context registers.
> + * Adding those context register programming in context workaround
> + * allow us to use the wa framework for proper application and validation.
> + */
> +static void
> +gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine,
> +			  struct i915_wa_list *wal)
> +{
> +	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> +		fakewa_disable_nestedbb_mode(engine, wal);
> +
> +	gen12_ctx_gt_mocs_init(engine, wal);
> +}

In the future we can move over WaDisable3DMidCmdPreemption,
WaDisableGPGPUMidCmdPreemption, and probably several others, but we can
do that in a separate series down the road.


After applying the s/wa_masked_field_set/wa_write_clr_set/ fix above,
the rest of the patch looks correct so

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> +
>  static void
>  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  			   struct i915_wa_list *wal,
> @@ -685,8 +720,12 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  	wa_init_start(wal, name, engine->name);
>  
>  	/* Applies to all engines */
> -	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
> -		fakewa_disable_nestedbb_mode(engine, wal);
> +	/*
> +	 * Fake workarounds are not the actual workaround but
> +	 * programming of context registers using workaround framework.
> +	 */
> +	if (GRAPHICS_VER(i915) >= 12)
> +		gen12_ctx_gt_fake_wa_init(engine, wal);
>  
>  	if (engine->class != RENDER_CLASS)
>  		goto done;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 92fda75751eef..99cb9321adac9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2568,6 +2568,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  		(REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
>  		 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
>  
> +#define BLIT_CCTL(base) _MMIO((base) + 0x204)
> +#define   BLIT_CCTL_DST_MOCS_MASK       REG_GENMASK(14, 8)
> +#define   BLIT_CCTL_SRC_MOCS_MASK       REG_GENMASK(6, 0)
> +#define   BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
> +			  BLIT_CCTL_SRC_MOCS_MASK)
> +#define   BLIT_CCTL_MOCS(dst, src)				       \
> +		(REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
> +		 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
> +
>  #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
>  #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
>  #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V4 4/6] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Ayaz A Siddiqui]

Historically we've initialized all undefined/reserved entries in
a platform's MOCS table to the contents of table entry #1 (i.e.,
I915_MOCS_PTE).
Going forward, we can't assume that table entry #1 will always
contain suitable values to use for undefined/reserved table
indices. We'll allow a platform-specific table index to be
selected at table initialization time in these cases.

This new mechanism to select L3 WB entry will be applicable for
all the Gen12+ platforms except TGL and RKL.

Since TGL and RLK are already in production so their mocs settings
are intact to avoid ABI break.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 46 ++++++++++++++++------------
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 7ccac15d9a331..0fdadefdabc29 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
 	unsigned int n_entries;
 	const struct drm_i915_mocs_entry *table;
 	u8 uc_index;
+	u8 unused_entries_index;
 };
 
 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
@@ -89,18 +90,25 @@ struct drm_i915_mocs_table {
  *
  * Entries not part of the following tables are undefined as far as
  * userspace is concerned and shouldn't be relied upon.  For Gen < 12
- * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
- * PTE and will be initialized to an invalid value.
+ * they will be initialized to PTE. Gen >= 12 don't have a setting for
+ * PTE and those platforms except TGL/RKL will be initialized L3 WB to
+ * catch accidental use of reserved and unused mocs indexes.
  *
  * The last few entries are reserved by the hardware. For ICL+ they
  * should be initialized according to bspec and never used, for older
  * platforms they should never be written to.
  *
- * NOTE: These tables are part of bspec and defined as part of hardware
+ * NOTE1: These tables are part of bspec and defined as part of hardware
  *       interface for ICL+. For older platforms, they are part of kernel
  *       ABI. It is expected that, for specific hardware platform, existing
  *       entries will remain constant and the table will only be updated by
  *       adding new entries, filling unused positions.
+ *
+ * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
+ *       indices have been set to L3 WB. These reserved entries should never
+ *       be used, they may be changed to low performant variants with better
+ *       coherency in the future if more entries are needed.
+ *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
  */
 #define GEN9_MOCS_ENTRIES \
 	MOCS_ENTRY(I915_MOCS_UNCACHED, \
@@ -283,17 +291,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
 };
 
 static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
-	/* Error */
-	MOCS_ENTRY(0, 0, L3_0_DIRECT),
 
 	/* UC */
 	MOCS_ENTRY(1, 0, L3_1_UC),
-
-	/* Reserved */
-	MOCS_ENTRY(2, 0, L3_0_DIRECT),
-	MOCS_ENTRY(3, 0, L3_0_DIRECT),
-	MOCS_ENTRY(4, 0, L3_0_DIRECT),
-
 	/* WB - L3 */
 	MOCS_ENTRY(5, 0, L3_3_WB),
 	/* WB - L3 50% */
@@ -343,16 +343,22 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 
 	memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
+	table->unused_entries_index = I915_MOCS_PTE;
 	if (IS_DG1(i915)) {
 		table->size = ARRAY_SIZE(dg1_mocs_table);
 		table->table = dg1_mocs_table;
 		table->uc_index = 1;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+		table->uc_index = 1;
+		table->unused_entries_index = 5;
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tgl_mocs_table);
 		table->table = tgl_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->uc_index = 3;
+		/* For TGL/RKL, Can't be changed now for ABI reasons */
+		if (!IS_TIGERLAKE(i915) || !IS_ROCKETLAKE(i915))
+			table->unused_entries_index = 2;
 	} else if (GRAPHICS_VER(i915) == 11) {
 		table->size  = ARRAY_SIZE(icl_mocs_table);
 		table->table = icl_mocs_table;
@@ -398,16 +404,16 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 }
 
 /*
- * Get control_value from MOCS entry taking into account when it's not used:
- * I915_MOCS_PTE's value is returned in this case.
+ * Get control_value from MOCS entry taking into account when it's not used
+ * then if unused_entries_index is non-zero then its value will be returned
+ * otherwise I915_MOCS_PTE's value is returned in this case.
  */
 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
 			     unsigned int index)
 {
 	if (index < table->size && table->table[index].used)
 		return table->table[index].control_value;
-
-	return table->table[I915_MOCS_PTE].control_value;
+	return table->table[table->unused_entries_index].control_value;
 }
 
 #define for_each_mocs(mocs, t, i) \
@@ -422,6 +428,8 @@ static void __init_mocs_table(struct intel_uncore *uncore,
 	unsigned int i;
 	u32 mocs;
 
+	drm_WARN_ONCE(&uncore->i915->drm, !table->unused_entries_index,
+		      "Unused entries index should have been defined\n");
 	for_each_mocs(mocs, table, i)
 		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
 }
@@ -448,16 +456,16 @@ static void init_mocs_table(struct intel_engine_cs *engine,
 }
 
 /*
- * Get l3cc_value from MOCS entry taking into account when it's not used:
- * I915_MOCS_PTE's value is returned in this case.
+ * Get l3cc_value from MOCS entry taking into account when it's not used
+ * then if unused_entries_index is not zero then its value will be returned
+ * otherwise I915_MOCS_PTE's value is returned in this case.
  */
 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 			  unsigned int index)
 {
 	if (index < table->size && table->table[index].used)
 		return table->table[index].l3cc_value;
-
-	return table->table[I915_MOCS_PTE].l3cc_value;
+	return table->table[table->unused_entries_index].l3cc_value;
 }
 
 static u32 l3cc_combine(u16 low, u16 high)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V4 4/6] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Matt Roper]

On Fri, Sep 03, 2021 at 12:26:33AM +0530, Ayaz A Siddiqui wrote:
> Historically we've initialized all undefined/reserved entries in
> a platform's MOCS table to the contents of table entry #1 (i.e.,
> I915_MOCS_PTE).
> Going forward, we can't assume that table entry #1 will always
> contain suitable values to use for undefined/reserved table
> indices. We'll allow a platform-specific table index to be
> selected at table initialization time in these cases.
> 
> This new mechanism to select L3 WB entry will be applicable for
> all the Gen12+ platforms except TGL and RKL.
> 
> Since TGL and RLK are already in production so their mocs settings
> are intact to avoid ABI break.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 46 ++++++++++++++++------------
>  1 file changed, 27 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 7ccac15d9a331..0fdadefdabc29 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
>  	unsigned int n_entries;
>  	const struct drm_i915_mocs_entry *table;
>  	u8 uc_index;
> +	u8 unused_entries_index;
>  };
>  
>  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> @@ -89,18 +90,25 @@ struct drm_i915_mocs_table {
>   *
>   * Entries not part of the following tables are undefined as far as
>   * userspace is concerned and shouldn't be relied upon.  For Gen < 12
> - * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
> - * PTE and will be initialized to an invalid value.
> + * they will be initialized to PTE. Gen >= 12 don't have a setting for
> + * PTE and those platforms except TGL/RKL will be initialized L3 WB to
> + * catch accidental use of reserved and unused mocs indexes.
>   *
>   * The last few entries are reserved by the hardware. For ICL+ they
>   * should be initialized according to bspec and never used, for older
>   * platforms they should never be written to.
>   *
> - * NOTE: These tables are part of bspec and defined as part of hardware
> + * NOTE1: These tables are part of bspec and defined as part of hardware
>   *       interface for ICL+. For older platforms, they are part of kernel
>   *       ABI. It is expected that, for specific hardware platform, existing
>   *       entries will remain constant and the table will only be updated by
>   *       adding new entries, filling unused positions.
> + *
> + * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
> + *       indices have been set to L3 WB. These reserved entries should never
> + *       be used, they may be changed to low performant variants with better
> + *       coherency in the future if more entries are needed.
> + *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
>   */
>  #define GEN9_MOCS_ENTRIES \
>  	MOCS_ENTRY(I915_MOCS_UNCACHED, \
> @@ -283,17 +291,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
>  };
>  
>  static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> -	/* Error */
> -	MOCS_ENTRY(0, 0, L3_0_DIRECT),
>  
>  	/* UC */
>  	MOCS_ENTRY(1, 0, L3_1_UC),
> -
> -	/* Reserved */
> -	MOCS_ENTRY(2, 0, L3_0_DIRECT),
> -	MOCS_ENTRY(3, 0, L3_0_DIRECT),
> -	MOCS_ENTRY(4, 0, L3_0_DIRECT),
> -
>  	/* WB - L3 */
>  	MOCS_ENTRY(5, 0, L3_3_WB),
>  	/* WB - L3 50% */
> @@ -343,16 +343,22 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  
>  	memset(table, 0, sizeof(struct drm_i915_mocs_table));
>  
> +	table->unused_entries_index = I915_MOCS_PTE;
>  	if (IS_DG1(i915)) {
>  		table->size = ARRAY_SIZE(dg1_mocs_table);
>  		table->table = dg1_mocs_table;
>  		table->uc_index = 1;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> +		table->uc_index = 1;
> +		table->unused_entries_index = 5;
>  	} else if (GRAPHICS_VER(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tgl_mocs_table);
>  		table->table = tgl_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->uc_index = 3;
> +		/* For TGL/RKL, Can't be changed now for ABI reasons */
> +		if (!IS_TIGERLAKE(i915) || !IS_ROCKETLAKE(i915))

I think you meant '&&' here rather than '||' (otherwise this statement
will always evaluate to true).

With that fixed,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> +			table->unused_entries_index = 2;
>  	} else if (GRAPHICS_VER(i915) == 11) {
>  		table->size  = ARRAY_SIZE(icl_mocs_table);
>  		table->table = icl_mocs_table;
> @@ -398,16 +404,16 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  }
>  
>  /*
> - * Get control_value from MOCS entry taking into account when it's not used:
> - * I915_MOCS_PTE's value is returned in this case.
> + * Get control_value from MOCS entry taking into account when it's not used
> + * then if unused_entries_index is non-zero then its value will be returned
> + * otherwise I915_MOCS_PTE's value is returned in this case.
>   */
>  static u32 get_entry_control(const struct drm_i915_mocs_table *table,
>  			     unsigned int index)
>  {
>  	if (index < table->size && table->table[index].used)
>  		return table->table[index].control_value;
> -
> -	return table->table[I915_MOCS_PTE].control_value;
> +	return table->table[table->unused_entries_index].control_value;
>  }
>  
>  #define for_each_mocs(mocs, t, i) \
> @@ -422,6 +428,8 @@ static void __init_mocs_table(struct intel_uncore *uncore,
>  	unsigned int i;
>  	u32 mocs;
>  
> +	drm_WARN_ONCE(&uncore->i915->drm, !table->unused_entries_index,
> +		      "Unused entries index should have been defined\n");
>  	for_each_mocs(mocs, table, i)
>  		intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
>  }
> @@ -448,16 +456,16 @@ static void init_mocs_table(struct intel_engine_cs *engine,
>  }
>  
>  /*
> - * Get l3cc_value from MOCS entry taking into account when it's not used:
> - * I915_MOCS_PTE's value is returned in this case.
> + * Get l3cc_value from MOCS entry taking into account when it's not used
> + * then if unused_entries_index is not zero then its value will be returned
> + * otherwise I915_MOCS_PTE's value is returned in this case.
>   */
>  static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
>  			  unsigned int index)
>  {
>  	if (index < table->size && table->table[index].used)
>  		return table->table[index].l3cc_value;
> -
> -	return table->table[I915_MOCS_PTE].l3cc_value;
> +	return table->table[table->unused_entries_index].l3cc_value;
>  }
>  
>  static u32 l3cc_combine(u16 low, u16 high)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V4 5/6] drm/i915/gt: Initialize L3CC table in mocs init

[Ayaz A Siddiqui]

From: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>

Initialize the L3CC table as part of mocs initialization to program
LNCFCMOCSx registers so that the mocs settings are available for
selection for subsequent memory transactions in the driver load path.

Apart from the above requirement, this patch is also needed for platforms
which does not have any renderer engine.
We have verified that value programmed LNCFCMOCSx is retained for
XEHP-SDV, while we lose those values for DG1/TGL.

Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 0fdadefdabc29..df8aa761d2d7f 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -481,10 +481,9 @@ static u32 l3cc_combine(u16 low, u16 high)
 	     0; \
 	     i++)
 
-static void init_l3cc_table(struct intel_engine_cs *engine,
+static void init_l3cc_table(struct intel_uncore *uncore,
 			    const struct drm_i915_mocs_table *table)
 {
-	struct intel_uncore *uncore = engine->uncore;
 	unsigned int i;
 	u32 l3cc;
 
@@ -509,7 +508,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 		init_mocs_table(engine, &table);
 
 	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
-		init_l3cc_table(engine, &table);
+		init_l3cc_table(engine->uncore, &table);
 }
 
 static u32 global_mocs_offset(void)
@@ -536,6 +535,14 @@ void intel_mocs_init(struct intel_gt *gt)
 	flags = get_mocs_settings(gt->i915, &table);
 	if (flags & HAS_GLOBAL_MOCS)
 		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
+
+	/*
+	 * Initialize the L3CC table as part of mocs initalization to make
+	 * sure the LNCFCMOCSx registers are programmed for the subsequent
+	 * memory transactions including guc transactions
+	 */
+	if (flags & HAS_RENDER_L3CC)
+		init_l3cc_table(gt->uncore, &table);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V4 5/6] drm/i915/gt: Initialize L3CC table in mocs init

[Matt Roper]

On Fri, Sep 03, 2021 at 12:26:34AM +0530, Ayaz A Siddiqui wrote:
> From: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
> 
> Initialize the L3CC table as part of mocs initialization to program
> LNCFCMOCSx registers so that the mocs settings are available for
> selection for subsequent memory transactions in the driver load path.
> 
> Apart from the above requirement, this patch is also needed for platforms
> which does not have any renderer engine.
> We have verified that value programmed LNCFCMOCSx is retained for
> XEHP-SDV, while we lose those values for DG1/TGL.

Just FYI, I believe the difference here isn't the platform itself, but
rather GuC vs execlists.  With GuC submission (currently enabled by
default on XeHP and beyond), the LNCFMOCS registers are added to the
GuC's save/restore list (in guc_mmio_regset_init()) so that they're
always saved/restored across resets without any special action by i915.
But when we're using execlists, as is the default on TGL and (for now)
DG1, the driver needs to explicitly re-write the registers after a
reset, which is what the call inside intel_mocs_init_engine() takes care
of.

You might want to clarify that slightly in the commit message, but
otherwise

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 0fdadefdabc29..df8aa761d2d7f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -481,10 +481,9 @@ static u32 l3cc_combine(u16 low, u16 high)
>  	     0; \
>  	     i++)
>  
> -static void init_l3cc_table(struct intel_engine_cs *engine,
> +static void init_l3cc_table(struct intel_uncore *uncore,
>  			    const struct drm_i915_mocs_table *table)
>  {
> -	struct intel_uncore *uncore = engine->uncore;
>  	unsigned int i;
>  	u32 l3cc;
>  
> @@ -509,7 +508,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>  		init_mocs_table(engine, &table);
>  
>  	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> -		init_l3cc_table(engine, &table);
> +		init_l3cc_table(engine->uncore, &table);
>  }
>  
>  static u32 global_mocs_offset(void)
> @@ -536,6 +535,14 @@ void intel_mocs_init(struct intel_gt *gt)
>  	flags = get_mocs_settings(gt->i915, &table);
>  	if (flags & HAS_GLOBAL_MOCS)
>  		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
> +
> +	/*
> +	 * Initialize the L3CC table as part of mocs initalization to make
> +	 * sure the LNCFCMOCSx registers are programmed for the subsequent
> +	 * memory transactions including guc transactions
> +	 */
> +	if (flags & HAS_RENDER_L3CC)
> +		init_l3cc_table(gt->uncore, &table);
>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V4 6/6] drm/i915/selftest: Remove Renderer class check for l3cc table read

[Ayaz A Siddiqui]

Some platform like XEHPSVD does not have Renderer engines. since
read_l3cc_table() is guarded by renderer class due to that check
of L3CC table was not being performed on those platforms.

Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index 13d25bf2a94aa..c3a48a06c37ee 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -237,7 +237,7 @@ static int check_mocs_engine(struct live_mocs *arg,
 	offset = i915_ggtt_offset(vma);
 	if (!err)
 		err = read_mocs_table(rq, arg->mocs, &offset);
-	if (!err && ce->engine->class == RENDER_CLASS)
+	if (!err)
 		err = read_l3cc_table(rq, arg->l3cc, &offset);
 	offset -= i915_ggtt_offset(vma);
 	GEM_BUG_ON(offset > PAGE_SIZE);
@@ -250,7 +250,7 @@ static int check_mocs_engine(struct live_mocs *arg,
 	vaddr = arg->vaddr;
 	if (!err)
 		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
-	if (!err && ce->engine->class == RENDER_CLASS)
+	if (!err)
 		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
 	if (err)
 		return err;
-- 
2.26.2

Re: [Intel-gfx] [PATCH V4 6/6] drm/i915/selftest: Remove Renderer class check for l3cc table read

[Matt Roper]

On Fri, Sep 03, 2021 at 12:26:35AM +0530, Ayaz A Siddiqui wrote:
> Some platform like XEHPSVD does not have Renderer engines. since
> read_l3cc_table() is guarded by renderer class due to that check
> of L3CC table was not being performed on those platforms.
> 

Yeah, Xe_HP SDV doesn't have an RCS engine, but it does have compute
engines (CCS) that fill the same role.  I have the initial patches to
enable the compute engine ready to send upstream; just waiting on one of
the userspace drivers (either Mesa or OCL) to have their own merge
requests ready so that I can reference that as our userspace consumer.

Maybe we should hold off on this patch for now and change this to

        if (!err && engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)

which will apply to both the render and compute engines at that point?
Or, since these registers are global and not engine-specific, we could
adjust the code to just do this once, with whatever the GT's first
engine happens to be (doesn't matter if it's RCS, CCS, BCS, VCS, or
VECS) so that we're not repeating the same process multiple times
needlessly?


Matt

> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index 13d25bf2a94aa..c3a48a06c37ee 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -237,7 +237,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  	offset = i915_ggtt_offset(vma);
>  	if (!err)
>  		err = read_mocs_table(rq, arg->mocs, &offset);
> -	if (!err && ce->engine->class == RENDER_CLASS)
> +	if (!err)
>  		err = read_l3cc_table(rq, arg->l3cc, &offset);
>  	offset -= i915_ggtt_offset(vma);
>  	GEM_BUG_ON(offset > PAGE_SIZE);
> @@ -250,7 +250,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  	vaddr = arg->vaddr;
>  	if (!err)
>  		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
> -	if (!err && ce->engine->class == RENDER_CLASS)
> +	if (!err)
>  		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
>  	if (err)
>  		return err;
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB
URL   : https://patchwork.freedesktop.org/series/94295/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2769 bytes --]

== Series Details ==

Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB
URL   : https://patchwork.freedesktop.org/series/94295/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10548 -> Patchwork_20946
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20946 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20946, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20946:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_timelines:
    - fi-rkl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10548/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html

  
Known issues
------------

  Here are the changes found in Patchwork_20946 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@runner@aborted:
    - fi-rkl-guc:         NOTRUN -> [FAIL][3] ([i915#3928])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/fi-rkl-guc/igt@runner@aborted.html

  
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928


Participating hosts (48 -> 39)
------------------------------

  Missing    (9): fi-ilk-m540 bat-adls-5 fi-hsw-4200u bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-bsw-kefka fi-bdw-samus bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10548 -> Patchwork_20946

  CI-20190529: 20190529
  CI_DRM_10548: 50be9d6f82904be755ea5b04efbd6c5e19e2d945 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6197: 40888f97a6ad219f4ed48a1830d0ef3c9617d006 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20946: aac515f419092c6c22c426c25bc89ac4eb63b800 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

aac515f41909 drm/i915/selftest: Remove Renderer class check for l3cc table read
8f930253133f drm/i915/gt: Initialize L3CC table in mocs init
cbe983e4de1e drm/i915/gt: Initialize unused MOCS entries with device specific values
ee72b0d50d16 drm/i915/gt: Set BLIT_CCTL reg to un-cached
ae6608c212cd drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
677e40246b6e drm/i915/gt: Add support of mocs propagation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/index.html

[-- Attachment #2: Type: text/html, Size: 3431 bytes --]

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Siddiqui, Ayaz A]

[-- Attachment #1.1: Type: text/plain, Size: 6809 bytes --]

I ran “igt@i915_selftest@live@gt_timelines multiple time with my changes but issue is not reproduced.
My code base is on “drm-tip: 2021y-08m-30d-01h-19m-56s UTC integration manifest” and test was done with enable_guc=3
=======
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.306s)
Subtest live: SUCCESS (20.306s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.289s)
Subtest live: SUCCESS (20.290s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.291s)
Subtest live: SUCCESS (20.292s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.433s)
Subtest live: SUCCESS (20.434s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.480s)
Subtest live: SUCCESS (20.481s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.298s)
Subtest live: SUCCESS (20.299s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.257s)
Subtest live: SUCCESS (20.258s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.336s)
Subtest live: SUCCESS (20.337s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.446s)
Subtest live: SUCCESS (20.447s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.328s)
Subtest live: SUCCESS (20.329s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$ sudo ./build/tests/i915_selftest --r live --dy gt_timelines
IGT-Version: 1.26-g925655c30 (x86_64) (Linux: 5.14.0-uc-mocs-aas-1 x86_64)
Starting subtest: live
Starting dynamic subtest: gt_timelines
Dynamic subtest gt_timelines: SUCCESS (20.335s)
Subtest live: SUCCESS (20.336s)
gta@DUT2020-RKLS:~/ayaz/igt-gpu-tools.internal-rebasing$


From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Friday, September 3, 2021 1:41 AM
To: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/gt: Initialize unused MOCS entries to L3_WB

Patch Details
Series:
drm/i915/gt: Initialize unused MOCS entries to L3_WB
URL:
https://patchwork.freedesktop.org/series/94295/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/index.html
CI Bug Log - changes from CI_DRM_10548 -> Patchwork_20946
Summary

FAILURE

Serious unknown changes coming with Patchwork_20946 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20946, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_20946:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@gt_timelines:

     *   fi-rkl-guc: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10548/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html>

Known issues

Here are the changes found in Patchwork_20946 that come from known issues:

IGT changes
Issues hit

  *   igt@runner@aborted:

     *   fi-rkl-guc: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20946/fi-rkl-guc/igt@runner@aborted.html> (i915#3928<https://gitlab.freedesktop.org/drm/intel/issues/3928>)

Participating hosts (48 -> 39)

Missing (9): fi-ilk-m540 bat-adls-5 fi-hsw-4200u bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-bsw-kefka fi-bdw-samus bat-jsl-1

Build changes

  *   Linux: CI_DRM_10548 -> Patchwork_20946

CI-20190529: 20190529
CI_DRM_10548: 50be9d6f82904be755ea5b04efbd6c5e19e2d945 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6197: 40888f97a6ad219f4ed48a1830d0ef3c9617d006 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20946: aac515f419092c6c22c426c25bc89ac4eb63b800 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

aac515f41909 drm/i915/selftest: Remove Renderer class check for l3cc table read
8f930253133f drm/i915/gt: Initialize L3CC table in mocs init
cbe983e4de1e drm/i915/gt: Initialize unused MOCS entries with device specific values
ee72b0d50d16 drm/i915/gt: Set BLIT_CCTL reg to un-cached
ae6608c212cd drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
677e40246b6e drm/i915/gt: Add support of mocs propagation

[-- Attachment #1.2: Type: text/html, Size: 27417 bytes --]

[-- Attachment #2: gt_timeline_dmesg.txt --]
[-- Type: text/plain, Size: 57726 bytes --]

[ 2148.384367] [IGT] i915_selftest: executing
[ 2148.416832] [IGT] i915_selftest: starting subtest live
[ 2148.416956] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 2148.484221] Setting dangerous option force_probe - tainting kernel
[ 2148.484229] Setting dangerous option enable_guc - tainting kernel
[ 2148.484232] Setting dangerous option live_selftests - tainting kernel
[ 2148.513775] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2148.513784] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2148.513786] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2148.513789] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2148.524895] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 2148.524904] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 2148.543359] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 2148.545152] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 2150.074797] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 2150.195408] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 2150.195411] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 2150.195412] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 2150.196874] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 2150.205593] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 2150.220482] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 2150.222990] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input12
[ 2150.223710] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2150.224344] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2150.225176] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 2150.225179] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 2150.225180] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 2150.225183] i915: Performing live selftests with st_random_seed=0x979171fb st_timeout=500
[ 2150.225184] i915: Running gt_timelines
[ 2150.225196] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 2151.415992] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2151.416000] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2151.416001] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2151.416003] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2152.251920] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 2159.519748] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 2166.520738] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 2166.526733] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 2167.032982] rcs0: simulated 99 wraps
[ 2167.535183] bcs0: simulated 106 wraps
[ 2168.038637] vcs0: simulated 99 wraps
[ 2168.540819] vecs0: simulated 102 wraps
[ 2168.566521] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 2168.579691] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 2168.722757] i915: probe of 0000:00:02.0 failed with error -25
[ 2168.861239] [IGT] i915_selftest: exiting, ret=0
[ 2173.303977] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2173.304144] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2173.304150] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2173.304156] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2187.766523] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2187.766543] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2187.766550] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2187.766556] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2213.901229] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2213.901388] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2213.901395] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2213.901401] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2214.389594] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2214.389612] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2214.389618] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2214.389624] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2224.654130] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2224.654368] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2224.654376] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2224.654383] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2240.013414] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2240.013580] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2240.013586] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2240.013592] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2321.930886] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2321.931047] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2321.931053] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2321.931059] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2329.074968] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2329.075132] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2329.075139] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2329.075145] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2389.007632] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2389.007652] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2389.007658] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2389.007664] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2394.633830] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2394.633838] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2394.633840] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2394.633842] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2394.642393] [IGT] i915_selftest: executing
[ 2394.655745] [IGT] i915_selftest: starting subtest live
[ 2394.655919] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 2394.721688] Setting dangerous option force_probe - tainting kernel
[ 2394.721696] Setting dangerous option enable_guc - tainting kernel
[ 2394.721700] Setting dangerous option live_selftests - tainting kernel
[ 2394.762189] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 2394.762198] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 2394.776772] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 2394.779691] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 2396.278370] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 2396.400284] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 2396.400289] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 2396.400290] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 2396.401426] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 2396.409950] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 2396.423074] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 2396.425468] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input13
[ 2396.426121] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2396.427009] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2396.427526] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 2396.427529] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 2396.427530] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 2396.427532] i915: Performing live selftests with st_random_seed=0x9ec75d46 st_timeout=500
[ 2396.427534] i915: Running gt_timelines
[ 2396.427546] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 2398.454623] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 2405.663737] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 2412.623768] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 2412.629705] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 2413.135697] rcs0: simulated 97 wraps
[ 2413.639085] bcs0: simulated 106 wraps
[ 2414.143736] vcs0: simulated 102 wraps
[ 2414.649835] vecs0: simulated 100 wraps
[ 2414.673313] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 2414.684027] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 2414.825596] i915: probe of 0000:00:02.0 failed with error -25
[ 2414.962923] [IGT] i915_selftest: exiting, ret=0
[ 2418.595832] [IGT] i915_selftest: executing
[ 2418.642966] [IGT] i915_selftest: starting subtest live
[ 2418.643439] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 2418.715893] Setting dangerous option force_probe - tainting kernel
[ 2418.715901] Setting dangerous option enable_guc - tainting kernel
[ 2418.715919] Setting dangerous option live_selftests - tainting kernel
[ 2418.756439] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 2418.756449] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 2418.770445] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 2418.771803] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 2420.276914] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 2420.397567] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 2420.397570] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 2420.397571] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 2420.399021] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 2420.407971] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 2420.422321] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 2420.424631] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input14
[ 2420.425534] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2420.426061] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2420.427058] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 2420.427061] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 2420.427063] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 2420.427066] i915: Performing live selftests with st_random_seed=0x3ce01cd9 st_timeout=500
[ 2420.427069] i915: Running gt_timelines
[ 2420.427085] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 2422.451090] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 2429.606515] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 2436.585548] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 2436.591607] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 2437.094848] rcs0: simulated 96 wraps
[ 2437.601910] bcs0: simulated 106 wraps
[ 2438.106708] vcs0: simulated 102 wraps
[ 2438.608919] vecs0: simulated 102 wraps
[ 2438.629762] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 2438.640487] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 2438.743215] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2438.743244] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2438.743254] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2438.743264] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2438.798079] i915: probe of 0000:00:02.0 failed with error -25
[ 2438.934332] [IGT] i915_selftest: exiting, ret=0
[ 2442.004289] [IGT] i915_selftest: executing
[ 2442.050887] [IGT] i915_selftest: starting subtest live
[ 2442.051274] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 2442.118001] Setting dangerous option force_probe - tainting kernel
[ 2442.118009] Setting dangerous option enable_guc - tainting kernel
[ 2442.118013] Setting dangerous option live_selftests - tainting kernel
[ 2442.158506] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 2442.158515] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 2442.173643] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 2442.176843] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 2443.700927] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 2443.826193] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 2443.826196] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 2443.826197] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 2443.827683] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 2443.836527] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 2443.851023] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 2443.853426] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input15
[ 2443.854054] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2443.855460] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 2443.855462] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 2443.855464] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 2443.855465] i915: Performing live selftests with st_random_seed=0x9fe86a1f st_timeout=500
[ 2443.855467] i915: Running gt_timelines
[ 2443.855478] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 2443.855920] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 2445.881601] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 2453.051528] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 2460.011702] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 2460.017771] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 2460.523375] rcs0: simulated 101 wraps
[ 2461.025545] bcs0: simulated 106 wraps
[ 2461.528959] vcs0: simulated 101 wraps
[ 2462.032397] vecs0: simulated 99 wraps
[ 2462.056223] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 2462.067024] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 2462.199337] i915: probe of 0000:00:02.0 failed with error -25
[ 2462.344001] [IGT] i915_selftest: exiting, ret=0
[ 2529.798427] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2529.798448] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2529.798454] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2529.798460] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2574.318062] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2574.318081] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2574.318087] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2574.318094] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2585.092775] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2585.092939] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2585.092946] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2585.092952] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2619.398322] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2619.398343] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2619.398349] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2619.398355] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2630.662840] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2630.662929] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2630.662936] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2630.662942] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2759.703017] kworker/dying (28) used greatest stack depth: 10992 bytes left
[ 2814.464773] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2814.464793] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2814.464800] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2814.464806] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2819.590536] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2819.590556] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2819.590562] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2819.590568] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2825.218224] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2825.218244] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2825.218251] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2825.218257] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2844.158678] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2844.158698] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2844.158705] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2844.158711] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2846.182196] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2846.182213] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2846.182220] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2846.182226] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2865.151920] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2865.151939] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2865.151945] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2865.151952] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 2883.557246] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 2883.557413] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 2883.557419] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 2883.557425] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3024.809395] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3024.809415] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3024.809422] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3024.809429] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3178.997191] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3178.997359] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3178.997365] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3178.997371] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3211.254926] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3211.255154] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3211.255161] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3211.255167] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3223.028451] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3223.028471] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3223.028477] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3223.028483] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3242.489376] [IGT] i915_selftest: executing
[ 3242.502972] [IGT] i915_selftest: starting subtest live
[ 3242.503118] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3242.573525] Setting dangerous option force_probe - tainting kernel
[ 3242.573533] Setting dangerous option enable_guc - tainting kernel
[ 3242.573536] Setting dangerous option live_selftests - tainting kernel
[ 3242.613916] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3242.613925] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3242.626358] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3242.629432] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3244.128580] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3244.251950] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3244.251954] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3244.251956] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3244.253078] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3244.261997] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3244.276278] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3244.278546] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input16
[ 3244.279169] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3244.279687] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3244.280801] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3244.280805] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3244.280807] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3244.280810] i915: Performing live selftests with st_random_seed=0xa4a3dd1e st_timeout=500
[ 3244.280813] i915: Running gt_timelines
[ 3244.280830] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3246.304331] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3253.575124] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3253.725852] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3253.725872] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3253.725874] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3253.725876] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3260.604410] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3260.610561] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3261.114045] rcs0: simulated 98 wraps
[ 3261.619910] bcs0: simulated 104 wraps
[ 3262.124581] vcs0: simulated 102 wraps
[ 3262.626784] vecs0: simulated 102 wraps
[ 3262.647745] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3262.658428] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3262.798283] i915: probe of 0000:00:02.0 failed with error -25
[ 3262.937897] [IGT] i915_selftest: exiting, ret=0
[ 3277.787580] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3277.787600] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3277.787606] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3277.787612] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3303.922522] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3303.922541] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3303.922547] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3303.922553] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3318.234154] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3318.234313] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3318.234320] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3318.234326] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3360.729166] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3360.729187] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3360.729193] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3360.729200] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3379.184567] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3379.184588] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3379.184594] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3379.184601] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3433.474206] [IGT] i915_selftest: executing
[ 3433.492366] [IGT] i915_selftest: starting subtest live
[ 3433.492607] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3433.560959] Setting dangerous option force_probe - tainting kernel
[ 3433.560966] Setting dangerous option enable_guc - tainting kernel
[ 3433.560970] Setting dangerous option live_selftests - tainting kernel
[ 3433.600994] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3433.601003] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3433.615214] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3433.618266] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3435.163422] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3435.284850] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3435.284854] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3435.284855] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3435.286341] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3435.294350] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3435.307506] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3435.309851] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input17
[ 3435.310514] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3435.311007] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3435.311904] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3435.311907] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3435.311908] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3435.311911] i915: Performing live selftests with st_random_seed=0xe4ba87cc st_timeout=500
[ 3435.311912] i915: Running gt_timelines
[ 3435.311925] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3437.339252] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3444.685868] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3449.840537] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3449.840547] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3449.840549] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3449.840552] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3451.672380] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3451.678460] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3452.183943] rcs0: simulated 100 wraps
[ 3452.688563] bcs0: simulated 107 wraps
[ 3453.189574] vcs0: simulated 102 wraps
[ 3453.692029] vecs0: simulated 102 wraps
[ 3453.719794] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3453.730614] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3453.847871] i915: probe of 0000:00:02.0 failed with error -25
[ 3453.974512] [IGT] i915_selftest: exiting, ret=0
[ 3458.491319] [IGT] i915_selftest: executing
[ 3458.538291] [IGT] i915_selftest: starting subtest live
[ 3458.538838] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3458.606873] Setting dangerous option force_probe - tainting kernel
[ 3458.606880] Setting dangerous option enable_guc - tainting kernel
[ 3458.606884] Setting dangerous option live_selftests - tainting kernel
[ 3458.647269] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3458.647279] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3458.659605] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3458.662838] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3460.186840] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3460.310227] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3460.310230] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3460.310232] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3460.311324] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3460.319486] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3460.334066] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3460.336550] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input18
[ 3460.337198] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3460.337995] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3460.338801] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3460.338804] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3460.338807] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3460.338810] i915: Performing live selftests with st_random_seed=0x3651583c st_timeout=500
[ 3460.338812] i915: Running gt_timelines
[ 3460.338829] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3462.360469] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3469.488551] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3476.523242] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3476.529353] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3477.035138] rcs0: simulated 98 wraps
[ 3477.539881] bcs0: simulated 104 wraps
[ 3478.045674] vcs0: simulated 102 wraps
[ 3478.549079] vecs0: simulated 102 wraps
[ 3478.567984] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3478.577612] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3478.711167] i915: probe of 0000:00:02.0 failed with error -25
[ 3478.838672] [IGT] i915_selftest: exiting, ret=0
[ 3488.392125] [IGT] i915_selftest: executing
[ 3488.405132] [IGT] i915_selftest: starting subtest live
[ 3488.405255] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3488.469185] Setting dangerous option force_probe - tainting kernel
[ 3488.469195] Setting dangerous option enable_guc - tainting kernel
[ 3488.469199] Setting dangerous option live_selftests - tainting kernel
[ 3488.509639] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3488.509648] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3488.524169] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3488.525506] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3490.010166] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3490.133382] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3490.133386] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3490.133388] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3490.134512] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3490.143094] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3490.162378] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3490.164772] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input19
[ 3490.165580] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3490.166100] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3490.167203] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3490.167206] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3490.167208] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3490.167211] i915: Performing live selftests with st_random_seed=0xdf120567 st_timeout=500
[ 3490.167213] i915: Running gt_timelines
[ 3490.167229] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3492.194781] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3499.371530] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3506.327700] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3506.333807] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3506.838010] rcs0: simulated 99 wraps
[ 3507.343848] bcs0: simulated 105 wraps
[ 3507.847251] vcs0: simulated 102 wraps
[ 3508.353116] vecs0: simulated 103 wraps
[ 3508.383268] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3508.395786] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3508.528389] i915: probe of 0000:00:02.0 failed with error -25
[ 3508.663857] [IGT] i915_selftest: exiting, ret=0
[ 3508.781900] [IGT] i915_selftest: executing
[ 3508.828014] [IGT] i915_selftest: starting subtest live
[ 3508.828512] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3508.899813] Setting dangerous option force_probe - tainting kernel
[ 3508.899821] Setting dangerous option enable_guc - tainting kernel
[ 3508.899825] Setting dangerous option live_selftests - tainting kernel
[ 3508.940251] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3508.940260] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3508.954309] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3508.957527] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3510.489334] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3510.610874] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3510.610878] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3510.610879] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3510.611976] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3510.619828] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3510.634691] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3510.637049] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input20
[ 3510.637688] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3510.638167] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3510.639098] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3510.639100] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3510.639101] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3510.639103] i915: Performing live selftests with st_random_seed=0x6ffe7656 st_timeout=500
[ 3510.639105] i915: Running gt_timelines
[ 3510.639116] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3512.664284] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3519.947507] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3526.857934] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3526.863848] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3527.365996] rcs0: simulated 99 wraps
[ 3527.868256] bcs0: simulated 103 wraps
[ 3528.374034] vcs0: simulated 103 wraps
[ 3528.878703] vecs0: simulated 102 wraps
[ 3528.907727] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3528.921237] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3529.035024] i915: probe of 0000:00:02.0 failed with error -25
[ 3529.165497] [IGT] i915_selftest: exiting, ret=0
[ 3529.299933] [IGT] i915_selftest: executing
[ 3529.346697] [IGT] i915_selftest: starting subtest live
[ 3529.347189] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3529.416541] Setting dangerous option force_probe - tainting kernel
[ 3529.416549] Setting dangerous option enable_guc - tainting kernel
[ 3529.416552] Setting dangerous option live_selftests - tainting kernel
[ 3529.456891] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3529.456901] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3529.469749] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3529.473125] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3530.968876] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3531.092326] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3531.092330] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3531.092331] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3531.093765] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3531.101868] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3531.114951] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3531.117256] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input21
[ 3531.117902] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3531.118470] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3531.120465] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3531.120468] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3531.120469] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3531.120471] i915: Performing live selftests with st_random_seed=0x2d0a6993 st_timeout=500
[ 3531.120473] i915: Running gt_timelines
[ 3531.120484] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3533.143617] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3540.457647] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3547.448594] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3547.454668] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3547.959427] rcs0: simulated 96 wraps
[ 3548.466449] bcs0: simulated 106 wraps
[ 3548.971104] vcs0: simulated 101 wraps
[ 3549.473302] vecs0: simulated 102 wraps
[ 3549.495174] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3549.506007] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3549.663392] i915: probe of 0000:00:02.0 failed with error -25
[ 3549.794810] [IGT] i915_selftest: exiting, ret=0
[ 3549.927370] [IGT] i915_selftest: executing
[ 3549.940832] [IGT] i915_selftest: starting subtest live
[ 3549.941033] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3550.004796] Setting dangerous option force_probe - tainting kernel
[ 3550.004804] Setting dangerous option enable_guc - tainting kernel
[ 3550.004808] Setting dangerous option live_selftests - tainting kernel
[ 3550.045345] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3550.045355] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3550.058163] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3550.061747] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3551.576421] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3551.698769] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3551.698773] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3551.698774] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3551.700152] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3551.709855] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3551.724496] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3551.726995] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input22
[ 3551.727625] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3551.728226] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3551.729224] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3551.729228] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3551.729230] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3551.729237] i915: Performing live selftests with st_random_seed=0x31456536 st_timeout=500
[ 3551.729239] i915: Running gt_timelines
[ 3551.729256] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3553.752086] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3560.429018] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3560.429027] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3560.429028] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3560.429030] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3560.902164] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3567.948617] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3567.954822] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3568.459596] rcs0: simulated 95 wraps
[ 3568.960570] bcs0: simulated 103 wraps
[ 3569.462801] vcs0: simulated 100 wraps
[ 3569.968623] vecs0: simulated 102 wraps
[ 3569.990608] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3570.002517] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3570.136907] i915: probe of 0000:00:02.0 failed with error -25
[ 3570.270285] [IGT] i915_selftest: exiting, ret=0
[ 3570.399781] [IGT] i915_selftest: executing
[ 3570.448800] [IGT] i915_selftest: starting subtest live
[ 3570.449289] [IGT] i915_selftest: starting dynamic subtest gt_timelines
[ 3570.520794] Setting dangerous option force_probe - tainting kernel
[ 3570.520802] Setting dangerous option enable_guc - tainting kernel
[ 3570.520805] Setting dangerous option live_selftests - tainting kernel
[ 3570.561148] i915 0000:00:02.0: [drm] VT-d active for gfx access
[ 3570.561157] i915 0000:00:02.0: vgaarb: deactivate vga console
[ 3570.576225] mei_hdcp 0000:00:16.0-b638ab7e-94e2-4ea2-a552-d1c54b627f04: bound 0000:00:02.0 (ops i915_hdcp_component_ops [i915])
[ 3570.577627] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/rkl_dmc_ver2_03.bin (v2.3)
[ 3572.119689] i915 0000:00:02.0: [drm] failed to retrieve link info, disabling eDP
[ 3572.242155] i915 0000:00:02.0: [drm] GuC firmware i915/tgl_guc_62.0.0.bin version 62.0 submission:enabled
[ 3572.242158] i915 0000:00:02.0: [drm] GuC SLPC: enabled
[ 3572.242159] i915 0000:00:02.0: [drm] HuC firmware i915/tgl_huc_7.9.3.bin version 7.9 authenticated:yes
[ 3572.243636] i915 0000:00:02.0: [drm] GuC RC: enabled
[ 3572.252024] [drm] Initialized i915 1.6.0 20201103 for 0000:00:02.0 on minor 0
[ 3572.266796] ACPI: video: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[ 3572.269147] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input23
[ 3572.269938] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3572.270542] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes
[ 3572.271360] i915 0000:00:02.0: [drm] DRM_I915_DEBUG enabled
[ 3572.271363] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_GEM enabled
[ 3572.271364] i915 0000:00:02.0: [drm] DRM_I915_DEBUG_RUNTIME_PM enabled
[ 3572.271366] i915: Performing live selftests with st_random_seed=0xc163c1cc st_timeout=500
[ 3572.271368] i915: Running gt_timelines
[ 3572.271380] i915: Running intel_timeline_live_selftests/live_hwsp_recycle
[ 3574.298551] i915: Running intel_timeline_live_selftests/live_hwsp_engine
[ 3580.908375] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3580.908384] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3580.908385] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3580.908387] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3581.452759] i915: Running intel_timeline_live_selftests/live_hwsp_alternate
[ 3588.457014] i915: Running intel_timeline_live_selftests/live_hwsp_wrap
[ 3588.463029] i915: Running intel_timeline_live_selftests/live_hwsp_read
[ 3588.965316] rcs0: simulated 95 wraps
[ 3589.468691] bcs0: simulated 102 wraps
[ 3589.974547] vcs0: simulated 102 wraps
[ 3590.478018] vecs0: simulated 102 wraps
[ 3590.500129] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_kernel
[ 3590.512158] i915: Running intel_timeline_live_selftests/live_hwsp_rollover_user
[ 3590.650283] i915: probe of 0000:00:02.0 failed with error -25
[ 3590.785966] [IGT] i915_selftest: exiting, ret=0
[ 3591.120847] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3591.120867] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3591.120873] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3591.120879] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3635.179907] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3635.180076] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3635.180082] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3635.180088] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3720.167975] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3720.167995] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3720.168001] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3720.168008] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3738.308637] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3738.308657] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3738.308664] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3738.308670] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3761.128147] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3761.128385] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3761.128394] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3761.128404] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3812.327366] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3812.327386] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3812.327392] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3812.327398] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3848.305346] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3848.305367] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3848.305373] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3848.305379] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3848.305729] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3848.305740] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3848.305745] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3848.305750] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3864.039654] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3864.039674] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3864.039680] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3864.039686] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3930.085339] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3930.085359] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3930.085366] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3930.085372] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3951.073740] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3951.073760] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3951.073766] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3951.073772] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 3961.313387] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 3961.313407] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 3961.313413] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 3961.313419] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4024.801289] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4024.801309] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4024.801315] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4024.801322] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4055.519892] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4055.519914] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4055.519920] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4055.519926] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4070.878616] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4070.878636] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4070.878643] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4070.878649] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4091.871807] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4091.871974] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4091.871979] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4091.871986] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4096.991698] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4096.991865] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4096.991871] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4096.991877] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4102.081362] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4102.081382] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4102.081388] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4102.081394] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4117.469043] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4117.469210] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4117.469216] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4117.469222] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4137.951271] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4137.951436] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4137.951442] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4137.951449] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4143.069321] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4143.069342] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4143.069348] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4143.069354] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4153.284821] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4153.284990] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4153.284996] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4153.285003] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4173.791252] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4173.791506] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4173.791513] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4173.791520] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4245.957950] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4245.957969] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4245.957975] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4245.957981] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4313.541696] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4313.541864] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4313.541870] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4313.541876] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4354.526429] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4354.526450] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4354.526456] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4354.526462] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4359.646268] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4359.646434] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4359.646440] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4359.646447] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4375.005348] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4375.005369] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4375.005375] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4375.005381] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4386.757131] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4386.757151] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4386.757158] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4386.757164] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4407.774873] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4407.774893] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4407.774899] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4407.774905] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4443.107501] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4443.107521] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4443.107527] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4443.107533] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4497.349566] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4497.349734] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4497.349740] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4497.349747] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4502.494711] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4502.494879] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4502.494885] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4502.494891] nvme 0000:01:00.0:    [ 0] RxErr                 
[ 4552.159987] pcieport 0000:00:06.0: AER: Corrected error received: 0000:01:00.0
[ 4552.160234] nvme 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, (Receiver ID)
[ 4552.160241] nvme 0000:01:00.0:   device [15b7:5006] error status/mask=00000001/0000e000
[ 4552.160247] nvme 0000:01:00.0:    [ 0] RxErr