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From: Vincenzo Frascino <vincenzo.frascino@arm.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com
Cc: vincenzo.frascino@arm.com,
	Andrew Morton <akpm@linux-foundation.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>,
	Andrey Ryabinin <aryabinin@virtuozzo.com>,
	Alexander Potapenko <glider@google.com>,
	Marco Elver <elver@google.com>,
	Evgenii Stepanov <eugenis@google.com>,
	Branislav Rankov <Branislav.Rankov@arm.com>,
	Andrey Konovalov <andreyknvl@gmail.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: [PATCH 2/5] arm64: mte: Bitfield definitions for Asymm MTE
Date: Mon, 13 Sep 2021 09:14:21 +0100	[thread overview]
Message-ID: <20210913081424.48613-3-vincenzo.frascino@arm.com> (raw)
In-Reply-To: <20210913081424.48613-1-vincenzo.frascino@arm.com>

Add Asymmetric Memory Tagging Extension bitfield definitions.

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b268082d67ed..f51d5912b41c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -621,6 +621,7 @@
 #define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_ASYMM	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
 
 #define SCTLR_ELx_ENIA_SHIFT	31
@@ -666,6 +667,7 @@
 #define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_ASYMM	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
 
 #define SCTLR_EL1_BT1		(BIT(36))
@@ -807,6 +809,7 @@
 #define ID_AA64PFR1_MTE_NI		0x0
 #define ID_AA64PFR1_MTE_EL0		0x1
 #define ID_AA64PFR1_MTE			0x2
+#define ID_AA64PFR1_MTE_ASYMM		0x3
 
 /* id_aa64zfr0 */
 #define ID_AA64ZFR0_F64MM_SHIFT		56
-- 
2.33.0


WARNING: multiple messages have this Message-ID (diff)
From: Vincenzo Frascino <vincenzo.frascino@arm.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com
Cc: vincenzo.frascino@arm.com,
	Andrew Morton <akpm@linux-foundation.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>,
	Andrey Ryabinin <aryabinin@virtuozzo.com>,
	Alexander Potapenko <glider@google.com>,
	Marco Elver <elver@google.com>,
	Evgenii Stepanov <eugenis@google.com>,
	Branislav Rankov <Branislav.Rankov@arm.com>,
	Andrey Konovalov <andreyknvl@gmail.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: [PATCH 2/5] arm64: mte: Bitfield definitions for Asymm MTE
Date: Mon, 13 Sep 2021 09:14:21 +0100	[thread overview]
Message-ID: <20210913081424.48613-3-vincenzo.frascino@arm.com> (raw)
In-Reply-To: <20210913081424.48613-1-vincenzo.frascino@arm.com>

Add Asymmetric Memory Tagging Extension bitfield definitions.

Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b268082d67ed..f51d5912b41c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -621,6 +621,7 @@
 #define SCTLR_ELx_TCF_NONE	(UL(0x0) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_SYNC	(UL(0x1) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_ASYNC	(UL(0x2) << SCTLR_ELx_TCF_SHIFT)
+#define SCTLR_ELx_TCF_ASYMM	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
 #define SCTLR_ELx_TCF_MASK	(UL(0x3) << SCTLR_ELx_TCF_SHIFT)
 
 #define SCTLR_ELx_ENIA_SHIFT	31
@@ -666,6 +667,7 @@
 #define SCTLR_EL1_TCF0_NONE	(UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_SYNC	(UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_ASYNC	(UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
+#define SCTLR_EL1_TCF0_ASYMM	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
 #define SCTLR_EL1_TCF0_MASK	(UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
 
 #define SCTLR_EL1_BT1		(BIT(36))
@@ -807,6 +809,7 @@
 #define ID_AA64PFR1_MTE_NI		0x0
 #define ID_AA64PFR1_MTE_EL0		0x1
 #define ID_AA64PFR1_MTE			0x2
+#define ID_AA64PFR1_MTE_ASYMM		0x3
 
 /* id_aa64zfr0 */
 #define ID_AA64ZFR0_F64MM_SHIFT		56
-- 
2.33.0


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  parent reply	other threads:[~2021-09-13  8:14 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13  8:14 [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Vincenzo Frascino
2021-09-13  8:14 ` Vincenzo Frascino
2021-09-13  8:14 ` [PATCH 1/5] kasan: Remove duplicate of kasan_flag_async Vincenzo Frascino
2021-09-13  8:14   ` Vincenzo Frascino
2021-09-20 15:31   ` Catalin Marinas
2021-09-20 15:31     ` Catalin Marinas
2021-10-03 17:12   ` Andrey Konovalov
2021-10-03 17:12     ` Andrey Konovalov
2021-09-13  8:14 ` Vincenzo Frascino [this message]
2021-09-13  8:14   ` [PATCH 2/5] arm64: mte: Bitfield definitions for Asymm MTE Vincenzo Frascino
2021-09-20 15:31   ` Catalin Marinas
2021-09-20 15:31     ` Catalin Marinas
2021-09-13  8:14 ` [PATCH 3/5] arm64: mte: CPU feature detection " Vincenzo Frascino
2021-09-13  8:14   ` Vincenzo Frascino
2021-09-20 15:31   ` Catalin Marinas
2021-09-20 15:31     ` Catalin Marinas
2021-09-20 15:41   ` Suzuki K Poulose
2021-09-20 15:41     ` Suzuki K Poulose
2021-09-13  8:14 ` [PATCH 4/5] arm64: mte: Add asymmetric mode support Vincenzo Frascino
2021-09-13  8:14   ` Vincenzo Frascino
2021-09-20 15:31   ` Catalin Marinas
2021-09-20 15:31     ` Catalin Marinas
2021-10-03 17:15   ` Andrey Konovalov
2021-10-03 17:15     ` Andrey Konovalov
2021-10-04 15:39     ` Vincenzo Frascino
2021-10-04 15:39       ` Vincenzo Frascino
2021-09-13  8:14 ` [PATCH 5/5] kasan: Extend KASAN mode kernel parameter Vincenzo Frascino
2021-09-13  8:14   ` Vincenzo Frascino
2021-09-16 10:43   ` Marco Elver
2021-09-16 10:43     ` Marco Elver
2021-09-20  7:46     ` Vincenzo Frascino
2021-09-20  7:46       ` Vincenzo Frascino
2021-10-03 17:16       ` Andrey Konovalov
2021-10-03 17:16         ` Andrey Konovalov
2021-10-04 15:45         ` Vincenzo Frascino
2021-10-04 15:45           ` Vincenzo Frascino
2021-09-20 15:32   ` Catalin Marinas
2021-09-20 15:32     ` Catalin Marinas
2021-09-20 21:29 ` [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Peter Collingbourne
2021-09-20 21:29   ` Peter Collingbourne
2021-09-21  7:03   ` Vincenzo Frascino
2021-09-21  7:03     ` Vincenzo Frascino
2021-09-29 15:49 ` Will Deacon
2021-09-29 15:49   ` Will Deacon
2021-10-04 15:16   ` Vincenzo Frascino
2021-10-04 15:16     ` Vincenzo Frascino

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