From: Vincenzo Frascino <vincenzo.frascino@arm.com>
To: Andrey Konovalov <andreyknvl@gmail.com>
Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
kasan-dev <kasan-dev@googlegroups.com>,
Andrew Morton <akpm@linux-foundation.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>,
Andrey Ryabinin <aryabinin@virtuozzo.com>,
Alexander Potapenko <glider@google.com>,
Marco Elver <elver@google.com>,
Evgenii Stepanov <eugenis@google.com>,
Branislav Rankov <Branislav.Rankov@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: Re: [PATCH 4/5] arm64: mte: Add asymmetric mode support
Date: Mon, 4 Oct 2021 17:39:16 +0200 [thread overview]
Message-ID: <cd011cc0-5d3d-b642-55c3-fa2107f7f826@arm.com> (raw)
In-Reply-To: <CA+fCnZeW35+ZmvM6SxZSb_NAMqsK42Ds_ADVKeVkfs9MT=Aovg@mail.gmail.com>
Hi Andrey,
On 10/3/21 7:15 PM, Andrey Konovalov wrote:
> This part is confusing: mte_async_mode gets enabled for the asymm
> mode, which contradicts the comment next to the mte_async_mode
> definition.
Good point I will fix the comment near by the mte_async_mode definition.
Thanks!
--
Regards,
Vincenzo
WARNING: multiple messages have this Message-ID (diff)
From: Vincenzo Frascino <vincenzo.frascino@arm.com>
To: Andrey Konovalov <andreyknvl@gmail.com>
Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
kasan-dev <kasan-dev@googlegroups.com>,
Andrew Morton <akpm@linux-foundation.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>,
Andrey Ryabinin <aryabinin@virtuozzo.com>,
Alexander Potapenko <glider@google.com>,
Marco Elver <elver@google.com>,
Evgenii Stepanov <eugenis@google.com>,
Branislav Rankov <Branislav.Rankov@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: Re: [PATCH 4/5] arm64: mte: Add asymmetric mode support
Date: Mon, 4 Oct 2021 17:39:16 +0200 [thread overview]
Message-ID: <cd011cc0-5d3d-b642-55c3-fa2107f7f826@arm.com> (raw)
In-Reply-To: <CA+fCnZeW35+ZmvM6SxZSb_NAMqsK42Ds_ADVKeVkfs9MT=Aovg@mail.gmail.com>
Hi Andrey,
On 10/3/21 7:15 PM, Andrey Konovalov wrote:
> This part is confusing: mte_async_mode gets enabled for the asymm
> mode, which contradicts the comment next to the mte_async_mode
> definition.
Good point I will fix the comment near by the mte_async_mode definition.
Thanks!
--
Regards,
Vincenzo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-04 15:39 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 8:14 [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Vincenzo Frascino
2021-09-13 8:14 ` Vincenzo Frascino
2021-09-13 8:14 ` [PATCH 1/5] kasan: Remove duplicate of kasan_flag_async Vincenzo Frascino
2021-09-13 8:14 ` Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-09-20 15:31 ` Catalin Marinas
2021-10-03 17:12 ` Andrey Konovalov
2021-10-03 17:12 ` Andrey Konovalov
2021-09-13 8:14 ` [PATCH 2/5] arm64: mte: Bitfield definitions for Asymm MTE Vincenzo Frascino
2021-09-13 8:14 ` Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-09-20 15:31 ` Catalin Marinas
2021-09-13 8:14 ` [PATCH 3/5] arm64: mte: CPU feature detection " Vincenzo Frascino
2021-09-13 8:14 ` Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-09-20 15:31 ` Catalin Marinas
2021-09-20 15:41 ` Suzuki K Poulose
2021-09-20 15:41 ` Suzuki K Poulose
2021-09-13 8:14 ` [PATCH 4/5] arm64: mte: Add asymmetric mode support Vincenzo Frascino
2021-09-13 8:14 ` Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-09-20 15:31 ` Catalin Marinas
2021-10-03 17:15 ` Andrey Konovalov
2021-10-03 17:15 ` Andrey Konovalov
2021-10-04 15:39 ` Vincenzo Frascino [this message]
2021-10-04 15:39 ` Vincenzo Frascino
2021-09-13 8:14 ` [PATCH 5/5] kasan: Extend KASAN mode kernel parameter Vincenzo Frascino
2021-09-13 8:14 ` Vincenzo Frascino
2021-09-16 10:43 ` Marco Elver
2021-09-16 10:43 ` Marco Elver
2021-09-20 7:46 ` Vincenzo Frascino
2021-09-20 7:46 ` Vincenzo Frascino
2021-10-03 17:16 ` Andrey Konovalov
2021-10-03 17:16 ` Andrey Konovalov
2021-10-04 15:45 ` Vincenzo Frascino
2021-10-04 15:45 ` Vincenzo Frascino
2021-09-20 15:32 ` Catalin Marinas
2021-09-20 15:32 ` Catalin Marinas
2021-09-20 21:29 ` [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Peter Collingbourne
2021-09-20 21:29 ` Peter Collingbourne
2021-09-21 7:03 ` Vincenzo Frascino
2021-09-21 7:03 ` Vincenzo Frascino
2021-09-29 15:49 ` Will Deacon
2021-09-29 15:49 ` Will Deacon
2021-10-04 15:16 ` Vincenzo Frascino
2021-10-04 15:16 ` Vincenzo Frascino
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cd011cc0-5d3d-b642-55c3-fa2107f7f826@arm.com \
--to=vincenzo.frascino@arm.com \
--cc=Branislav.Rankov@arm.com \
--cc=akpm@linux-foundation.org \
--cc=andreyknvl@gmail.com \
--cc=aryabinin@virtuozzo.com \
--cc=catalin.marinas@arm.com \
--cc=dvyukov@google.com \
--cc=elver@google.com \
--cc=eugenis@google.com \
--cc=glider@google.com \
--cc=kasan-dev@googlegroups.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.