From: Chen Huang <chenhuang5@huawei.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Chen Huang <chenhuang5@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 0/2] riscv: improve unaligned memory accesses
Date: Mon, 13 Sep 2021 12:19:54 +0000 [thread overview]
Message-ID: <20210913121956.1776656-1-chenhuang5@huawei.com> (raw)
The RISCV ISA can support unaligned memory accesses, so the patchset
selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
to improve the efficiency of unaligned memory accesses.
Chen Huang (2):
riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
riscv: Support DCACHE_WORD_ACCESS
arch/riscv/Kconfig | 2 ++
arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
--
2.18.0.huawei.25
WARNING: multiple messages have this Message-ID (diff)
From: Chen Huang <chenhuang5@huawei.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Chen Huang <chenhuang5@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 0/2] riscv: improve unaligned memory accesses
Date: Mon, 13 Sep 2021 12:19:54 +0000 [thread overview]
Message-ID: <20210913121956.1776656-1-chenhuang5@huawei.com> (raw)
The RISCV ISA can support unaligned memory accesses, so the patchset
selects HAVE_EFFICIENT_UNALIGNED_ACCESS and supports DCACHE_WORD_ACCESS
to improve the efficiency of unaligned memory accesses.
Chen Huang (2):
riscv: Kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS
riscv: Support DCACHE_WORD_ACCESS
arch/riscv/Kconfig | 2 ++
arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
--
2.18.0.huawei.25
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next reply other threads:[~2021-09-13 12:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 12:19 Chen Huang [this message]
2021-09-13 12:19 ` [PATCH 0/2] riscv: improve unaligned memory accesses Chen Huang
2021-09-13 12:19 ` [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS Chen Huang
2021-09-13 12:19 ` Chen Huang
2021-09-14 17:08 ` Darius Rad
2021-09-14 17:08 ` Darius Rad
2021-09-13 12:19 ` [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS Chen Huang
2021-09-13 12:19 ` Chen Huang
2021-09-15 14:13 ` [SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses Jisheng Zhang
2021-09-16 2:54 ` Chen Huang
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