From: Chen Huang <chenhuang5@huawei.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Chen Huang <chenhuang5@huawei.com>, Kefeng Wang <wangkefeng.wang@huawei.com>, <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS Date: Mon, 13 Sep 2021 12:19:56 +0000 [thread overview] Message-ID: <20210913121956.1776656-3-chenhuang5@huawei.com> (raw) In-Reply-To: <20210913121956.1776656-1-chenhuang5@huawei.com> This patch selects DCACHE_WORD_ACCESS on riscv and implements support for load_unaligned_zeropad. DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string comparisons in the vfs layer. Signed-off-by: Chen Huang <chenhuang5@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6e70bf50b02a..f6f0da0f436b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK + select DCACHE_WORD_ACCESS select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h index 7c086ac6ecd4..0b77ce654f56 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -11,6 +11,8 @@ #include <linux/kernel.h> +#include <asm/asm.h> + struct word_at_a_time { const unsigned long one_bits, high_bits; }; @@ -45,4 +47,38 @@ static inline unsigned long find_zero(unsigned long mask) /* The mask we created is directly usable as a bytemask */ #define zero_bytemask(mask) (mask) +/* + * Load an unaligned word from kernel space. + * + * In the (very unlikely) case of the word being a page-crosser + * and the next page not being mapped, take the exception and + * return zeroes in the non-existing part. + */ +static inline unsigned long load_unaligned_zeropad(const void *addr) +{ + unsigned long ret, tmp; + + /* Load word from unaligned pointer addr */ + asm( + "1: " REG_L " %0, %3\n" + "2:\n" + " .section .fixup,\"ax\"\n" + " .balign 2\n" + "3: andi %1, %2, ~0x7\n" + " " REG_L " %0, (%1)\n" + " andi %1, %2, 0x7\n" + " slli %1, %1, 0x3\n" + " srl %0, %0, %1\n" + " jump 2b, %1\n" + " .previous\n" + " .section __ex_table,\"a\"\n" + " .balign " RISCV_SZPTR "\n" + " " RISCV_PTR " 1b, 3b\n" + " .previous" + : "=&r" (ret), "=&r" (tmp) + : "r" (addr), "m" (*(unsigned long *)addr)); + + return ret; +} + #endif /* _ASM_RISCV_WORD_AT_A_TIME_H */ -- 2.18.0.huawei.25
WARNING: multiple messages have this Message-ID (diff)
From: Chen Huang <chenhuang5@huawei.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Chen Huang <chenhuang5@huawei.com>, Kefeng Wang <wangkefeng.wang@huawei.com>, <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS Date: Mon, 13 Sep 2021 12:19:56 +0000 [thread overview] Message-ID: <20210913121956.1776656-3-chenhuang5@huawei.com> (raw) In-Reply-To: <20210913121956.1776656-1-chenhuang5@huawei.com> This patch selects DCACHE_WORD_ACCESS on riscv and implements support for load_unaligned_zeropad. DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string comparisons in the vfs layer. Signed-off-by: Chen Huang <chenhuang5@huawei.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/word-at-a-time.h | 36 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6e70bf50b02a..f6f0da0f436b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,7 @@ config RISCV select CLONE_BACKWARDS select CLINT_TIMER if !MMU select COMMON_CLK + select DCACHE_WORD_ACCESS select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h index 7c086ac6ecd4..0b77ce654f56 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -11,6 +11,8 @@ #include <linux/kernel.h> +#include <asm/asm.h> + struct word_at_a_time { const unsigned long one_bits, high_bits; }; @@ -45,4 +47,38 @@ static inline unsigned long find_zero(unsigned long mask) /* The mask we created is directly usable as a bytemask */ #define zero_bytemask(mask) (mask) +/* + * Load an unaligned word from kernel space. + * + * In the (very unlikely) case of the word being a page-crosser + * and the next page not being mapped, take the exception and + * return zeroes in the non-existing part. + */ +static inline unsigned long load_unaligned_zeropad(const void *addr) +{ + unsigned long ret, tmp; + + /* Load word from unaligned pointer addr */ + asm( + "1: " REG_L " %0, %3\n" + "2:\n" + " .section .fixup,\"ax\"\n" + " .balign 2\n" + "3: andi %1, %2, ~0x7\n" + " " REG_L " %0, (%1)\n" + " andi %1, %2, 0x7\n" + " slli %1, %1, 0x3\n" + " srl %0, %0, %1\n" + " jump 2b, %1\n" + " .previous\n" + " .section __ex_table,\"a\"\n" + " .balign " RISCV_SZPTR "\n" + " " RISCV_PTR " 1b, 3b\n" + " .previous" + : "=&r" (ret), "=&r" (tmp) + : "r" (addr), "m" (*(unsigned long *)addr)); + + return ret; +} + #endif /* _ASM_RISCV_WORD_AT_A_TIME_H */ -- 2.18.0.huawei.25 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-09-13 12:11 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-13 12:19 [PATCH 0/2] riscv: improve unaligned memory accesses Chen Huang 2021-09-13 12:19 ` Chen Huang 2021-09-13 12:19 ` [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS Chen Huang 2021-09-13 12:19 ` Chen Huang 2021-09-14 17:08 ` Darius Rad 2021-09-14 17:08 ` Darius Rad 2021-09-13 12:19 ` Chen Huang [this message] 2021-09-13 12:19 ` [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS Chen Huang 2021-09-15 14:13 ` [SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses Jisheng Zhang 2021-09-16 2:54 ` Chen Huang
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