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From: Chen Huang <chenhuang5@huawei.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Chen Huang <chenhuang5@huawei.com>,
	Kefeng Wang <wangkefeng.wang@huawei.com>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Mon, 13 Sep 2021 12:19:55 +0000	[thread overview]
Message-ID: <20210913121956.1776656-2-chenhuang5@huawei.com> (raw)
In-Reply-To: <20210913121956.1776656-1-chenhuang5@huawei.com>

The RISCV ISA can perform efficient unaligned memory accesses
in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
for that.

Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..6e70bf50b02a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_EBPF_JIT if MMU
+	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 	select HAVE_FUNCTION_ERROR_INJECTION
 	select HAVE_FUTEX_CMPXCHG if FUTEX
 	select HAVE_GCC_PLUGINS
-- 
2.18.0.huawei.25


WARNING: multiple messages have this Message-ID (diff)
From: Chen Huang <chenhuang5@huawei.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: Chen Huang <chenhuang5@huawei.com>,
	Kefeng Wang <wangkefeng.wang@huawei.com>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Mon, 13 Sep 2021 12:19:55 +0000	[thread overview]
Message-ID: <20210913121956.1776656-2-chenhuang5@huawei.com> (raw)
In-Reply-To: <20210913121956.1776656-1-chenhuang5@huawei.com>

The RISCV ISA can perform efficient unaligned memory accesses
in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
for that.

Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..6e70bf50b02a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_EBPF_JIT if MMU
+	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 	select HAVE_FUNCTION_ERROR_INJECTION
 	select HAVE_FUTEX_CMPXCHG if FUTEX
 	select HAVE_GCC_PLUGINS
-- 
2.18.0.huawei.25


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  reply	other threads:[~2021-09-13 12:11 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13 12:19 [PATCH 0/2] riscv: improve unaligned memory accesses Chen Huang
2021-09-13 12:19 ` Chen Huang
2021-09-13 12:19 ` Chen Huang [this message]
2021-09-13 12:19   ` [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS Chen Huang
2021-09-14 17:08   ` Darius Rad
2021-09-14 17:08     ` Darius Rad
2021-09-13 12:19 ` [PATCH 2/2] riscv: Support DCACHE_WORD_ACCESS Chen Huang
2021-09-13 12:19   ` Chen Huang
2021-09-15 14:13 ` [SPAM] [PATCH 0/2] riscv: improve unaligned memory accesses Jisheng Zhang
2021-09-16  2:54   ` Chen Huang

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