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* [PATCH] drm/v3d: fix wait for TMU write combiner flush
@ 2021-09-14  5:55 Iago Toral Quiroga
  2021-09-15  8:57 ` Melissa Wen
  0 siblings, 1 reply; 5+ messages in thread
From: Iago Toral Quiroga @ 2021-09-14  5:55 UTC (permalink / raw)
  To: dri-devel; +Cc: mwen

The hardware sets the TMUWCF bit back to 0 when the TMU write
combiner flush completes so we should be checking for that instead
of the L2TFLS bit.

Fixes spurious Vulkan CTS failures in:
dEQP-VK.binding_model.descriptorset_random.*
---
 drivers/gpu/drm/v3d/v3d_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index a3529809d547..5159f544bc16 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -197,7 +197,7 @@ v3d_clean_caches(struct v3d_dev *v3d)
 
 	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
 	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
-		       V3D_L2TCACTL_L2TFLS), 100)) {
+		       V3D_L2TCACTL_TMUWCF), 100)) {
 		DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
 	}
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/v3d: fix wait for TMU write combiner flush
  2021-09-14  5:55 [PATCH] drm/v3d: fix wait for TMU write combiner flush Iago Toral Quiroga
@ 2021-09-15  8:57 ` Melissa Wen
  2021-09-15  9:54   ` Iago Toral
  2021-09-15 10:05   ` [PATCH v2] " Iago Toral Quiroga
  0 siblings, 2 replies; 5+ messages in thread
From: Melissa Wen @ 2021-09-15  8:57 UTC (permalink / raw)
  To: Iago Toral Quiroga; +Cc: dri-devel

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On 09/14, Iago Toral Quiroga wrote:
> The hardware sets the TMUWCF bit back to 0 when the TMU write
> combiner flush completes so we should be checking for that instead
> of the L2TFLS bit.
> 
> Fixes spurious Vulkan CTS failures in:
> dEQP-VK.binding_model.descriptorset_random.*
Hi Iago,

makes sense to me.

can you add the fix tag?
Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch") 

also, you forgot to add your Signed-off-by tag.
> ---
>  drivers/gpu/drm/v3d/v3d_gem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
> index a3529809d547..5159f544bc16 100644
> --- a/drivers/gpu/drm/v3d/v3d_gem.c
> +++ b/drivers/gpu/drm/v3d/v3d_gem.c
> @@ -197,7 +197,7 @@ v3d_clean_caches(struct v3d_dev *v3d)
>  
>  	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
>  	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
> -		       V3D_L2TCACTL_L2TFLS), 100)) {
> +		       V3D_L2TCACTL_TMUWCF), 100)) {
>  		DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
hm.. would it be clearer to say "TMU write combiner" here?

in the next version, you can already include:
Reviewed-by: Melissa Wen <mwen@igalia.com>

Thanks,

Melissa
>  	}
>  
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/v3d: fix wait for TMU write combiner flush
  2021-09-15  8:57 ` Melissa Wen
@ 2021-09-15  9:54   ` Iago Toral
  2021-09-15 10:05   ` [PATCH v2] " Iago Toral Quiroga
  1 sibling, 0 replies; 5+ messages in thread
From: Iago Toral @ 2021-09-15  9:54 UTC (permalink / raw)
  To: Melissa Wen; +Cc: dri-devel

On Wed, 2021-09-15 at 09:57 +0100, Melissa Wen wrote:
> On 09/14, Iago Toral Quiroga wrote:
> > The hardware sets the TMUWCF bit back to 0 when the TMU write
> > combiner flush completes so we should be checking for that instead
> > of the L2TFLS bit.
> > 
> > Fixes spurious Vulkan CTS failures in:
> > dEQP-VK.binding_model.descriptorset_random.*
> Hi Iago,
> 
> makes sense to me.
> 
> can you add the fix tag?
> Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader
> dispatch") 
> 
> also, you forgot to add your Signed-off-by tag.

Will include both, thanks.

> > ---
> >  drivers/gpu/drm/v3d/v3d_gem.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/v3d/v3d_gem.c
> > b/drivers/gpu/drm/v3d/v3d_gem.c
> > index a3529809d547..5159f544bc16 100644
> > --- a/drivers/gpu/drm/v3d/v3d_gem.c
> > +++ b/drivers/gpu/drm/v3d/v3d_gem.c
> > @@ -197,7 +197,7 @@ v3d_clean_caches(struct v3d_dev *v3d)
> >  
> >  	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
> >  	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
> > -		       V3D_L2TCACTL_L2TFLS), 100)) {
> > +		       V3D_L2TCACTL_TMUWCF), 100)) {
> >  		DRM_ERROR("Timeout waiting for L1T write combiner
> > flush\n");
> hm.. would it be clearer to say "TMU write combiner" here?

Yes, I guess it does. I'll add this too.

> 
> in the next version, you can already include:
> Reviewed-by: Melissa Wen <mwen@igalia.com>
> 
Thanks!

Iago

> Thanks,
> 
> Melissa
> >  	}
> >  
> > -- 
> > 2.25.1
> > 


^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2] drm/v3d: fix wait for TMU write combiner flush
  2021-09-15  8:57 ` Melissa Wen
  2021-09-15  9:54   ` Iago Toral
@ 2021-09-15 10:05   ` Iago Toral Quiroga
  2021-09-15 17:54     ` Melissa Wen
  1 sibling, 1 reply; 5+ messages in thread
From: Iago Toral Quiroga @ 2021-09-15 10:05 UTC (permalink / raw)
  To: dri-devel; +Cc: mwen

The hardware sets the TMUWCF bit back to 0 when the TMU write
combiner flush completes so we should be checking for that instead
of the L2TFLS bit.

v2 (Melissa Wen):
  - Add Signed-off-by and Fixes tags.
  - Change the error message for the timeout to be more clear.

Fixes spurious Vulkan CTS failures in:
dEQP-VK.binding_model.descriptorset_random.*

Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch")
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/v3d/v3d_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index a3529809d547..1953706bdaeb 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -197,8 +197,8 @@ v3d_clean_caches(struct v3d_dev *v3d)
 
 	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
 	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
-		       V3D_L2TCACTL_L2TFLS), 100)) {
-		DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
+		       V3D_L2TCACTL_TMUWCF), 100)) {
+		DRM_ERROR("Timeout waiting for TMU write combiner flush\n");
 	}
 
 	mutex_lock(&v3d->cache_clean_lock);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/v3d: fix wait for TMU write combiner flush
  2021-09-15 10:05   ` [PATCH v2] " Iago Toral Quiroga
@ 2021-09-15 17:54     ` Melissa Wen
  0 siblings, 0 replies; 5+ messages in thread
From: Melissa Wen @ 2021-09-15 17:54 UTC (permalink / raw)
  To: Iago Toral Quiroga; +Cc: dri-devel, mwen

On 09/15, Iago Toral Quiroga wrote:
> The hardware sets the TMUWCF bit back to 0 when the TMU write
> combiner flush completes so we should be checking for that instead
> of the L2TFLS bit.
> 
> v2 (Melissa Wen):
>   - Add Signed-off-by and Fixes tags.
>   - Change the error message for the timeout to be more clear.
> 
> Fixes spurious Vulkan CTS failures in:
> dEQP-VK.binding_model.descriptorset_random.*
> 
> Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch")
> Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
> Reviewed-by: Melissa Wen <mwen@igalia.com>

Applied to drm-misc-next.

Thanks,

Melissa

> ---
>  drivers/gpu/drm/v3d/v3d_gem.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
> index a3529809d547..1953706bdaeb 100644
> --- a/drivers/gpu/drm/v3d/v3d_gem.c
> +++ b/drivers/gpu/drm/v3d/v3d_gem.c
> @@ -197,8 +197,8 @@ v3d_clean_caches(struct v3d_dev *v3d)
>  
>  	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
>  	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
> -		       V3D_L2TCACTL_L2TFLS), 100)) {
> -		DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
> +		       V3D_L2TCACTL_TMUWCF), 100)) {
> +		DRM_ERROR("Timeout waiting for TMU write combiner flush\n");
>  	}
>  
>  	mutex_lock(&v3d->cache_clean_lock);
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-09-15 17:54 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-14  5:55 [PATCH] drm/v3d: fix wait for TMU write combiner flush Iago Toral Quiroga
2021-09-15  8:57 ` Melissa Wen
2021-09-15  9:54   ` Iago Toral
2021-09-15 10:05   ` [PATCH v2] " Iago Toral Quiroga
2021-09-15 17:54     ` Melissa Wen

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