* [PATCH 1/5] drm/amd/pm: Slight function rename (v2)
2021-10-15 0:50 [PATCH 0/5] 0 MHz is not a valid current frequency (v3) Luben Tuikov
@ 2021-10-15 0:50 ` Luben Tuikov
2021-10-15 0:50 ` [PATCH 2/5] drm/amd/pm: Rename cur_value to curr_value Luben Tuikov
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Luben Tuikov @ 2021-10-15 0:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Luben Tuikov, Alex Deucher
Rename
sienna_cichlid_is_support_fine_grained_dpm() to
sienna_cichlid_supports_fine_grained_dpm().
Rename
navi10_is_support_fine_grained_dpm() to
navi10_supports_fine_grained_dpm().
v2: Fix function name in commit message to reflect
the change being done: add a missing 's'.
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 ++++---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 7 ++++---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 71161f6b78fea9..0fe9790f67f5af 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1231,7 +1231,8 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
value);
}
-static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
+static bool navi10_supports_fine_grained_dpm(struct smu_context *smu,
+ enum smu_clk_type clk_type)
{
PPTable_t *pptable = smu->smu_table.driver_pptable;
DpmDescriptor_t *dpm_desc = NULL;
@@ -1299,7 +1300,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
if (ret)
return size;
- if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
+ if (!navi10_supports_fine_grained_dpm(smu, clk_type)) {
for (i = 0; i < count; i++) {
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
if (ret)
@@ -1465,7 +1466,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
case SMU_UCLK:
case SMU_FCLK:
/* There is only 2 levels for fine grained DPM */
- if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
+ if (navi10_supports_fine_grained_dpm(smu, clk_type)) {
soft_max_level = (soft_max_level >= 1 ? 1 : 0);
soft_min_level = (soft_min_level >= 1 ? 1 : 0);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 15e66e1912de33..3f5721baa5ff50 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1006,7 +1006,8 @@ static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
}
-static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
+static bool sienna_cichlid_supports_fine_grained_dpm(struct smu_context *smu,
+ enum smu_clk_type clk_type)
{
DpmDescriptor_t *dpm_desc = NULL;
DpmDescriptor_t *table_member;
@@ -1084,7 +1085,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
if (ret)
goto print_clk_out;
- if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
+ if (!sienna_cichlid_supports_fine_grained_dpm(smu, clk_type)) {
for (i = 0; i < count; i++) {
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
if (ret)
@@ -1235,7 +1236,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
case SMU_UCLK:
case SMU_FCLK:
/* There is only 2 levels for fine grained DPM */
- if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
+ if (sienna_cichlid_supports_fine_grained_dpm(smu, clk_type)) {
soft_max_level = (soft_max_level >= 1 ? 1 : 0);
soft_min_level = (soft_min_level >= 1 ? 1 : 0);
}
--
2.33.1.558.g2bd2f258f4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] drm/amd/pm: Rename cur_value to curr_value
2021-10-15 0:50 [PATCH 0/5] 0 MHz is not a valid current frequency (v3) Luben Tuikov
2021-10-15 0:50 ` [PATCH 1/5] drm/amd/pm: Slight function rename (v2) Luben Tuikov
@ 2021-10-15 0:50 ` Luben Tuikov
2021-10-15 0:50 ` [PATCH 3/5] drm/amd/pm: Rename freq_values --> freq_value Luben Tuikov
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Luben Tuikov @ 2021-10-15 0:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Luben Tuikov, Alex Deucher
Rename "cur_value", which stands for "cursor
value" to "curr_value", which stands for "current
value".
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 12 ++++++------
.../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 15 ++++++++-------
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 0fe9790f67f5af..f810549df493d5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1267,7 +1267,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
{
uint16_t *curve_settings;
int i, size = 0, ret = 0;
- uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t curr_value = 0, value = 0, count = 0;
uint32_t freq_values[3] = {0};
uint32_t mark_index = 0;
struct smu_table_context *table_context = &smu->smu_table;
@@ -1292,7 +1292,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
case SMU_VCLK:
case SMU_DCLK:
case SMU_DCEFCLK:
- ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
+ ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &curr_value);
if (ret)
return size;
@@ -1307,7 +1307,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
return size;
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
- cur_value == value ? "*" : "");
+ curr_value == value ? "*" : "");
}
} else {
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
@@ -1317,9 +1317,9 @@ static int navi10_print_clk_levels(struct smu_context *smu,
if (ret)
return size;
- freq_values[1] = cur_value;
- mark_index = cur_value == freq_values[0] ? 0 :
- cur_value == freq_values[2] ? 2 : 1;
+ freq_values[1] = curr_value;
+ mark_index = curr_value == freq_values[0] ? 0 :
+ curr_value == freq_values[2] ? 2 : 1;
if (mark_index != 1)
freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3f5721baa5ff50..3ebded3a99b5f2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1052,7 +1052,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
OverDriveTable_t *od_table =
(OverDriveTable_t *)table_context->overdrive_table;
int i, size = 0, ret = 0;
- uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t curr_value = 0, value = 0, count = 0;
uint32_t freq_values[3] = {0};
uint32_t mark_index = 0;
uint32_t gen_speed, lane_width;
@@ -1073,10 +1073,11 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
case SMU_DCLK:
case SMU_DCLK1:
case SMU_DCEFCLK:
- ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
+ ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &curr_value);
if (ret)
goto print_clk_out;
+
/* no need to disable gfxoff when retrieving the current gfxclk */
if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
amdgpu_gfx_off_ctrl(adev, false);
@@ -1092,7 +1093,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
goto print_clk_out;
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
- cur_value == value ? "*" : "");
+ curr_value == value ? "*" : "");
}
} else {
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
@@ -1102,9 +1103,9 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
if (ret)
goto print_clk_out;
- freq_values[1] = cur_value;
- mark_index = cur_value == freq_values[0] ? 0 :
- cur_value == freq_values[2] ? 2 : 1;
+ freq_values[1] = curr_value;
+ mark_index = curr_value == freq_values[0] ? 0 :
+ curr_value == freq_values[2] ? 2 : 1;
count = 3;
if (mark_index != 1) {
@@ -1114,7 +1115,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
for (i = 0; i < count; i++) {
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
- cur_value == freq_values[i] ? "*" : "");
+ curr_value == freq_values[i] ? "*" : "");
}
}
--
2.33.1.558.g2bd2f258f4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/5] drm/amd/pm: Rename freq_values --> freq_value
2021-10-15 0:50 [PATCH 0/5] 0 MHz is not a valid current frequency (v3) Luben Tuikov
2021-10-15 0:50 ` [PATCH 1/5] drm/amd/pm: Slight function rename (v2) Luben Tuikov
2021-10-15 0:50 ` [PATCH 2/5] drm/amd/pm: Rename cur_value to curr_value Luben Tuikov
@ 2021-10-15 0:50 ` Luben Tuikov
2021-10-15 0:50 ` [PATCH 4/5] dpm/amd/pm: Sienna: 0 MHz is not a current clock frequency (v2) Luben Tuikov
2021-10-15 0:50 ` [PATCH 5/5] dpm/amd/pm: Navi10: " Luben Tuikov
4 siblings, 0 replies; 7+ messages in thread
From: Luben Tuikov @ 2021-10-15 0:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Luben Tuikov, Alex Deucher
By usage: read freq_values[x] to freq_value[x].
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 16 ++++++++--------
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 18 +++++++++---------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f810549df493d5..646e9bbf8af42a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1268,7 +1268,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
uint16_t *curve_settings;
int i, size = 0, ret = 0;
uint32_t curr_value = 0, value = 0, count = 0;
- uint32_t freq_values[3] = {0};
+ uint32_t freq_value[3] = {0, 0, 0};
uint32_t mark_index = 0;
struct smu_table_context *table_context = &smu->smu_table;
uint32_t gen_speed, lane_width;
@@ -1310,21 +1310,21 @@ static int navi10_print_clk_levels(struct smu_context *smu,
curr_value == value ? "*" : "");
}
} else {
- ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
+ ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_value[0]);
if (ret)
return size;
- ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
+ ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_value[2]);
if (ret)
return size;
- freq_values[1] = curr_value;
- mark_index = curr_value == freq_values[0] ? 0 :
- curr_value == freq_values[2] ? 2 : 1;
+ freq_value[1] = curr_value;
+ mark_index = curr_value == freq_value[0] ? 0 :
+ curr_value == freq_value[2] ? 2 : 1;
if (mark_index != 1)
- freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
+ freq_value[1] = (freq_value[0] + freq_value[2]) / 2;
for (i = 0; i < 3; i++) {
- size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
+ size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_value[i],
i == mark_index ? "*" : "");
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3ebded3a99b5f2..f630d5e928ccfe 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1053,7 +1053,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
(OverDriveTable_t *)table_context->overdrive_table;
int i, size = 0, ret = 0;
uint32_t curr_value = 0, value = 0, count = 0;
- uint32_t freq_values[3] = {0};
+ uint32_t freq_value[3] = {0, 0, 0};
uint32_t mark_index = 0;
uint32_t gen_speed, lane_width;
uint32_t min_value, max_value;
@@ -1096,26 +1096,26 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
curr_value == value ? "*" : "");
}
} else {
- ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
+ ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_value[0]);
if (ret)
goto print_clk_out;
- ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
+ ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_value[2]);
if (ret)
goto print_clk_out;
- freq_values[1] = curr_value;
- mark_index = curr_value == freq_values[0] ? 0 :
- curr_value == freq_values[2] ? 2 : 1;
+ freq_value[1] = curr_value;
+ mark_index = curr_value == freq_value[0] ? 0 :
+ curr_value == freq_value[2] ? 2 : 1;
count = 3;
if (mark_index != 1) {
count = 2;
- freq_values[1] = freq_values[2];
+ freq_value[1] = freq_value[2];
}
for (i = 0; i < count; i++) {
- size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
- curr_value == freq_values[i] ? "*" : "");
+ size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_value[i],
+ curr_value == freq_value[i] ? "*" : "");
}
}
--
2.33.1.558.g2bd2f258f4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] dpm/amd/pm: Sienna: 0 MHz is not a current clock frequency (v2)
2021-10-15 0:50 [PATCH 0/5] 0 MHz is not a valid current frequency (v3) Luben Tuikov
` (2 preceding siblings ...)
2021-10-15 0:50 ` [PATCH 3/5] drm/amd/pm: Rename freq_values --> freq_value Luben Tuikov
@ 2021-10-15 0:50 ` Luben Tuikov
2021-10-15 0:50 ` [PATCH 5/5] dpm/amd/pm: Navi10: " Luben Tuikov
4 siblings, 0 replies; 7+ messages in thread
From: Luben Tuikov @ 2021-10-15 0:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Luben Tuikov, Alex Deucher, Lijo Lazar
A current value of a clock frequency of 0, means
that the IP block is in some kind of low power
state. Ignore it and don't report it here. Here we
only report the possible operating (non-zero)
frequencies of the block requested. So, if the
current clock value is 0, then print the DPM
frequencies, but don't report a current value.
v2: Don't report the minimum one as the current
one when reported one is 0, i.e. don't add an
asterisk (Lijo). LT: It is conceivable that this
may confuse user-mode tools if they scan and look
for a current one, i.e. look for an asterisk, but
they'll have to adapt and use other methods for
finding power states of the chip--we can't report
0 as current.
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Lijo Lazar <Lijo.Lazar@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 60 ++++++++++++-------
1 file changed, 40 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index f630d5e928ccfe..6fe792be77dbbb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1040,7 +1040,8 @@ static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_tabl
}
static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
- enum smu_clk_type clk_type, char *buf)
+ enum smu_clk_type clk_type,
+ char *buf)
{
struct amdgpu_device *adev = smu->adev;
struct smu_table_context *table_context = &smu->smu_table;
@@ -1052,12 +1053,12 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
OverDriveTable_t *od_table =
(OverDriveTable_t *)table_context->overdrive_table;
int i, size = 0, ret = 0;
- uint32_t curr_value = 0, value = 0, count = 0;
+ uint32_t curr_value, value, count;
uint32_t freq_value[3] = {0, 0, 0};
- uint32_t mark_index = 0;
uint32_t gen_speed, lane_width;
uint32_t min_value, max_value;
uint32_t smu_version;
+ bool fine_grained;
smu_cmn_get_sysfs_buf(&buf, &size);
@@ -1077,6 +1078,20 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
if (ret)
goto print_clk_out;
+ ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0,
+ &freq_value[0]);
+ if (ret)
+ goto print_clk_out;
+
+ /* A current value of a clock frequency of 0, means
+ * that the IP block is in some kind of low power
+ * state. Ignore it and don't report it here. Here we
+ * only report the possible operating (non-zero)
+ * frequencies of the block requested. So, if the
+ * current clock value is 0, then we don't report a
+ * "current" value from the DPM states, i.e. we don't
+ * add an asterisk.
+ */
/* no need to disable gfxoff when retrieving the current gfxclk */
if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
@@ -1086,38 +1101,43 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
if (ret)
goto print_clk_out;
- if (!sienna_cichlid_supports_fine_grained_dpm(smu, clk_type)) {
- for (i = 0; i < count; i++) {
+ fine_grained = sienna_cichlid_supports_fine_grained_dpm(smu, clk_type);
+ if (!fine_grained) {
+ /* We already got the 0-th index--print it
+ * here and continue thereafter.
+ */
+ size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 0, freq_value[0],
+ curr_value == freq_value[0] ? "*" : "");
+ for (i = 1; i < count; i++) {
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
if (ret)
goto print_clk_out;
-
size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
curr_value == value ? "*" : "");
}
} else {
- ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_value[0]);
- if (ret)
- goto print_clk_out;
+ freq_value[1] = curr_value ?: freq_value[0];
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_value[2]);
if (ret)
goto print_clk_out;
- freq_value[1] = curr_value;
- mark_index = curr_value == freq_value[0] ? 0 :
- curr_value == freq_value[2] ? 2 : 1;
-
- count = 3;
- if (mark_index != 1) {
+ if (freq_value[1] == freq_value[0]) {
+ i = 1;
+ count = 3;
+ } else if (freq_value[1] == freq_value[2]) {
+ i = 0;
count = 2;
- freq_value[1] = freq_value[2];
+ } else {
+ i = 0;
+ count = 3;
}
- for (i = 0; i < count; i++) {
- size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_value[i],
- curr_value == freq_value[i] ? "*" : "");
+ for ( ; i < count; i++) {
+ size += sysfs_emit_at(buf, size,
+ "%d: %uMhz %s\n",
+ i, freq_value[i],
+ curr_value == freq_value[i] ? "*" : "");
}
-
}
break;
case SMU_PCIE:
--
2.33.1.558.g2bd2f258f4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] dpm/amd/pm: Navi10: 0 MHz is not a current clock frequency (v2)
2021-10-15 0:50 [PATCH 0/5] 0 MHz is not a valid current frequency (v3) Luben Tuikov
` (3 preceding siblings ...)
2021-10-15 0:50 ` [PATCH 4/5] dpm/amd/pm: Sienna: 0 MHz is not a current clock frequency (v2) Luben Tuikov
@ 2021-10-15 0:50 ` Luben Tuikov
4 siblings, 0 replies; 7+ messages in thread
From: Luben Tuikov @ 2021-10-15 0:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Luben Tuikov, Alex Deucher, Lijo Lazar
A current value of a clock frequency of 0, means
that the IP block is in some kind of low power
state. Ignore it and don't report it here. Here we
only report the possible operating (non-zero)
frequencies of the block requested. So, if the
current clock value is 0, then print the DPM
frequencies, but don't report a current value.
v2: Don't report the minimum one as the current
one when reported one is 0, i.e. don't add an
asterisk (Lijo). LT: It is conceivable that this
may confuse user-mode tools if they scan and look
for a current one, i.e. look for an asterisk, but
they'll have to adapt and use other methods for
finding power states of the chip--we can't report
0 as current.
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Cc: Lijo Lazar <Lijo.Lazar@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 44 ++++++++++++-------
1 file changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 646e9bbf8af42a..2af6fd336352aa 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1267,9 +1267,8 @@ static int navi10_print_clk_levels(struct smu_context *smu,
{
uint16_t *curve_settings;
int i, size = 0, ret = 0;
- uint32_t curr_value = 0, value = 0, count = 0;
+ uint32_t curr_value, value, count;
uint32_t freq_value[3] = {0, 0, 0};
- uint32_t mark_index = 0;
struct smu_table_context *table_context = &smu->smu_table;
uint32_t gen_speed, lane_width;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
@@ -1279,6 +1278,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
(OverDriveTable_t *)table_context->overdrive_table;
struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
uint32_t min_value, max_value;
+ bool fine_grained;
smu_cmn_get_sysfs_buf(&buf, &size);
@@ -1296,12 +1296,20 @@ static int navi10_print_clk_levels(struct smu_context *smu,
if (ret)
return size;
+ ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0,
+ &freq_value[0]);
+ if (ret)
+ return size;
+
ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
if (ret)
return size;
- if (!navi10_supports_fine_grained_dpm(smu, clk_type)) {
- for (i = 0; i < count; i++) {
+ fine_grained = navi10_supports_fine_grained_dpm(smu, clk_type);
+ if (!fine_grained) {
+ size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 0, freq_value[0],
+ curr_value == freq_value[0] ? "*" : "");
+ for (i = 1; i < count; i++) {
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
if (ret)
return size;
@@ -1310,24 +1318,28 @@ static int navi10_print_clk_levels(struct smu_context *smu,
curr_value == value ? "*" : "");
}
} else {
- ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_value[0]);
- if (ret)
- return size;
+ freq_value[1] = curr_value ?: freq_value[0];
ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_value[2]);
if (ret)
return size;
- freq_value[1] = curr_value;
- mark_index = curr_value == freq_value[0] ? 0 :
- curr_value == freq_value[2] ? 2 : 1;
- if (mark_index != 1)
- freq_value[1] = (freq_value[0] + freq_value[2]) / 2;
-
- for (i = 0; i < 3; i++) {
- size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_value[i],
- i == mark_index ? "*" : "");
+ if (freq_value[1] == freq_value[0]) {
+ i = 1;
+ count = 3;
+ } else if (freq_value[1] == freq_value[2]) {
+ i = 0;
+ count = 2;
+ } else {
+ i = 0;
+ count = 3;
}
+ for ( ; i < count; i++) {
+ size += sysfs_emit_at(buf, size,
+ "%d: %uMhz %s\n",
+ i, freq_value[i],
+ curr_value == freq_value[i] ? "*" : "");
+ }
}
break;
case SMU_PCIE:
--
2.33.1.558.g2bd2f258f4
^ permalink raw reply related [flat|nested] 7+ messages in thread