From: Suzuki K Poulose <suzuki.poulose@arm.com> To: will@kernel.org, mathieu.poirier@linaro.org Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v6 07/15] coresight: trbe: Decouple buffer base from the hardware base Date: Tue, 19 Oct 2021 17:31:45 +0100 [thread overview] Message-ID: <20211019163153.3692640-8-suzuki.poulose@arm.com> (raw) In-Reply-To: <20211019163153.3692640-1-suzuki.poulose@arm.com> We always set the TRBBASER_EL1 to the base of the virtual ring buffer. We are about to change this for working around an erratum. So, in preparation to that, allow the driver to choose a different base for the TRBBASER_EL1 (which is within the buffer range). Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index e3767f21ee68..ae0bde9630f6 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -57,6 +57,8 @@ struct trbe_buf { * trbe_limit sibling pointers. */ unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; int nr_pages; @@ -470,12 +472,13 @@ static void set_trbe_limit_pointer_enabled(unsigned long addr) static void trbe_enable_hw(struct trbe_buf *buf) { - WARN_ON(buf->trbe_write < buf->trbe_base); + WARN_ON(buf->trbe_hw_base < buf->trbe_base); + WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >= buf->trbe_limit); set_trbe_disabled(); isb(); clr_trbe_status(); - set_trbe_base_pointer(buf->trbe_base); + set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); /* @@ -520,7 +523,12 @@ static unsigned long trbe_get_trace_size(struct perf_output_handle *handle, else write = get_trbe_write_pointer(); - end_off = write - get_trbe_base_pointer(); + /* + * TRBE may use a different base address than the base + * of the ring buffer. Thus use the beginning of the ring + * buffer to compute the offsets. + */ + end_off = write - buf->trbe_base; start_off = PERF_IDX2OFF(handle->head, buf); if (WARN_ON_ONCE(end_off < start_off)) @@ -678,6 +686,8 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_stop_and_truncate_event(handle); return -ENOSPC; } + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; trbe_enable_hw(buf); return 0; @@ -771,7 +781,7 @@ static bool is_perf_trbe(struct perf_output_handle *handle) struct trbe_drvdata *drvdata = cpudata->drvdata; int cpu = smp_processor_id(); - WARN_ON(buf->trbe_base != get_trbe_base_pointer()); + WARN_ON(buf->trbe_hw_base != get_trbe_base_pointer()); WARN_ON(buf->trbe_limit != get_trbe_limit_pointer()); if (cpudata->mode != CS_MODE_PERF) -- 2.25.4
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: will@kernel.org, mathieu.poirier@linaro.org Cc: catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v6 07/15] coresight: trbe: Decouple buffer base from the hardware base Date: Tue, 19 Oct 2021 17:31:45 +0100 [thread overview] Message-ID: <20211019163153.3692640-8-suzuki.poulose@arm.com> (raw) In-Reply-To: <20211019163153.3692640-1-suzuki.poulose@arm.com> We always set the TRBBASER_EL1 to the base of the virtual ring buffer. We are about to change this for working around an erratum. So, in preparation to that, allow the driver to choose a different base for the TRBBASER_EL1 (which is within the buffer range). Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index e3767f21ee68..ae0bde9630f6 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -57,6 +57,8 @@ struct trbe_buf { * trbe_limit sibling pointers. */ unsigned long trbe_base; + /* The base programmed into the TRBE */ + unsigned long trbe_hw_base; unsigned long trbe_limit; unsigned long trbe_write; int nr_pages; @@ -470,12 +472,13 @@ static void set_trbe_limit_pointer_enabled(unsigned long addr) static void trbe_enable_hw(struct trbe_buf *buf) { - WARN_ON(buf->trbe_write < buf->trbe_base); + WARN_ON(buf->trbe_hw_base < buf->trbe_base); + WARN_ON(buf->trbe_write < buf->trbe_hw_base); WARN_ON(buf->trbe_write >= buf->trbe_limit); set_trbe_disabled(); isb(); clr_trbe_status(); - set_trbe_base_pointer(buf->trbe_base); + set_trbe_base_pointer(buf->trbe_hw_base); set_trbe_write_pointer(buf->trbe_write); /* @@ -520,7 +523,12 @@ static unsigned long trbe_get_trace_size(struct perf_output_handle *handle, else write = get_trbe_write_pointer(); - end_off = write - get_trbe_base_pointer(); + /* + * TRBE may use a different base address than the base + * of the ring buffer. Thus use the beginning of the ring + * buffer to compute the offsets. + */ + end_off = write - buf->trbe_base; start_off = PERF_IDX2OFF(handle->head, buf); if (WARN_ON_ONCE(end_off < start_off)) @@ -678,6 +686,8 @@ static int __arm_trbe_enable(struct trbe_buf *buf, trbe_stop_and_truncate_event(handle); return -ENOSPC; } + /* Set the base of the TRBE to the buffer base */ + buf->trbe_hw_base = buf->trbe_base; *this_cpu_ptr(buf->cpudata->drvdata->handle) = handle; trbe_enable_hw(buf); return 0; @@ -771,7 +781,7 @@ static bool is_perf_trbe(struct perf_output_handle *handle) struct trbe_drvdata *drvdata = cpudata->drvdata; int cpu = smp_processor_id(); - WARN_ON(buf->trbe_base != get_trbe_base_pointer()); + WARN_ON(buf->trbe_hw_base != get_trbe_base_pointer()); WARN_ON(buf->trbe_limit != get_trbe_limit_pointer()); if (cpudata->mode != CS_MODE_PERF) -- 2.25.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-19 16:33 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-19 16:31 [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose [this message] 2021-10-19 16:31 ` [PATCH v6 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-20 15:42 ` [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Mathieu Poirier 2021-10-20 15:42 ` Mathieu Poirier 2021-10-21 8:53 ` Will Deacon 2021-10-21 8:53 ` Will Deacon 2021-10-21 16:35 ` Mathieu Poirier 2021-10-21 16:35 ` Mathieu Poirier 2021-10-21 16:47 ` Will Deacon 2021-10-21 16:47 ` Will Deacon 2021-10-21 17:11 ` Mathieu Poirier 2021-10-21 17:11 ` Mathieu Poirier 2021-10-21 21:42 ` Suzuki K Poulose 2021-10-21 21:42 ` Suzuki K Poulose 2021-10-22 7:14 ` Greg KH 2021-10-22 7:14 ` Greg KH 2021-10-22 15:13 ` Mathieu Poirier 2021-10-22 15:13 ` Mathieu Poirier 2021-10-22 15:27 ` Mathieu Poirier 2021-10-22 15:27 ` Mathieu Poirier 2021-10-23 8:58 ` Greg KH 2021-10-23 8:58 ` Greg KH 2021-10-21 17:11 ` Will Deacon 2021-10-21 17:11 ` Will Deacon
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