From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Will Deacon <will@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>, catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Date: Thu, 21 Oct 2021 10:35:31 -0600 [thread overview] Message-ID: <20211021163531.GA3561043@p14s> (raw) In-Reply-To: <20211021085313.GA15622@willie-the-truck> On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > Suzuki K Poulose (15): > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > arm64: errata: Add workaround for TSB flush failures > > > arm64: errata: Add detection for TRBE write to out-of-range > > > coresight: trbe: Add a helper to calculate the trace generated > > > coresight: trbe: Add a helper to pad a given buffer area > > > coresight: trbe: Decouple buffer base from the hardware base > > > coresight: trbe: Allow driver to choose a different alignment > > > coresight: trbe: Add infrastructure for Errata handling > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > coresight: trbe: Make sure we have enough space > > > coresight: trbe: Work around write to out of range > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > address > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > arch/arm64/Kconfig | 111 ++++++ > > > arch/arm64/include/asm/barrier.h | 16 +- > > > arch/arm64/include/asm/cputype.h | 4 + > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > I have applied this set. > > Mathieu -- the plan here (which we have discussed on the list [1]) is > for the first four patches to be shared with arm64. Since you've gone > ahead and applied the whole series, please can you provide me a stable > branch with the first four patches only so that I can include them in > the arm64 tree? > > Failing that, I can create a branch for you to pull and apply the remaining > patches on top. > > Please let me know. Coresight patches flow through Greg's tree and as such the coresight-next tree gets rebased anyway. I will remove the first 4 patches and push again. By the way do you also want to pick up patches 14 and 16 since they are concerned with "arch/arm64/Kconfig" or should I keep them? Thanks, Mathieu > > Thanks, > > Will > > [1] https://lore.kernel.org/all/20211008073229.GB32625@willie-the-truck/
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org> To: Will Deacon <will@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>, catalin.marinas@arm.com, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Date: Thu, 21 Oct 2021 10:35:31 -0600 [thread overview] Message-ID: <20211021163531.GA3561043@p14s> (raw) In-Reply-To: <20211021085313.GA15622@willie-the-truck> On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > Suzuki K Poulose (15): > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > arm64: errata: Add workaround for TSB flush failures > > > arm64: errata: Add detection for TRBE write to out-of-range > > > coresight: trbe: Add a helper to calculate the trace generated > > > coresight: trbe: Add a helper to pad a given buffer area > > > coresight: trbe: Decouple buffer base from the hardware base > > > coresight: trbe: Allow driver to choose a different alignment > > > coresight: trbe: Add infrastructure for Errata handling > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > coresight: trbe: Make sure we have enough space > > > coresight: trbe: Work around write to out of range > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > address > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > arch/arm64/Kconfig | 111 ++++++ > > > arch/arm64/include/asm/barrier.h | 16 +- > > > arch/arm64/include/asm/cputype.h | 4 + > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > I have applied this set. > > Mathieu -- the plan here (which we have discussed on the list [1]) is > for the first four patches to be shared with arm64. Since you've gone > ahead and applied the whole series, please can you provide me a stable > branch with the first four patches only so that I can include them in > the arm64 tree? > > Failing that, I can create a branch for you to pull and apply the remaining > patches on top. > > Please let me know. Coresight patches flow through Greg's tree and as such the coresight-next tree gets rebased anyway. I will remove the first 4 patches and push again. By the way do you also want to pick up patches 14 and 16 since they are concerned with "arch/arm64/Kconfig" or should I keep them? Thanks, Mathieu > > Thanks, > > Will > > [1] https://lore.kernel.org/all/20211008073229.GB32625@willie-the-truck/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-21 16:35 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-19 16:31 [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 01/15] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 03/15] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 04/15] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 05/15] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 06/15] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 07/15] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 08/15] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 09/15] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 10/15] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 11/15] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 12/15] coresight: trbe: Make sure we have enough space Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 13/15] coresight: trbe: Work around write to out of range Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 14/15] arm64: errata: Enable workaround for TRBE overwrite in FILL mode Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-19 16:31 ` [PATCH v6 15/15] arm64: errata: Enable TRBE workaround for write to out-of-range address Suzuki K Poulose 2021-10-19 16:31 ` Suzuki K Poulose 2021-10-20 15:42 ` [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds Mathieu Poirier 2021-10-20 15:42 ` Mathieu Poirier 2021-10-21 8:53 ` Will Deacon 2021-10-21 8:53 ` Will Deacon 2021-10-21 16:35 ` Mathieu Poirier [this message] 2021-10-21 16:35 ` Mathieu Poirier 2021-10-21 16:47 ` Will Deacon 2021-10-21 16:47 ` Will Deacon 2021-10-21 17:11 ` Mathieu Poirier 2021-10-21 17:11 ` Mathieu Poirier 2021-10-21 21:42 ` Suzuki K Poulose 2021-10-21 21:42 ` Suzuki K Poulose 2021-10-22 7:14 ` Greg KH 2021-10-22 7:14 ` Greg KH 2021-10-22 15:13 ` Mathieu Poirier 2021-10-22 15:13 ` Mathieu Poirier 2021-10-22 15:27 ` Mathieu Poirier 2021-10-22 15:27 ` Mathieu Poirier 2021-10-23 8:58 ` Greg KH 2021-10-23 8:58 ` Greg KH 2021-10-21 17:11 ` Will Deacon 2021-10-21 17:11 ` Will Deacon
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