From: Christoph Hellwig <hch@lst.de>
To: Wei Fu <wefu@redhat.com>
Cc: "Guo Ren" <guoren@kernel.org>, "Christoph Hellwig" <hch@lst.de>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Anup Patel" <Anup.Patel@wdc.com>,
"Atish Patra" <Atish.Patra@wdc.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
liush <liush@allwinnertech.com>,
"Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com,
"Aniket Ponkshe" <aniket.ponkshe@canonical.com>,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
"Gordan Markus" <gordan.markus@canonical.com>,
"Guo Ren" <guoren@linux.alibaba.com>,
"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
"Xinhaoqu (Freddie)" <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports
Date: Mon, 8 Nov 2021 08:52:44 +0100 [thread overview]
Message-ID: <20211108075244.GA26350@lst.de> (raw)
In-Reply-To: <CA+YCwK=vMtKC0DrhSJ7apgZ4s4_8fzGoRxY2mKEjjyJZjNW2QQ@mail.gmail.com>
On Sun, Nov 07, 2021 at 03:12:51PM +0800, Wei Fu wrote:
> How about
>
> config RISCV_SVPBMT
> bool
> depends on 64BIT && MMU
> default y
Yes. You can shorten this a bit more using def_bool if you want.
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Wei Fu <wefu@redhat.com>
Cc: "Guo Ren" <guoren@kernel.org>, "Christoph Hellwig" <hch@lst.de>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Anup Patel" <Anup.Patel@wdc.com>,
"Atish Patra" <Atish.Patra@wdc.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
liush <liush@allwinnertech.com>,
"Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com,
"Aniket Ponkshe" <aniket.ponkshe@canonical.com>,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
"Gordan Markus" <gordan.markus@canonical.com>,
"Guo Ren" <guoren@linux.alibaba.com>,
"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
"Xinhaoqu (Freddie)" <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports
Date: Mon, 8 Nov 2021 08:52:44 +0100 [thread overview]
Message-ID: <20211108075244.GA26350@lst.de> (raw)
In-Reply-To: <CA+YCwK=vMtKC0DrhSJ7apgZ4s4_8fzGoRxY2mKEjjyJZjNW2QQ@mail.gmail.com>
On Sun, Nov 07, 2021 at 03:12:51PM +0800, Wei Fu wrote:
> How about
>
> config RISCV_SVPBMT
> bool
> depends on 64BIT && MMU
> default y
Yes. You can shorten this a bit more using def_bool if you want.
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next prev parent reply other threads:[~2021-11-08 7:52 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 4:06 [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu
2021-10-25 4:06 ` wefu
2021-10-25 4:06 ` [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt wefu
2021-10-25 4:06 ` wefu
2021-10-25 4:17 ` Anup Patel
2021-10-25 4:17 ` Anup Patel
2021-10-25 6:00 ` Guo Ren
2021-10-25 6:00 ` Guo Ren
2021-10-25 6:08 ` Anup Patel
2021-10-25 6:08 ` Anup Patel
2021-10-25 13:21 ` Philipp Tomsich
2021-10-25 13:21 ` Philipp Tomsich
2021-10-25 6:09 ` Guo Ren
2021-10-25 6:09 ` Guo Ren
2021-10-25 4:06 ` [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports wefu
2021-10-25 4:06 ` wefu
2021-10-25 6:55 ` Christoph Hellwig
2021-10-25 6:55 ` Christoph Hellwig
2021-10-25 10:55 ` Wei Fu
2021-10-25 10:55 ` Wei Fu
2021-11-02 6:07 ` Christoph Hellwig
2021-11-02 6:07 ` Christoph Hellwig
2021-11-07 7:23 ` Wei Fu
2021-11-07 7:23 ` Wei Fu
2021-10-25 14:49 ` Wei Fu
2021-10-25 14:49 ` Wei Fu
2021-11-02 6:04 ` Christoph Hellwig
2021-11-02 6:04 ` Christoph Hellwig
2021-11-07 6:54 ` Wei Fu
2021-11-07 6:54 ` Wei Fu
2021-10-27 0:12 ` [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Palmer Dabbelt
2021-10-27 0:12 ` Palmer Dabbelt
2021-10-27 7:54 ` Heinrich Schuchardt
2021-10-27 7:54 ` Heinrich Schuchardt
2021-11-02 2:07 ` Guo Ren
2021-11-02 2:07 ` Guo Ren
2021-11-02 5:58 ` Christoph Hellwig
2021-11-02 5:58 ` Christoph Hellwig
2021-11-02 8:51 ` Guo Ren
2021-11-02 8:51 ` Guo Ren
2021-11-07 7:12 ` Wei Fu
2021-11-07 7:12 ` Wei Fu
2021-11-08 7:52 ` Christoph Hellwig [this message]
2021-11-08 7:52 ` Christoph Hellwig
2021-11-26 16:23 ` Wei Fu
2021-11-26 16:23 ` Wei Fu
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